mb/system76/adl-p: oryp9: Enable dGPU
Change-Id: If78241c197a552a5d93e4bfdadcb175d68194e3d Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
@@ -3,6 +3,7 @@ if BOARD_SYSTEM76_DARP8 || BOARD_SYSTEM76_LEMP11 || BOARD_SYSTEM76_ORYP9
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config BOARD_SPECIFIC_OPTIONS
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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def_bool y
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select BOARD_ROMSIZE_KB_32768
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select BOARD_ROMSIZE_KB_32768
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select DRIVERS_GFX_NVIDIA if BOARD_SYSTEM76_ORYP9
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select DRIVERS_I2C_HID
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select DRIVERS_I2C_HID
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select DRIVERS_INTEL_PMC
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select DRIVERS_INTEL_PMC
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select DRIVERS_INTEL_USB4_RETIMER
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select DRIVERS_INTEL_USB4_RETIMER
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@@ -1,4 +1,5 @@
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
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bootblock-y += bootblock.c
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bootblock-y += bootblock.c
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bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
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bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
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@@ -1,5 +1,9 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* SPDX-License-Identifier: GPL-2.0-only */
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#if CONFIG(DRIVERS_GFX_NVIDIA)
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#include <variant/gpio.h>
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#endif
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#define EC_GPE_SCI 0x6E
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#define EC_GPE_SCI 0x6E
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#define EC_GPE_SWI 0x6B
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#define EC_GPE_SWI 0x6B
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#include <ec/system76/ec/acpi/ec.asl>
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#include <ec/system76/ec/acpi/ec.asl>
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@@ -8,5 +12,11 @@ Scope (\_SB) {
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#include "sleep.asl"
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#include "sleep.asl"
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Scope (PCI0) {
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Scope (PCI0) {
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#include "backlight.asl"
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#include "backlight.asl"
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#if CONFIG(DRIVERS_GFX_NVIDIA)
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Scope (PEG2) {
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#include <drivers/gfx/nvidia/acpi/tigerlake.asl>
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}
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#endif
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}
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}
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}
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}
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@@ -0,0 +1,13 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef VARIANT_GPIO_H
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#define VARIANT_GPIO_H
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#include <soc/gpio.h>
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#define DGPU_RST_N GPP_B2
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#define DGPU_PWR_EN GPP_A14
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#define DGPU_GC6 GPP_A7
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#define DGPU_SSID 0x65f51558
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#endif
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@@ -18,13 +18,17 @@ chip soc/intel/alderlake
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device domain 0 on
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device domain 0 on
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subsystemid 0x1558 0x65f5 inherit
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subsystemid 0x1558 0x65f5 inherit
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device ref pcie5 off
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device ref pcie5 on
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# CPU PCIe RP#2 x8, Clock 3 (DGPU)
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# CPU PCIe RP#2 x8, Clock 3 (DGPU)
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register "cpu_pcie_rp[CPU_RP(2)]" = "{
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register "cpu_pcie_rp[CPU_RP(2)]" = "{
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.clk_src = 3,
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.clk_src = 3,
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.clk_req = 3,
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.clk_req = 3,
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.flags = PCIE_RP_LTR,
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.flags = PCIE_RP_LTR,
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}"
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}"
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chip drivers/gfx/nvidia
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device pci 00.0 on end # VGA controller
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device pci 00.1 on end # Audio device
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end
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end
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end
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device ref igpu on
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device ref igpu on
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register "ddi_portA_config" = "1"
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register "ddi_portA_config" = "1"
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@@ -1,7 +1,9 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <drivers/gfx/nvidia/gpu.h>
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#include <soc/meminit.h>
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#include <soc/meminit.h>
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#include <soc/romstage.h>
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#include <soc/romstage.h>
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#include <variant/gpio.h>
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void mainboard_memory_init_params(FSPM_UPD *mupd)
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void mainboard_memory_init_params(FSPM_UPD *mupd)
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{
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{
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@@ -18,6 +20,17 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
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};
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};
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const bool half_populated = false;
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const bool half_populated = false;
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const struct nvidia_gpu_config config = {
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.power_gpio = DGPU_PWR_EN,
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.reset_gpio = DGPU_RST_N,
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.enable = true,
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};
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// Enable dGPU power
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nvidia_set_power(&config);
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// Set primary display to internal graphics
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mupd->FspmConfig.PrimaryDisplay = 0;
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mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1;
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mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1;
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mupd->FspmConfig.DmiMaxLinkSpeed = 4;
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mupd->FspmConfig.DmiMaxLinkSpeed = 4;
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mupd->FspmConfig.GpioOverride = 0;
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mupd->FspmConfig.GpioOverride = 0;
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