mb/amd/birman: Update DXIO descriptors per schematic
Update DXIO descriptors for birman-phoenix per schematic 105-D67000-00B v0.7 Update devicetree to reference the updated DXIO descriptors. TEST=boot birman and note the devices show up in the logs correctly Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I76cf6715b60a1857bf58349d70a623bf043594fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/69705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Felix Held
parent
03ff5db8b8
commit
c706880bfe
@@ -151,16 +151,23 @@ chip soc/amd/phoenix
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.PhyP3CpmP4Support = 0,
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}"
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register "gpp_clk_config[0]" = "GPP_CLK_REQ"
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register "gpp_clk_config[1]" = "GPP_CLK_REQ"
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register "gpp_clk_config[2]" = "GPP_CLK_OFF"
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register "gpp_clk_config[3]" = "GPP_CLK_REQ"
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register "gpp_clk_config[0]" = "GPP_CLK_REQ" # MXM
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register "gpp_clk_config[1]" = "GPP_CLK_REQ" # NVMe SSD1
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register "gpp_clk_config[2]" = "GPP_CLK_REQ" # NVMe SSD0
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register "gpp_clk_config[3]" = "GPP_CLK_REQ" # WLAN
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register "gpp_clk_config[4]" = "GPP_CLK_REQ" # WWAN
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register "gpp_clk_config[5]" = "GPP_CLK_REQ" # SD
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register "gpp_clk_config[6]" = "GPP_CLK_REQ" # GBE
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device domain 0 on
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device ref iommu on end
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device ref gpp_bridge_2_1 on end # GBE
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device ref gpp_bridge_2_2 on end # WIFI
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device ref gpp_bridge_2_3 on end # NVMe SSD
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device ref gpp_bridge_1_1 on end # MXM
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device ref gpp_bridge_1_2 on end # NVMe SSD1
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device ref gpp_bridge_1_3 on end # GBE
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device ref gpp_bridge_2_1 on end # SD
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device ref gpp_bridge_2_2 on end # WWAN
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device ref gpp_bridge_2_3 on end # WIFI
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device ref gpp_bridge_2_4 on end # NVMe SSD0
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device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A
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device ref gfx on end # Internal GPU (GFX)
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device ref gfx_hda on end # Display HD Audio Controller (GFXAZ)
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@@ -4,52 +4,136 @@
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#include <device/i2c_simple.h>
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#include <gpio.h>
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#include <soc/platform_descriptors.h>
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#include <soc/soc_util.h>
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#include <types.h>
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/* TODO: Update for birman */
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#define phx_mxm_dxio_descriptor { \
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.engine_type = PCIE_ENGINE, \
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.port_present = CONFIG(ENABLE_EVAL_CARD), \
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.start_logical_lane = 0, \
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.end_logical_lane = 7, \
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.device_number = 1, \
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.function_number = 1, \
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.link_speed_capability = GEN3, \
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.turn_off_unused_lanes = true, \
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.link_aspm = ASPM_L1, \
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.link_hotplug = 0, \
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.clk_req = CLK_REQ0, \
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}
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static const fsp_dxio_descriptor birman_dxio_descriptors[] = {
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{
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.engine_type = PCIE_ENGINE,
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.port_present = true,
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.start_logical_lane = 0,
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.end_logical_lane = 0,
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.device_number = 2,
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.function_number = 1,
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.link_speed_capability = GEN3,
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.turn_off_unused_lanes = true,
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.link_aspm = 2,
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.link_hotplug = 3,
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.clk_req = CLK_REQ3,
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},
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{
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.engine_type = PCIE_ENGINE,
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.port_present = true,
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.start_logical_lane = 1,
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.end_logical_lane = 1,
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.device_number = 2,
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.function_number = 2,
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.link_speed_capability = GEN3,
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.turn_off_unused_lanes = true,
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.link_aspm = 2,
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.link_hotplug = 3,
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.clk_req = CLK_REQ1,
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},
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{
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.engine_type = PCIE_ENGINE,
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.port_present = true,
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.start_logical_lane = 2,
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.end_logical_lane = 3,
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.device_number = 2,
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.function_number = 3,
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.link_speed_capability = GEN3,
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.turn_off_unused_lanes = true,
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.link_aspm = 2,
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.link_hotplug = 3,
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.gpio_group_id = GPIO_27,
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.clk_req = CLK_REQ0,
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},
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};
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/* TODO: verify on hardware */
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#define phx2_mxm_dxio_descriptor { \
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.engine_type = PCIE_ENGINE, \
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.port_present = CONFIG(ENABLE_EVAL_CARD), \
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.start_logical_lane = 0, \
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.end_logical_lane = 3, \
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.device_number = 1, \
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.function_number = 1, \
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.link_speed_capability = GEN3, \
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.turn_off_unused_lanes = true, \
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.link_aspm = ASPM_L1, \
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.link_hotplug = 0, \
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.clk_req = CLK_REQ0, \
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}
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#define phx_ssd1_dxio_descriptor { \
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.engine_type = PCIE_ENGINE, \
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.port_present = !CONFIG(DISABLE_DT_M2), \
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.start_logical_lane = 8, \
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.end_logical_lane = 11, \
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.device_number = 1, \
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.function_number = 2, \
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.link_speed_capability = GEN3, \
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.turn_off_unused_lanes = true, \
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.link_aspm = ASPM_L1, \
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.link_hotplug = 0, \
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.clk_req = CLK_REQ1, \
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}
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/* TODO: verify on hardware */
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#define phx2_ssd1_dxio_descriptor { \
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.engine_type = PCIE_ENGINE, \
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.port_present = true, \
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.start_logical_lane = 8, \
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.end_logical_lane = 9, \
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.device_number = 1, \
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.function_number = 2, \
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.link_speed_capability = GEN3, \
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.turn_off_unused_lanes = true, \
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.link_aspm = ASPM_L1, \
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.link_hotplug = 0, \
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.clk_req = CLK_REQ1, \
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}
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#define gbe_dxio_descriptor { \
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.engine_type = PCIE_ENGINE, \
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.port_present = true, \
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.start_logical_lane = 12, \
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.end_logical_lane = 12, \
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.device_number = 1, \
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.function_number = 3, \
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.link_speed_capability = GEN3, \
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.turn_off_unused_lanes = true, \
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.link_aspm = ASPM_L1, \
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.link_hotplug = 0, \
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.clk_req = CLK_REQ6, \
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}
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#define sd_dxio_descriptor { \
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.engine_type = PCIE_ENGINE, \
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.port_present = true, \
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.start_logical_lane = 13, \
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.end_logical_lane = 13, \
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.device_number = 2, \
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.function_number = 1, \
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.link_speed_capability = GEN3, \
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.turn_off_unused_lanes = true, \
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.link_aspm = ASPM_L1, \
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.link_hotplug = 0, \
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.clk_req = CLK_REQ5, \
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}
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#define wwan_dxio_descriptor { \
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.engine_type = PCIE_ENGINE, \
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.port_present = true, \
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.start_logical_lane = 14, \
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.end_logical_lane = CONFIG(WWAN01) ? 15 : 14, \
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.device_number = 2, \
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.function_number = 2, \
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.link_speed_capability = GEN3, \
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.turn_off_unused_lanes = true, \
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.link_aspm = ASPM_L1, \
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.link_hotplug = 0, \
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.clk_req = CLK_REQ4, \
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}
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#define wlan_dxio_descriptor { \
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.engine_type = PCIE_ENGINE, \
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.port_present = true, \
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.start_logical_lane = 15, \
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.end_logical_lane = CONFIG(WLAN01) ? 14 : 15, \
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.device_number = 2, \
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.function_number = 3, \
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.link_speed_capability = GEN3, \
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.turn_off_unused_lanes = true, \
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.link_aspm = ASPM_L1, \
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.link_hotplug = 0, \
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.clk_req = CLK_REQ3, \
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}
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#define ssd0_dxio_descriptor { \
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.engine_type = PCIE_ENGINE, \
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.port_present = true, \
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.start_logical_lane = 16, \
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.end_logical_lane = 19, \
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.device_number = 2, \
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.function_number = 4, \
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.link_speed_capability = GEN3, \
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.turn_off_unused_lanes = true, \
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.link_aspm = ASPM_L1, \
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.link_hotplug = 0, \
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.clk_req = CLK_REQ2, \
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}
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static fsp_ddi_descriptor birman_ddi_descriptors[] = {
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{ /* DDI0 - eDP */
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@@ -123,8 +207,44 @@ void mainboard_get_dxio_ddi_descriptors(
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{
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birman_ddi_descriptors[1].connector_type = get_ddi1_type();
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*dxio_descs = birman_dxio_descriptors;
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*dxio_num = ARRAY_SIZE(birman_dxio_descriptors);
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enum soc_type type = get_soc_type();
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if (type == SOC_PHOENIX) {
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printk(BIOS_DEBUG, "Using PHX DXIO\n");
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static const fsp_dxio_descriptor birman_phx_dxio_descriptors[] = {
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phx_mxm_dxio_descriptor,
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phx_ssd1_dxio_descriptor,
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gbe_dxio_descriptor,
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sd_dxio_descriptor,
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#if CONFIG(WLAN0_WWAN0) || CONFIG(WWAN01)
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wwan_dxio_descriptor,
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#endif
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#if CONFIG(WLAN0_WWAN0) || CONFIG(WLAN01)
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wlan_dxio_descriptor,
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#endif
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ssd0_dxio_descriptor,
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};
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*dxio_descs = birman_phx_dxio_descriptors;
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*dxio_num = ARRAY_SIZE(birman_phx_dxio_descriptors);
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} else {
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printk(BIOS_DEBUG, "Using PHX2 DXIO\n");
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static const fsp_dxio_descriptor birman_phx2_dxio_descriptors[] = {
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phx2_mxm_dxio_descriptor,
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phx2_ssd1_dxio_descriptor,
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gbe_dxio_descriptor,
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sd_dxio_descriptor,
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#if CONFIG(WLAN0_WWAN0) || CONFIG(WWAN01)
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wwan_dxio_descriptor,
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#endif
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#if CONFIG(WLAN0_WWAN0) || CONFIG(WLAN01)
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wlan_dxio_descriptor,
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#endif
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ssd0_dxio_descriptor,
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};
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*dxio_descs = birman_phx2_dxio_descriptors;
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*dxio_num = ARRAY_SIZE(birman_phx2_dxio_descriptors);
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}
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*ddi_descs = birman_ddi_descriptors;
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*ddi_num = ARRAY_SIZE(birman_ddi_descriptors);
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}
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