cpu/x86: Make 1GB paging the default

This patch flips the polarity of CONFIG_USE_1G_PAGES_TLB into
CONFIG_NEED_SMALL_2MB_PAGE_TABLES which is off by default, meaning
CPUs added in the future will automatically build the smaller 1GB pages.
We can expect support for this feature to be available on all future CPU
generations (with the possible exception of embedded edge cases), so
this default setting should make mistakes less likely and keep
maintenance effort lower. (Besides, enabling the support where it
doesn't work fails fast, whereas keeping it disabled where it could work
is an inefficiency that can easily go overlooked for a long time.)

While this is technically a CPU feature, not a northbridge feature, we
support a lot more individual CPUs than northbridges in the pre-SoC era,
and they tend to be closely coupled anyway. So select the option at the
northbridge level for older CPUs to keep things simpler.

Change-Id: I2cf1237a7fb63b8904c2a3d57fead162c66bacde
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

src/cpu/qemu-x86/Kconfig

@@ -7,6 +7,7 @@ config CPU_QEMU_X86
 	select UDELAY_TSC
 	select TSC_MONOTONIC_TIMER
 	select UNKNOWN_TSC_RATE
+	select NEED_SMALL_2MB_PAGE_TABLES	# QEMU doesn't support 1GB pages
 
 if CPU_QEMU_X86
 

src/cpu/x86/64bit/Makefile.mk

@@ -3,10 +3,10 @@
 all_x86-y += mode_switch.S
 all_x86-y += mode_switch2.S
 
-ifeq ($(CONFIG_USE_1G_PAGES_TLB),y)
-PAGETABLE_SRC := pt1G.S
-else
+ifeq ($(CONFIG_NEED_SMALL_2MB_PAGE_TABLES),y)
 PAGETABLE_SRC := pt.S
+else
+PAGETABLE_SRC := pt1G.S
 endif
 
 all_x86-y += $(PAGETABLE_SRC)

src/cpu/x86/Kconfig

@@ -152,12 +152,12 @@ config NO_SMM
 	bool
 	default n
 
-config USE_1G_PAGES_TLB
+config NEED_SMALL_2MB_PAGE_TABLES
 	bool
 	default n
 	help
-	  Select this option to enable access to up to 512 GiB of memory
-	  by using 1 GiB large pages.
+	  Select this option from boards/SoCs that do not support the Page1GB
+	  CPUID feature (CPUID.80000001H:EDX.bit26).
 
 config SMM_ASEG
 	bool

src/northbridge/intel/e7505/Kconfig

@@ -6,3 +6,4 @@ config NORTHBRIDGE_INTEL_E7505
 	select HAVE_DEBUG_RAM_SETUP
 	select NO_CBFS_MCACHE
 	select SMM_TSEG
+	select NEED_SMALL_2MB_PAGE_TABLES

src/northbridge/intel/gm45/Kconfig

@@ -10,6 +10,7 @@ config NORTHBRIDGE_INTEL_GM45
 	select HAVE_X86_64_SUPPORT
 	select USE_DDR3
 	select USE_DDR2
+	select NEED_SMALL_2MB_PAGE_TABLES
 
 if NORTHBRIDGE_INTEL_GM45
 

src/northbridge/intel/i440bx/Kconfig

@@ -5,6 +5,7 @@ config NORTHBRIDGE_INTEL_I440BX
 	select NO_ECAM_MMCONF_SUPPORT
 	select HAVE_DEBUG_RAM_SETUP
 	select NO_CBFS_MCACHE
+	select NEED_SMALL_2MB_PAGE_TABLES
 
 config SDRAMPWR_4DIMM
 	bool

src/northbridge/intel/i945/Kconfig

@@ -9,6 +9,7 @@ config NORTHBRIDGE_INTEL_I945
 	select INTEL_EDID
 	select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
 	select USE_DDR2
+	select NEED_SMALL_2MB_PAGE_TABLES
 
 if NORTHBRIDGE_INTEL_I945
 

src/northbridge/intel/ironlake/Kconfig

@@ -9,6 +9,7 @@ config NORTHBRIDGE_INTEL_IRONLAKE
 	select CACHE_MRC_SETTINGS
 	select HAVE_DEBUG_RAM_SETUP
 	select USE_DDR3
+	select NEED_SMALL_2MB_PAGE_TABLES
 
 if NORTHBRIDGE_INTEL_IRONLAKE
 

src/northbridge/intel/pineview/Kconfig

@@ -10,6 +10,7 @@ config NORTHBRIDGE_INTEL_PINEVIEW
 	select INTEL_GMA_ACPI
 	select USE_DDR3
 	select USE_DDR2
+	select NEED_SMALL_2MB_PAGE_TABLES
 
 if NORTHBRIDGE_INTEL_PINEVIEW
 

src/northbridge/intel/sandybridge/Kconfig

@@ -6,6 +6,7 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE
 	select CPU_INTEL_MODEL_206AX
 	select HAVE_DEBUG_RAM_SETUP
 	select INTEL_GMA_ACPI
+	select NEED_SMALL_2MB_PAGE_TABLES
 	select USE_DDR3
 
 if NORTHBRIDGE_INTEL_SANDYBRIDGE

src/northbridge/intel/x4x/Kconfig

@@ -10,6 +10,7 @@ config NORTHBRIDGE_INTEL_X4X
 	select HAVE_X86_64_SUPPORT
 	select USE_DDR3
 	select USE_DDR2
+	select NEED_SMALL_2MB_PAGE_TABLES
 
 if NORTHBRIDGE_INTEL_X4X
 

src/soc/intel/baytrail/Kconfig

@@ -33,6 +33,7 @@ config SOC_INTEL_BAYTRAIL
 	select CPU_HAS_L2_ENABLE_MSR
 	select TCO_SPACE_NOT_YET_SPLIT
 	select USE_DDR3
+	select NEED_SMALL_2MB_PAGE_TABLES
 	help
 	  Bay Trail M/D part support.
 

src/soc/intel/braswell/Kconfig

@@ -39,6 +39,7 @@ config SOC_INTEL_BRASWELL
 	select SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT
 	select NO_CBFS_MCACHE
 	select TCO_SPACE_NOT_YET_SPLIT
+	select NEED_SMALL_2MB_PAGE_TABLES
 	help
 	  Braswell M/D part support.
 

src/soc/intel/elkhartlake/Kconfig

@@ -24,6 +24,7 @@ config SOC_INTEL_ELKHARTLAKE
 	select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
 	select MP_SERVICES_PPI_V1
 	select MRC_SETTINGS_PROTECT
+	select NEED_SMALL_2MB_PAGE_TABLES
 	select PARALLEL_MP_AP_WORK
 	select PLATFORM_USES_FSP2_1
 	select PMC_GLOBAL_RESET_ENABLE_LOCK