soc/intel/apollolake: Switch to snake case for DisableSataSalpSupport

For a unification of the naming convension, change from pascal case to
snake case style for parameter 'DisableSataSalpSupport'.

Change-Id: I4a68ffd2b68c92434da681b5e5567329c8784c72
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75858
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Mario Scheithauer
2023-06-15 14:43:27 +02:00
committed by Jakub Czapiga
parent 53ad07a1ec
commit c7beb4f317
9 changed files with 9 additions and 9 deletions

View File

@@ -71,7 +71,7 @@ chip soc/intel/apollolake
device pci 12.0 on # - SATA
register "sata_ports_enable[0]" = "1"
register "sata_ports_enable[1]" = "1"
register "DisableSataSalpSupport" = "1"
register "disable_sata_salp_support" = "1"
end
device pci 13.0 on # - RP 2 - PCIe A 0 - MACPHY
register "pcie_rp_clkreq_pin[2]" = "0"

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@@ -71,7 +71,7 @@ chip soc/intel/apollolake
register "sata_ports_enable[1]" = "1"
register "sata_ports_ssd[0]" = "1"
register "sata_ports_ssd[1]" = "1"
register "DisableSataSalpSupport" = "1"
register "disable_sata_salp_support" = "1"
register "sata_speed" = "SATA_GEN2"
end
device pci 13.0 on # - RP 2 - PCIe A 0

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@@ -66,7 +66,7 @@ chip soc/intel/apollolake
device pci 12.0 on # - SATA
register "sata_ports_enable[0]" = "1"
register "sata_ports_enable[1]" = "1"
register "DisableSataSalpSupport" = "1"
register "disable_sata_salp_support" = "1"
end
device pci 13.0 on # - RP 2 - PCIe A 0
register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"

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@@ -60,7 +60,7 @@ chip soc/intel/apollolake
device pci 12.0 on # - SATA
register "sata_ports_enable[0]" = "1"
register "sata_ports_enable[1]" = "1"
register "DisableSataSalpSupport" = "1"
register "disable_sata_salp_support" = "1"
end
device pci 13.0 on # - RP 2 - PCIe A 0
register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"

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@@ -71,7 +71,7 @@ chip soc/intel/apollolake
register "sata_ports_enable[1]" = "1"
register "sata_ports_ssd[0]" = "1"
register "sata_ports_ssd[1]" = "1"
register "DisableSataSalpSupport" = "1"
register "disable_sata_salp_support" = "1"
register "sata_speed" = "SATA_GEN2"
end
device pci 13.0 on # - RP 2 - PCIe A 0

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@@ -42,7 +42,7 @@ chip soc/intel/apollolake
register "sata_ports_enable[1]" = "1"
register "sata_ports_ssd[0]" = "1"
register "sata_ports_ssd[1]" = "1"
register "DisableSataSalpSupport" = "1"
register "disable_sata_salp_support" = "1"
register "sata_speed" = "SATA_GEN2"
end
device pci 13.0 on # - RP 2 - PCIe A 0

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@@ -58,7 +58,7 @@ chip soc/intel/apollolake
device pci 0f.0 on end # - CSE
device pci 11.0 on end # - ISH
device pci 12.0 on # - SATA
register "DisableSataSalpSupport" = "1"
register "disable_sata_salp_support" = "1"
end
device pci 13.0 on # - RP 2 - PCIe A 0
register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"

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@@ -736,7 +736,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
/* SATA config */
if (is_devfn_enabled(PCH_DEVFN_SATA)) {
silconfig->SataSalpSupport = !(cfg->DisableSataSalpSupport);
silconfig->SataSalpSupport = !(cfg->disable_sata_salp_support);
ahci_set_speed(cfg->sata_speed);
memcpy(silconfig->SataPortsEnable, cfg->sata_ports_enable,
sizeof(silconfig->SataPortsEnable));

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@@ -221,7 +221,7 @@ struct soc_intel_apollolake_config {
uint8_t disable_xhci_lfps_pm;
/* SATA Aggressive Link Power Management */
uint8_t DisableSataSalpSupport;
uint8_t disable_sata_salp_support;
/* Sata Power Optimisation */
uint8_t SataPwrOptimizeDisable;