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autoport: Factor out GPIO config generation

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Intel chipsets from ICH7 through Lynxpoint use the same GPIO register
format and thus mainboards using using these platforms have similar
gpio.c files. Factor out the code to generate gpio.c from bd82x6x.go so
that it other chipsets added to autoport can use it.

This was originally written by Iru Cai in his Haswell autoport patch in
CB:30890; I have simply split out the code to a separate commit as it is
a separate logical change.

TEST=Generated output is identical before and after this patch when run
against logs from a Dell Latitude E6430

Change-Id: If1f506f6ad10144bd6acc42505592426bb7193b7
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83286
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Nicholas Chin 2024-06-30 13:09:28 -06:00 committed by Felix Singer
parent 7a0deb4d1b
commit c7cb5e434b
2 changed files with 115 additions and 110 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

112
util/autoport/bd82x6x.go
View File

@ -1,120 +1,12 @@
package main
import (
"fmt"
"os"
)
import "fmt"
type bd82x6x struct {
variant string
node *DevTreeNode
}
func (b bd82x6x) writeGPIOSet(ctx Context, sb *os.File,
val uint32, set uint, partno int, constraint uint32) {
max := uint(32)
if set == 3 {
max = 12
}
bits := [6][2]string{
{"GPIO_MODE_NATIVE", "GPIO_MODE_GPIO"},
{"GPIO_DIR_OUTPUT", "GPIO_DIR_INPUT"},
{"GPIO_LEVEL_LOW", "GPIO_LEVEL_HIGH"},
{"GPIO_RESET_PWROK", "GPIO_RESET_RSMRST"},
{"GPIO_NO_INVERT", "GPIO_INVERT"},
{"GPIO_NO_BLINK", "GPIO_BLINK"},
}
for i := uint(0); i < max; i++ {
if (constraint>>i)&1 == 1 {
fmt.Fprintf(sb, " .gpio%d = %s,\n",
(set-1)*32+i,
bits[partno][(val>>i)&1])
}
}
}
func (b bd82x6x) GPIO(ctx Context, inteltool InteltoolData) {
var constraint uint32
gpio := Create(ctx, "gpio.c")
defer gpio.Close()
AddBootBlockFile("gpio.c", "")
AddROMStageFile("gpio.c", "")
Add_gpl(gpio)
gpio.WriteString("#include <southbridge/intel/common/gpio.h>\n\n")
addresses := [3][6]int{
{0x00, 0x04, 0x0c, 0x60, 0x2c, 0x18},
{0x30, 0x34, 0x38, 0x64, -1, -1},
{0x40, 0x44, 0x48, 0x68, -1, -1},
}
for set := 1; set <= 3; set++ {
for partno, part := range []string{"mode", "direction", "level", "reset", "invert", "blink"} {
addr := addresses[set-1][partno]
if addr < 0 {
continue
}
fmt.Fprintf(gpio, "static const struct pch_gpio_set%d pch_gpio_set%d_%s = {\n",
set, set, part)
constraint = 0xffffffff
switch part {
case "direction":
/* Ignored on native mode */
constraint = inteltool.GPIO[uint16(addresses[set-1][0])]
case "level":
/* Level doesn't matter for input */
constraint = inteltool.GPIO[uint16(addresses[set-1][0])]
constraint &^= inteltool.GPIO[uint16(addresses[set-1][1])]
case "reset":
/* Only show reset */
constraint = inteltool.GPIO[uint16(addresses[set-1][3])]
case "invert":
/* Only on input and only show inverted GPIO */
constraint = inteltool.GPIO[uint16(addresses[set-1][0])]
constraint &= inteltool.GPIO[uint16(addresses[set-1][1])]
constraint &= inteltool.GPIO[uint16(addresses[set-1][4])]
case "blink":
/* Only on output and only show blinking GPIO */
constraint = inteltool.GPIO[uint16(addresses[set-1][0])]
constraint &^= inteltool.GPIO[uint16(addresses[set-1][1])]
constraint &= inteltool.GPIO[uint16(addresses[set-1][5])]
}
b.writeGPIOSet(ctx, gpio, inteltool.GPIO[uint16(addr)], uint(set), partno, constraint)
gpio.WriteString("};\n\n")
}
}
gpio.WriteString(`const struct pch_gpio_map mainboard_gpio_map = {
.set1 = {
.mode = &pch_gpio_set1_mode,
.direction = &pch_gpio_set1_direction,
.level = &pch_gpio_set1_level,
.blink = &pch_gpio_set1_blink,
.invert = &pch_gpio_set1_invert,
.reset = &pch_gpio_set1_reset,
},
.set2 = {
.mode = &pch_gpio_set2_mode,
.direction = &pch_gpio_set2_direction,
.level = &pch_gpio_set2_level,
.reset = &pch_gpio_set2_reset,
},
.set3 = {
.mode = &pch_gpio_set3_mode,
.direction = &pch_gpio_set3_direction,
.level = &pch_gpio_set3_level,
.reset = &pch_gpio_set3_reset,
},
};
`)
}
func (b bd82x6x) IsPCIeHotplug(ctx Context, port int) bool {
portDev, ok := PCIMap[PCIAddr{Bus: 0, Dev: 0x1c, Func: port}]
if !ok {
@ -168,7 +60,7 @@ func (b bd82x6x) Scan(ctx Context, addr PCIDevData) {
SouthBridge = &b
inteltool := ctx.InfoSource.GetInteltool()
b.GPIO(ctx, inteltool)
GPIO(ctx, inteltool)
KconfigBool["SOUTHBRIDGE_INTEL_"+b.variant] = true
KconfigBool["SERIRQ_CONTINUOUS_MODE"] = true

113
util/autoport/gpio_common.go Normal file
View File

@ -0,0 +1,113 @@
/* code to generate common GPIO code for Intel 6/7/8 Series Chipset */
package main
import (
"fmt"
"os"
)
func writeGPIOSet(ctx Context, sb *os.File,
val uint32, set uint, partno int, constraint uint32) {
max := uint(32)
if set == 3 {
max = 12
}
bits := [6][2]string{
{"GPIO_MODE_NATIVE", "GPIO_MODE_GPIO"},
{"GPIO_DIR_OUTPUT", "GPIO_DIR_INPUT"},
{"GPIO_LEVEL_LOW", "GPIO_LEVEL_HIGH"},
{"GPIO_RESET_PWROK", "GPIO_RESET_RSMRST"},
{"GPIO_NO_INVERT", "GPIO_INVERT"},
{"GPIO_NO_BLINK", "GPIO_BLINK"},
}
for i := uint(0); i < max; i++ {
if (constraint>>i)&1 == 1 {
fmt.Fprintf(sb, " .gpio%d = %s,\n",
(set-1)*32+i,
bits[partno][(val>>i)&1])
}
}
}
func GPIO(ctx Context, inteltool InteltoolData) {
var constraint uint32
gpio := Create(ctx, "gpio.c")
defer gpio.Close()
AddBootBlockFile("gpio.c", "")
AddROMStageFile("gpio.c", "")
Add_gpl(gpio)
gpio.WriteString("#include <southbridge/intel/common/gpio.h>\n\n")
addresses := [3][6]int{
{0x00, 0x04, 0x0c, 0x60, 0x2c, 0x18},
{0x30, 0x34, 0x38, 0x64, -1, -1},
{0x40, 0x44, 0x48, 0x68, -1, -1},
}
for set := 1; set <= 3; set++ {
for partno, part := range []string{"mode", "direction", "level", "reset", "invert", "blink"} {
addr := addresses[set-1][partno]
if addr < 0 {
continue
}
fmt.Fprintf(gpio, "static const struct pch_gpio_set%d pch_gpio_set%d_%s = {\n",
set, set, part)
constraint = 0xffffffff
switch part {
case "direction":
/* Ignored on native mode */
constraint = inteltool.GPIO[uint16(addresses[set-1][0])]
case "level":
/* Level doesn't matter for input */
constraint = inteltool.GPIO[uint16(addresses[set-1][0])]
constraint &^= inteltool.GPIO[uint16(addresses[set-1][1])]
case "reset":
/* Only show reset */
constraint = inteltool.GPIO[uint16(addresses[set-1][3])]
case "invert":
/* Only on input and only show inverted GPIO */
constraint = inteltool.GPIO[uint16(addresses[set-1][0])]
constraint &= inteltool.GPIO[uint16(addresses[set-1][1])]
constraint &= inteltool.GPIO[uint16(addresses[set-1][4])]
case "blink":
/* Only on output and only show blinking GPIO */
constraint = inteltool.GPIO[uint16(addresses[set-1][0])]
constraint &^= inteltool.GPIO[uint16(addresses[set-1][1])]
constraint &= inteltool.GPIO[uint16(addresses[set-1][5])]
}
writeGPIOSet(ctx, gpio, inteltool.GPIO[uint16(addr)], uint(set), partno, constraint)
gpio.WriteString("};\n\n")
}
}
gpio.WriteString(`const struct pch_gpio_map mainboard_gpio_map = {
.set1 = {
.mode = &pch_gpio_set1_mode,
.direction = &pch_gpio_set1_direction,
.level = &pch_gpio_set1_level,
.blink = &pch_gpio_set1_blink,
.invert = &pch_gpio_set1_invert,
.reset = &pch_gpio_set1_reset,
},
.set2 = {
.mode = &pch_gpio_set2_mode,
.direction = &pch_gpio_set2_direction,
.level = &pch_gpio_set2_level,
.reset = &pch_gpio_set2_reset,
},
.set3 = {
.mode = &pch_gpio_set3_mode,
.direction = &pch_gpio_set3_direction,
.level = &pch_gpio_set3_level,
.reset = &pch_gpio_set3_reset,
},
};
`)
}