Merge remote-tracking branch 'upstream/master' into system75

.gitignore

@@ -56,6 +56,7 @@ site-local
 *.\#
 *.bin
 *.debug
+!Kconfig.debug
 *.elf
 *.o
 *.out

.gitmodules

@@ -37,3 +37,8 @@
 [submodule "3rdparty/ffs"]
 	path = 3rdparty/ffs
 	url = https://github.com/coreboot/ffs.git
+[submodule "3rdparty/amd_blobs"]
+	path = 3rdparty/amd_blobs
+	url = https://review.coreboot.org/amd_blobs.git
+	update = none
+	ignore = dirty

3rdparty/amd_blobs

@@ -0,0 +1 @@
+Subproject commit cf227316b0fbd3995854ce21e81a63270b29bfb5

3rdparty/libgfxinit

@@ -1 +1 @@
-Subproject commit a815704c84b4823f5b723404a37efed9d6c85d66
+Subproject commit fe7985f2a0692bc773d470a92ec54d22d3c12e4b

AUTHORS

@@ -13,12 +13,17 @@ Advanced Micro Devices, Inc.
 Alex Züpke
 Alexander Couzens
 Alexandru Gagniuc
+Analog Devices Inc.
 Andy Fleming
 ARM Limited and Contributors
 Arthur Heymans
+ASPEED Technology Inc.
+Atheros Corporation
+Atmel Corporation
 Carl-Daniel Hailfinger
 coresystems GmbH
 Damien Zammit
+David Brownell
 David Hendricks
 David Mosberger-Tang
 Denis Dowling
@@ -26,6 +31,7 @@ DENX Software Engineering
 DMP Electronics Inc.
 Drew Eckhardt
 Egbert Eich
+Eltan B.V
 Eric Biederman
 Eswar Nallusamy
 Facebook, Inc.
@@ -37,12 +43,16 @@ Gary Jennejohn
 Gerd Hoffmann
 Google LLC
 Greg Watson
+Idwer Vollering
 Imagination Technologies
+Infineon Technologies
 Intel Corporation
 Jason Zhao
+Jonathan Neuschäfer
 Jordan Crouse
 Joseph Smith
 Keith Hui
+Keith Packard
 Kshitij
 Kyösti Mälkki
 Lei Wen
@@ -50,43 +60,58 @@ Li-Ta Lo
 Libra Li
 Linus Torvalds
 Linux Networx, Inc.
+Luc Verhaegen
 Marc Jones
 Marek Vasut
 Marius Gröger
 Martin Mares
+Marvell International Ltd.
 Marvell Semiconductor Inc.
 MediaTek Inc.
 MontaVista Software, Inc.
 Myles Watson
+Network Appliance Inc.
 Nicholas Sielicki
 Nick Barker
 Nico Huber
+Ollie Lo
+Orion Technologies, LLC
 Patrick Georgi
 Patrick Rudolph
 PC Engines GmbH
 Per Odlund
 Peter Stuge
 Raptor Engineering, LLC
+Red Hat Inc
+Reinhard Meyer
 Richard Woodruff
 Ronald G. Minnich
 Rudolf Marek
 Russell King
 Sage Electronic Engineering, LLC
+Samsung Electronics
 SciTech Software, Inc.
+Sebastian Grzywna
 secunet Security Networks AG
 Siemens AG
 Silicon Integrated System Corporation
 Stefan Reinauer
 Steve Magnani
+ST Microelectronics
 SUSE LINUX AG
 Sven Schnelle
 Syed Mohammed Khasim
 Texas Instruments
 The Linux Foundation
+Thomas Winischhofer
 Timothy Pearson
+Tungsten Graphics, Inc.
 Tyan Computer Corp.
+ucRobotics Inc.
 Uwe Hermann
 VIA Technologies, Inc
+Vipin Kumar
+Ward Vandewege
 Wolfgang Denk
 Yinghai Lu
 
@@ -99,3 +124,4 @@ src/commonlib
 src/console
 src/cpu
 src/device
+src/drivers

Documentation/RFC/config.tex

@@ -1,290 +0,0 @@
-		New config language for LinuxBIOS
-
-\begin{abstract}
-We describe the new configuration language for LinuxBIOS.
-\end{abstract}
-
-\section{Scope}
-This document defines the new configuration language for LinuxBIOS.
-
-\section{Goals}
-The goals of the new language are these:
-\begin{itemize}
-\item Simplified Makefiles so people can see what is set
-\item Move from the regular-expression-based language to something
-a bit more comprehensible and flexible
-\item make the specification easier for people to use and understand
-\item allow unique register-set-specifiers for each chip
-\item allow generic register-set-specifiers for each chip
-\item generate static initialization code, as needed, for the
-specifiers.
-\end{itemize}
-
-\section{Language}
-Here is the new language. It is very similar to the old one, differing
-in only a few respects. It borrows heavily from Greg Watson's suggestions.
-
-I am presenting it in a pseudo-BNF in the hopes it will be easier. Things
-in '' are keywords; things in ``'' are strings in the actual text.
-\begin{verbatim}
-#exprs are composed of factor or factor + factor etc.
-expr ::= factor ( ``+'' factor | ``-'' factor | )*
-#factors are term or term * term or term / term or ...
-factor ::=  term ( ``*'' term | ``/'' term | ... )*
-#
-unary-op ::= ``!'' ID
-# term is a number, hexnumber, ID, unary-op, or a full-blown expression
-term ::= NUM | XNUM | ID | unary-op | ``(`` expr ``)''
-
-# Option command. Can be an expression or quote-string.
-# Options are used in the config tool itself (in expressions and 'if')
-# and are also passed to the C compiler when building linuxbios.
-# It is an error to have two option commands in a file.
-# It is an error to have an option command after the ID has been used
-#   in an expression (i.e. 'set after used' is an error)
-option ::= 'option' ID '=' (``value'' | term)
-
-# Default command. The ID is set to this value if no option command
-# is scanned.
-# Multiple defaults for an ID will produce warning, but not errors.
-# It is OK to scan a default command after use of an ID.
-# Options always over-ride defaults.
-default ::= 'default' ID '=' (``value'' | term)
-
-# the mainboard, southbridge, northbridge commands
-# cause sourcing of Config.lb files as in the old config tool
-# as parts are sourced, a device tree is built. The structure
-# of the tree is determined by the structure of the components
-# as they are specified. To attach a superio to a southbridge, for
-# example, one would do this:
-# southbridge acer/5432
-#   superio nsc/123
-#   end
-# end
-# the tool generates static initializers for this hierarchy.
-
-# add C code to the current component (motherboard, etc. )
-# to initialise the component-INDEPENDENT structure members
-init ::= 'init' ``CODE''
-
-# add C code to the current component (motherboard, etc. )
-# to initialise the component-DEPENDENT structure members
-register ::= 'register' ``CODE''
-
-
-# mainboard command
-# statements in this block will set variables controlling the mainboard,
-# and will also place components (northbridge etc.) in the device tree
-# under this mainboard
-mainboard ::= 'mainboard' PATH (statements)* 'end'
-
-# standard linuxbios commands
-southbridge ::= 'southbridge' PATH (statemnts)* 'end'
-northbridge ::= 'northbridge' PATH (statemnts)* 'end'
-superio ::= 'superio PATH (statemnts)* 'end'
-cpu ::= 'cpu' PATH (statemnts)* 'end'
-arch ::= 'arch' PATH (statemnts)* 'end'
-
-# files for building linuxbios
-# include a file in crt0.S
-mainboardinit ::= 'mainboardinit' PATH
-
-# object file
-object ::= 'object' PATH
-# driver objects are just built into the image in a different way
-driver ::= 'driver' PATH
-
-# Use the Config.lb file in the PATH
-dir ::= 'dir' PATH
-
-# add a file to the set of ldscript files
-ldscript ::= 'ldscript' PATH
-
-# dependencies or actions for the makerule command
-dep ::= 'dep' ``dependency-string''
-act ::= 'act' ``actions''
-depsacts ::= (dep | act)*
-# set up a makerule
-#
-makerule ::= 'makerule' PATH depsacts
-
-#defines for use in makefiles only
-# note usable in the config tool, not passed to cc
-makedefine ::= 'makedefine' ``RAWTEXT''
-
-# add an action to an existing make rule
-addaction ::= 'addaction' PATH ``ACTION''
-
-# statements
-statement ::=
-		  option
-		| default
-		| cpu
-		| arch
-		| northbridge
-		| southbridge
-		| superio
-		| object
-		| driver
-		| mainboardinit
-		| makerule
-		| makedefine
-		| addaction
-		| init
-		| register
-		| iif
-		| dir
-		| ldscript
-
-statements ::= (statement)*
-
-# target directory specification
-target ::= 'target' PATH
-
-# and the whole thing
-board ::= target (option)* mainboard
-
-\end{verbatim}
-
-\subsubsection{Command definitions}
-\subsubsubsection{option}
-\subsubsubsection{default}
-\subsubsubsection{cpu}
-\subsubsubsection{arch}
-\subsubsubsection{northbridge}
-\subsubsubsection{southbridge}
-\subsubsubsection{superio}
-\subsubsubsection{object}
-\subsubsubsection{driver}
-\subsubsubsection{mainboardinit}
-\subsubsubsection{makerule}
-\subsubsubsection{makedefine}
-\subsubsubsection{addaction}
-\subsubsubsection{init}
-\subsubsubsection{register}
-\subsubsubsection{iif}
-\subsubsubsection{dir}
-\subsubsubsection{ldscript}
-
-
-A sample file:
-
-\begin{verbatim}
-target x
-
-# over-ride the default ROM size in the mainboard file
-option CONFIG_ROM_SIZE=1024*1024
-mainboard amd/solo
-end
-
-\end{verbatim}
-
-Sample mainboard file
-\begin{verbatim}
-#
-###
-### Set all of the defaults for an x86 architecture
-###
-arch i386 end
-cpu k8 end
-#
-option CONFIG_DEBUG=1
-default CONFIG_USE_FALLBACK_IMAGE=1
-option A=(1+2)
-option B=0xa
-#
-###
-### Build our 16 bit and 32 bit linuxBIOS entry code
-###
-mainboardinit cpu/i386/entry16.inc
-mainboardinit cpu/i386/entry32.inc
-ldscript cpu/i386/entry16.lds
-ldscript cpu/i386/entry32.lds
-#
-###
-### Build our reset vector (This is where linuxBIOS is entered)
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/i386/reset16.inc
-	ldscript cpu/i386/reset16.lds
-else
-	mainboardinit cpu/i386/reset32.inc
-	ldscript cpu/i386/reset32.lds
-end
-.
-.
-.
-if CONFIG_USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc  end
-#
-###
-### Romcc output
-###
-#makerule ./failover.E dep "$(CONFIG_MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c > ./failever.E"
-#makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc"
-#mainboardinit ./failover.inc
-makerule ./auto.E dep "$(CONFIG_MAINBOARD)/auto.c" act "$(CPP) -I$(TOP)/src -$(ROMCCPPFLAGS) $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c > ./auto.E"
-makerule ./auto.inc dep "./romcc ./auto.E" act "./romcc -O ./auto.E > auto.inc"
-mainboardinit ./auto.inc
-#
-###
-### Include the secondary Configuration files
-###
-northbridge amd/amdk8
-end
-southbridge amd/amd8111
-end
-#mainboardinit arch/i386/smp/secondary.inc
-superio nsc/pc87360
-	register "com1={1} com2={0} floppy=1 lpt=1 keyboard=1"
-end
-dir /pc80
-##dir /src/superio/winbond/w83627hf
-cpu p5 end
-cpu p6 end
-cpu k7 end
-cpu k8 end
-#
-###
-### Build the objects we have code for in this directory.
-###
-##object mainboard.o
-driver mainboard.o
-object static_devices.o
-if CONFIG_HAVE_MP_TABLE object mptable.o end
-if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
-### Location of the DIMM EEPROMS on the SMBUS
-### This is fixed into a narrow range by the DIMM package standard.
-###
-option SMBUS_MEM_DEVICE_START=(0xa << 3)
-option SMBUS_MEM_DEVICE_END=(SMBUS_MEM_DEVICE_START +1)
-option SMBUS_MEM_DEVICE_INC=1
-#
-### The linuxBIOS bootloader.
-###
-option CONFIG_PAYLOAD_SIZE            = (CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE)
-option CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)
-#
-
-\end{verbatim}
-
-I've found the output of the new tool to be easier to
-handle. Makefile.settings looks like this, for example:
-\begin{verbatim}
-TOP:=/home/rminnich/src/yapps2/freebios2
-TARGET_DIR:=x
-export CONFIG_MAINBOARD:=/home/rminnich/src/yapps2/freebios2/src/mainboard/amd/solo
-export CONFIG_ARCH:=i386
-export CONFIG_RAMBASE:=0x4000
-export CONFIG_ROM_IMAGE_SIZE:=65535
-export CONFIG_PAYLOAD_SIZE:=131073
-export CONFIG_MAX_CPUS:=1
-export CONFIG_HEAP_SIZE:=8192
-export CONFIG_STACK_SIZE:=8192
-export CONFIG_MEMORY_HOLE:=0
-export COREBOOT_VERSION:=1.1.0
-export CC:=$(CONFIG_CROSS_COMPILE)gcc
-
-\end{verbatim}
-
-In other words, instead of expressions, we see the values. It's easier to
-deal with.

Documentation/arch/x86/index.md

@@ -16,24 +16,36 @@ In order to add support for x86_64 the following assumptions are made:
 * The reference implementation is qemu
 * The CPU supports 1GiB hugepages
 
-## Assuptions for ARCH_ROMSTAGE_X86_64 reference implementation
+## Assuptions for all stages using the reference implementation
-* 0-4GiB are identity mapped using 1GiB huge-pages
+* 0-4GiB are identity mapped using 2MiB-pages as WB
 * Memory above 4GiB isn't accessible
-* pagetables reside in _pagetables
+* page tables reside in memory mapped ROM
-* Romstage must install new pagetables in CBMEM after RAMINIT
+* A stage can install new page tables in RAM
 
-## Assuptions for ARCH_RAMSTAGE_X86_64 reference implementation
+## Page tables
-* Romstage installed pagetables according to memory layout
+Page tables are generated by a tool in `util/pgtblgen/pgtblgen`. It writes
-* Memory above 4GiB is accessible
+the page tables to a file which is then included into the CBFS as file called
+`pagetables`.
+
+To generate the static page tables it must know the physical address where to
+place the file.
+
+The page tables contains the following structure:
+* PML4E pointing to PDPE
+* PDPE with *$n* entries each pointing to PDE
+* *$n* PDEs with 512 entries each
+
+At the moment *$n* is 4, which results in identity mapping the lower 4 GiB.
 
 ## Steps to add basic support for x86_64
 * Add x86_64 toolchain support - *DONE*
 * Fix compilation errors - *DONE*
 * Fix linker errors - *TODO*
-* Add x86_64 rmodule support - *ONGERRIT*
+* Add x86_64 rmodule support - *DONE*
 * Add x86_64 exception handlers - *TODO*
-* Setup page tables for long mode - *TODO*
+* Setup page tables for long mode - *DONE*
-* Add assembly code for long mode - *TODO*
+* Add assembly code for long mode - *DONE*
+* Add assembly code for postcar stage - *TODO*
 * Add assembly code to return to protected mode - *TODO*
 * Implement reference code for mainboard `emulation/qemu-q35` - *TODO*
 

Documentation/community/services.md

@@ -0,0 +1,45 @@
+# Accounts on coreboot.org
+
+There are a number of places where you can benefit from creaating an account
+in our community. Since there is no single sign-on system in place (at this
+time), they come with their own setup routines.
+
+## Gerrit code review
+We exchange and review patches to the code using our [Gerrit code review
+system](https://review.coreboot.org).
+
+It allows logging in with a Google or GitHub account using OAuth2 as well
+as with any OpenID provider that you may already use.
+
+On the [settings screen](https://review.coreboot.org/settings) you can register
+all your email addresses you intend to use in the context of coreboot
+development so that commits with your email address in them are associated with
+you properly.
+
+### https push access
+When using the https URLs to git repositories, you can push with the "HTTP
+Credentials" you can have Gerrit generate for you on that page. By default,
+git uses `$HOME/.netrc` for http authentication data, so add a line there
+stating:
+
+    machine review.coreboot.org login $your-user-name password $your-password
+
+### Gerrit user avatar
+To setup an avatar to show in Gerrit, clone the avatars repository at
+https://review.coreboot.org/gerrit-avatars.git and add a file named
+$your-user-ID.jpg (the user ID is a number shown on the [settings screen](https://review.coreboot.org/settings)).
+The image must be provided in JPEG format, must be square and have at most 50000
+bytes.
+
+After you push for review, the system will automatically verify your change
+and, if adhering to these constraints, approve it. You can then immediately
+submit it.
+
+## Issue tracker
+We have an [issue tracker](https://ticket.coreboot.org) that is used for
+coreboot and related code, such as libpayload, as well as for the project's
+infrastructure.
+
+It can be helpful to refer to issues we track there in commit messages:
+
+    Fixes: https://ticket.coreboot.org/issues/$id

Documentation/getting_started/architecture.md

@@ -1,6 +1,6 @@
 # coreboot architecture
 
-## Overwiew
+## Overview
 ![][architecture]
 
 [architecture]: comparision_coreboot_uefi.svg

Documentation/getting_started/writing_documentation.md

@@ -14,18 +14,40 @@ coreboot uses [Sphinx] documentation tool. We prefer the markdown format
 over reStructuredText so only embedded ReST is supported. Checkout the
 [Markdown Guide] for more information.
 
-### Install Sphinx
+### option 1: Use the docker image
+
+The easiest way to build the documentation is using a docker image.
+To build the image run the following in the base directory:
+
+	make -C util/docker/ doc.coreboot.org
+
+Before building the documentation make sure the output directory is given
+the correct permissions before running docker.
+
+	mkdir -p Documentation/_build
+
+To build the documentation:
+
+	make -C util/docker docker-build-docs
+
+To have the documentation build and served over a web server live run:
+
+	make -C util/docker docker-livehtml-docs
+
+On the host machine, open a browser to the address <http://0.0.0.0:8000>.
+
+### option 2: Install Sphinx
 
 Please follow this official [guide] to install sphinx.
 You will also need python-recommonmark for sphinx to be able to handle
-markdown documenation.
+markdown documentation.
 
 The recommended version is sphinx 1.7.7, sphinx_rtd_theme 0.4.1 and
 recommonmark 0.4.0.
 
 ### Optional
 
-Install [shpinx-autobuild] for rebuilding markdown/rst sources on the fly!
+Install [sphinx-autobuild] for rebuilding markdown/rst sources on the fly!
 
 ## Basic and simple rules
 
@@ -116,7 +138,7 @@ TOC tree.
 
 [coreboot]: https://coreboot.org
 [Documentation]: https://review.coreboot.org/cgit/coreboot.git/tree/Documentation
-[shpinx-autobuild]: https://github.com/GaretJax/sphinx-autobuild
+[sphinx-autobuild]: https://github.com/GaretJax/sphinx-autobuild
 [guide]: http://www.sphinx-doc.org/en/stable/install.html
 [Sphinx]: http://www.sphinx-doc.org/en/master/
 [Markdown Guide]: https://www.markdownguide.org/

Documentation/gfx/libgfxinit.md

@@ -7,13 +7,14 @@ Introduction and Current State in coreboot
 *libgfxinit* is a library of full-featured graphics initialization
 (aka. modesetting) drivers. It's implemented in SPARK (a subset of
 Ada with formal verification features). While not restricted to in
-any way, it currently only supports Intel's integrated gfx control-
+any way, it currently only supports Intel's integrated graphics
-lers (GMA).
+controllers (GMA).
 
-Currently, it supports the Intel Core i3/i5/i7 processor line and
+Currently, it supports the Intel Core i3/i5/i7 processor line, HDMI
-will support HDMI and DP on the Atom successor Apollo Lake. At the
+and DP on the Apollo Lake processors and everything but SDVO on G45
-time of writing, Sandy Bridge, Ivy Bridge, and Haswell are veri-
+and GM45 chipsets. At the time of writing, G45, GM45, everything
-fied to work within *coreboot*.
+from Arrandale to Coffee Lake, and Apollo Lake are verified to work
+within *coreboot*.
 
 GMA: Framebuffer Configuration
 ------------------------------

Documentation/ifdtool/index.md

@@ -1,3 +1,4 @@
+# ifdtool
 
 Contents:
 

Documentation/index.md

@@ -166,10 +166,11 @@ Contents:
 * [Project Ideas](contributing/project_ideas.md)
 * [Code of Conduct](community/code_of_conduct.md)
 * [Community forums](community/forums.md)
+* [Project services](community/services.md)
 * [coreboot at conferences](community/conferences.md)
 * [Payloads](payloads.md)
 * [Distributions](distributions.md)
-* [Dealing with Untrusted Input in SMM](technotes/2017-02-dealing-with-untrusted-input-in-smm.md)
+* [Technotes](technotes/index.md)
 * [GPIO toggling in ACPI AML](acpi/gpio.md)
 * [Adding devices to a device tree](acpi/devicetree.md)
 * [Native Graphics Initialization with libgfxinit](gfx/libgfxinit.md)

Documentation/lib/flashmap.md

@@ -17,7 +17,7 @@ something else) should have its own Flashmap section, and everything else should
 normally go into CBFS.
 
 The Flashmap itself starts with a header `struct fmap` and followed by a list of
-section descriptions in `strcut fmap_area`.
+section descriptions in `struct fmap_area`.
 
 ### Header
 The header `struct fmap` has following fields:

Documentation/mainboard/amd/index.md

@@ -1,7 +0,0 @@
-# AMD platforms documentation
-
-This section contains documentation about specific AMD mainboards.
-
-## Mainboard
-
-- [padmelon](padmelon/padmelon.md)

Documentation/mainboard/amd/padmelon/padmelon.md

@@ -75,6 +75,6 @@ Three items are marked in this picture
 
 [Merlin Falcon BKDG][merlinfalcon]
 
-[merlinfalcon]: ../../soc/amd/family15h.md
+[merlinfalcon]: ../../../soc/amd/family15h.md
 [padmelon]: padmelon.jpg
 [padmelon_io]: padmelon_io.jpg

Documentation/mainboard/asrock/h81m-hds.md

@@ -70,7 +70,7 @@ facing towards the bottom of the board.
 - The VGA port doesn't work until the OS reinitialises the display.
 
 - There is no automatic, OS-independent fan control. This is because
-  the super I/O hardware monitor can only obtain valid CPU temperature
+  the Super I/O hardware monitor can only obtain valid CPU temperature
   readings from the PECI agent, but the required driver doesn't exist
   in coreboot. The `coretemp` driver can still be used for accurate CPU
   temperature readings from an OS.

Documentation/mainboard/asus/p8h61-m_lx.md

@@ -49,7 +49,7 @@ region is not readable even by the host.
   suspend.
 
 - There is no automatic, OS-independent fan control. This is because
-  the super I/O hardware monitor can only obtain valid CPU temperature
+  the Super I/O hardware monitor can only obtain valid CPU temperature
   readings from the PECI agent, whose complete initialisation is not
   publicly documented. The `coretemp` driver can still be used for
   accurate CPU temperature readings.

Documentation/mainboard/asus/p8h61-m_pro.md

@@ -46,7 +46,7 @@ region is not readable even by the host.
 ## Known issues
 
 - There is no automatic, OS-independent fan control. This is because
-  the super I/O hardware monitor can only obtain valid CPU temperature
+  the Super I/O hardware monitor can only obtain valid CPU temperature
   readings from the PECI agent, whose complete initialisation is not
   publicly documented. The `coretemp` driver can still be used for
   accurate CPU temperature readings.

Documentation/mainboard/facebook/fbg1701.md

@@ -5,16 +5,17 @@ This page describes how to run coreboot on the Facebook FBG1701.
 FBG1701 are assembled with different onboard memory modules:
 	Rev 1.0	Onboard Samsung K4B8G1646D-MYKO memory
 	Rev 1.1 and 1.2	Onboard Micron MT41K512M16HA-125A memory
+	Rev 1.3	Onboard Kingston B5116ECMDXGGB memory
 
-Use make menuconfig to configure `onboard memory manufacturer` in Mainboard
+Use make menuconfig to configure `onboard memory manufacturer Samsung` in
-menu.
+Mainboard menu.
 
 ## Required blobs
 
 This board currently requires:
 fsp blob	3rdparty/fsp/BraswellFspBinPkg/FspBin/BSWFSP.fd
 Microcode	Intel Braswell cpuid 1046C4 version 410
-		(Used pre-build binary retrieved from Intel site)
+		(Used pre-built binary retrieved from Intel site)
 
 ## Flashing coreboot
 
@@ -25,7 +26,7 @@ The main SPI flash can be accessed using [flashrom].
 ### External programming
 
 The system has an internal flash chip which is a 8 MiB soldered SOIC-8 chip.
-This chip is located to the top middle side of the board. It's located
+This chip is located on the top middle side of the board. It's located
 between SoC and Q7 connector. Use clip (or solder wires) to program
 the chip.
 Specifically, it's a Winbond W25Q64FW (1.8V), whose datasheet can be found

Documentation/mainboard/index.md

@@ -2,6 +2,9 @@
 
 This section contains documentation about coreboot on specific mainboards.
 
+## AMD
+- [padmelon](amd/padmelon/padmelon.md)
+
 ## ASRock
 
 - [H81M-HDS](asrock/h81m-hds.md)
@@ -62,9 +65,18 @@ The boards in this section are not real mainboards, but emulators.
 
 - [Mainboard codenames](lenovo/codenames.md)
 - [Hardware Maintenance Manual of ThinkPads](lenovo/thinkpad_hmm.md)
+- [R60](lenovo/r60.md)
 - [T4xx common](lenovo/t4xx_series.md)
 - [X2xx common](lenovo/x2xx_series.md)
 
+### Nehalem series
+
+- [T410](lenovo/t410.md)
+
+### GM45 series
+
+- [X301](lenovo/x301.md)
+
 ### Sandy Bridge series
 
 - [T420](lenovo/t420.md)
@@ -79,6 +91,14 @@ The boards in this section are not real mainboards, but emulators.
 - [T430 / T530 / X230 / W530 common](lenovo/xx30_series.md)
 - [T431s](lenovo/t431s.md)
 
+### Haswell series
+
+- [T440p](lenovo/t440p.md)
+
+## Portwell
+
+- [PQ7-M107](portwell/pq7-m107.md)
+
 ## MSI
 
 - [MS-7707](msi/ms7707/ms7707.md)
@@ -108,7 +128,7 @@ The boards in this section are not real mainboards, but emulators.
 ## Supermicro
 
 - [X10SLM+-F](supermicro/x10slm-f.md)
-- [X11 LGA1151 series](supermicro/x11-lga1151-series/index.md)
+- [X11 LGA1151 series](supermicro/x11-lga1151-series/x11-lga1151-series.md)
 
 ## UP
 

Documentation/mainboard/lenovo/r60.md

@@ -0,0 +1,44 @@
+# Lenovo Thinkpad R60
+
+Untested on boards with external Radeon graphics adapter. If you have such
+board, proceed at your own risk and document if it does work.
+
+## Flashing instructions
+
+### External flashing
+
+The flash IC is located at the bottom center of the mainboard. Access to
+the flash chip is blocked by the magnesium frame, so you need to disassemble
+the entire laptop and remove the mainboard. The flash chip is referenced as U49 in
+the schematics and in the boardview.
+
+![](r60_chip.jpg)
+
+To disassemble the laptop, follow the [Hardware Maintenance Manual](https://thinkpads.com/support/hmm/hmm_pdf/42x3749_02.pdf).
+
+### Internal flashing on Vendor BIOS
+
+This [method](https://gist.github.com/ArthurHeymans/c5ef494ada01af372735f237f6c6adbe) describes a way to install coreboot with vendor firmware still
+installed on the Lenovo Thinkpad X60. It is reported to also work in Thinkpad
+R60, with the only difference being the board target you build coreboot for.
+
+### Flashing on coreboot
+
+Default configuration of coreboot doesn't feature any flash restrictions
+like the vendor firmware, therefore flashrom is able to flash any rom without problems.
+
+## Things tested and working in Linux 5.3:
+
+- Intel WiFi card
+- Suspend and resume
+- Native graphics initialization. Both legacy VGA and linear framebuffer work
+- GRUB2 2.04 and SeaBIOS 1.12.1 payloads
+- Reflashing with flashrom (use flashrom-git as of 17.09.2019)
+- 2G+1G memory configuration working
+- 2504 dock USB ports if not hotplugged
+
+## Things tested and not working:
+
+- 2504 dock hotplugging
+- Black bar at the left side of the screen. Doesn't appear in Linux. See picture at top
+- Sometimes it takes several second to run coreboot. Just wait for it

Documentation/mainboard/lenovo/t410.md

@@ -0,0 +1,44 @@
+# Lenovo T410
+
+## Known issues
+* Dock has wrong ACPI ID (causes "AC adapter state cannot be read" in Linux)
+* TPM not working with VBOOT and C_ENV bootblock (works without C_ENV BB)
+
+## Flashing instructions
+```eval_rst
++---------------------+--------------------------------+
+| Type                | Value                          |
++=====================+================================+
+| Socketed flash      | no                             |
++---------------------+--------------------------------+
+| Size                | 8 MiB                          |
++---------------------+--------------------------------+
+| In circuit flashing | Only in S3/WoL                 |
++---------------------+--------------------------------+
+| Package             | SOIC-8                         |
++---------------------+--------------------------------+
+| Write protection    | No                             |
++---------------------+--------------------------------+
+| Dual BIOS feature   | No                             |
++---------------------+--------------------------------+
+| Internal flashing   | Yes                            |
++---------------------+--------------------------------+
+```
+
+The flash IC is located at the bottom center of the mainboard.  Sadly,
+access to the IC is blocked by the magnesum frame, so you need to disassemble
+the entire laptop and remove the mainboard.
+
+Below is a picture of IC on the mainboard, with the pinouts labeled.
+
+![t410_chip_location](t410_chip_location.jpg)
+
+The chip will either be a Macronix MX25L6405D or a Winbond W25Q64CVSIG.
+Do not rely on dots painted in the corner of the chip (such as the blue dot
+pictured) to orient the pins!
+
+[Flashing tutorial](../../flash_tutorial/no_ext_power.md)
+
+Steps to access the flash IC are described here [T4xx series].
+
+[T4xx series]: t4xx_series.md

Documentation/mainboard/lenovo/t440p.md

@@ -0,0 +1,66 @@
+# Lenovo ThinkPad T440p
+
+This page describes how to run coreboot on [Lenovo ThinkPad T440p].
+
+## Required proprietary blobs
+
+Please see [mrc.bin](../../northbridge/intel/haswell/mrc.bin).
+
+## Flashing instructions
+
+T440p has two flash chips, an 8MB W25Q64FV and a 4MB W25Q32FV. To flash
+coreboot, you just need to remove the big door according to the T440
+[Hardware Maintenance Manual] and flash the 4MB chip.
+
+![T440p flash chip](t440p_flash_chip.jpg)
+
+To access the 8MB chip, you need to remove the base cover.
+
+![T440p 8MB flash chip](t440p_all_flash_chips.jpg)
+
+The flash layout of the OEM firmware is as follows:
+
+    00000000:00000fff fd
+    00001000:00002fff gbe
+    00003000:004fffff me
+    00500000:00bfffff bios
+
+After flashing coreboot, you may need to re-plug the AC adapter to make
+the laptop able to power on.
+
+## Known Issues
+
+- No audio output when using a headphone
+- The touchpad is misconfigured, the 3 keys on top are all identified
+  as left button
+- Cannot get the mainboard serial number from the mainboard: the OEM
+  UEFI firmware gets the serial number from an "emulated EEPROM" via
+  I/O port 0x1630/0x1634, but it's still unknown how to make it work
+
+## Untested
+
+- the dGPU model
+
+## Working
+
+- boot Arch Linux with Linux 4.19.77 from SeaBIOS payload
+- integrated graphics init with libgfxinit
+- EHCI debug: the port is the non-charging USB2 port on the right
+- video output: internal (eDP), miniDP, dock DP, dock HDMI
+- ACPI support
+- keyboard and trackpoint
+- SATA
+- M.2 SATA SSD
+- USB
+- Ethernet
+- WLAN
+- WWAN
+- bluetooth
+- virtualization: VT-x and VT-d
+- dock
+- CMOS options: wlan, trackpoint, fn_ctrl_swap
+- internal flashing when IFD is unlocked
+- using `me_cleaner`
+
+[Lenovo ThinkPad T440p]: https://pcsupport.lenovo.com/us/zh/products/laptops-and-netbooks/thinkpad-t-series-laptops/thinkpad-t440p
+[Hardware Maintenance Manual]: https://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/t440p_hmm_en_sp40a25467_04.pdf

Documentation/mainboard/lenovo/x301.md

@@ -0,0 +1,44 @@
+# Lenovo X301
+
+## Disassembly Instructions
+
+You must remove the following parts to access the SPI flash:
+
+![X301 with WSON8 chip replaced with SOIC8 chip](x301_kb_removed.jpg)
+
+* Battery pack
+* Keyboard
+
+Its [Hardware Maintenance Manual](https://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/43y9441.pdf) can be used as a guidance of disassembly.
+
+The WSON-8 flash chip (surrounded with red circle in the photo above,
+already replaced with a SOIC-8 one) sits under a piece of insulating
+tape. If solders between the chip and soldering pads fortunately
+overflows beside the chip as tiny tin balls attached to soldering pads,
+it will be possible to use a pomona 5250 clip to hold the chip, with
+its metal tips just attached to tin balls, thus connecting the chip to
+the programmer. Otherwise, it may be recommended to replace it with a
+SOIC-8 one (you might need to add the chip to the IFD VSCC list), as
+what is done in the photo.
+
+The vendor IFD VSCC list contains:
+    -MACRONIX_MX25L6405 (0xc2, 0x2017)
+    -WINBOND_NEX_W25X64 (0xef, 0x3017)
+    -ATMEL_AT25DF641 (0x1f, 0x4800)
+
+```eval_rst
+:doc:`../../flash_tutorial/ext_power`
+```
+Tested:
+    - CPU Core 2 Duo U9400
+    - Slotted DIMM 4GiB*2 from samsung
+    - Camera
+    - pci-e slots
+    - sata and usb2
+    - libgfxinit-based graphic init
+    - NVRAM options for North and South bridges
+    - Sound
+    - Thinkpad EC
+    - S3
+    - Linux 4.19.67-2 within Debian GNU/Linux stable, loaded from
+      Linux payload (Heads) and Seabios.

Documentation/mainboard/portwell/pq7-m107.md

@@ -4,9 +4,10 @@ This page describes how to run coreboot on the [Portwell PQ7-M107].
 
 PQ7-M107 are assembled with different onboard memory modules:
 	Rev 1.0	Onboard Samsung K4B8G1646D-MYKO memory
-	Rev 1.1	and 1.2 Onboard Micron MT41K512M16HA-125A memory
+	Rev 1.1 and 1.2 Onboard Micron MT41K512M16HA-125A memory
+	Rev 1.3	Onboard Kingston B5116ECMDXGGB memory
 
-Use 'make menuconfig' to configure `onboard memory manufacture` in Mainboard
+Use 'make menuconfig' to configure `onboard memory manufacturer` in Mainboard
 menu.
 
 ## Required blobs
@@ -53,7 +54,7 @@ serial/video/pcie ports might be available.
 - eMMC
 - SATA
 - serial port
-- SMbus
+- SMBus
 - HDA (codec on carrier)
 - initialization with FSP MR2
 - SeaBIOS payload (version rel-1.11.0-44-g7961917)

Documentation/mainboard/supermicro/x10slm-f.md

@@ -168,7 +168,7 @@ Please also see :doc:`../../northbridge/intel/haswell/known-issues`.
 - VGA graphics
 - disabling VGA graphics using the jumper
 - hiding the AST2400 using the CMOS setting
-- super I/O hardware monitor (see [Known issues](#known-issues))
+- Super I/O hardware monitor (see [Known issues](#known-issues))
 - initialisation with Haswell MRC version 1.6.1 build 2
 - flashrom under coreboot
 - Wake-on-LAN

Documentation/mainboard/supermicro/x11-lga1151-series/index.md

@@ -1,7 +0,0 @@
-# X11 LGA1151 series
-
-The supermicros X11 series with socket LGA1151 are mostly the same boards with some minor
-differences in internal and external interfaces like available PCIe slots, 1 GbE, 10 GbE,
-IPMI etc. This is why those boards are grouped as "X11 LGA1151 series".
-
-- [X11SSH-TF](x11ssh-tf/x11ssh-tf.md)

Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md

@@ -0,0 +1,62 @@
+# X11 LGA1151 series
+
+The [Supermicro X11 LGA1151 series] are mostly the same boards with some minor differences in
+internal and external interfaces like available PCIe slots, NICs (1 GbE, 10 GbE), IPMI, RAID
+Controller etc.
+
+## Supported boards
+
+- [X11SSH-TF](x11ssh-tf/x11ssh-tf.md)
+- [X11SSM-F](x11ssm-f/x11ssm-f.md)
+
+## Required proprietary blobs
+
+- [Intel FSP2.0]
+- Intel ME
+
+## De-blobbing
+
+- [Intel FSP2.0] can not be removed as long as there is no free replacement
+- Intel ME can be cleaned using me_cleaner (~4.5 MB more free space)
+- Intel Ethernet Controller Firmware can be removed when it's extended functionality is not
+  needed. For more details refer to the respective datasheet (e.g 333016-008 for I210).
+- Boards with [AST2400] BMC/IPMI: Firmware can be replaced by [OpenBMC]
+
+## Flashing coreboot
+
+Look at the [flashing tutorial] and the board-specific section.
+
+## Known issues
+
+These issues apply to all boards. Have a look at the board-specific issues, too.
+
+- TianoCore doesn't work with Aspeed NGI, as it's text mode only (Fix is WIP CB:35726)
+- MRC caching does not work with cold boot
+
+## ToDo
+
+- Fix issues above
+- Fix issues in board specific sections
+- Fix TODOs mentioned in code
+- Add more boards! :-)
+
+## Technology
+
+```eval_rst
++------------------+--------------------------------------------------+
+| CPU              | Intel Kaby Lake                                  |
++------------------+--------------------------------------------------+
+| PCH              | Intel C232/C236                                  |
++------------------+--------------------------------------------------+
+| Coprocessor      | Intel SPS (server version of the ME)             |
++------------------+--------------------------------------------------+
+```
+
+## Extra links
+
+[Supermicro X11 LGA1151 series]: https://www.supermicro.com/products/motherboard/Xeon3000/#1151
+[OpenBMC]: https://www.openbmc.org/
+[flashrom]: https://flashrom.org/Flashrom
+[flashing tutorial]: ../../../../flash_tutorial/ext_power.md
+[Intel FSP2.0]: ../../../../soc/intel/fsp/index.md
+[AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376

Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf.md

@@ -2,46 +2,40 @@
 
 This section details how to run coreboot on the [Supermicro X11SSH-TF].
 
-## Required proprietary blobs
-
-* [Intel FSP2.0]
-* Intel ME
-
 ## Flashing coreboot
 
-The board can be flashed externally using *some* programmers.
+The board can be flashed externally using *some* programmers. The CH341 was found working, while
-The CH341 was found working, while Dediprog won't detect the chip.
+Dediprog didn't detect the chip.
-
-For more details have a look at the [flashing tutorial].
 
 The flash IC can be found between the two PCIe slots near the southbridge:
 ![](x11ssh-tf_flash.jpg)
 
 ## BMC (IPMI)
 
-This board has an ASPEED [AST2400], which has BMC functionality. The
+This board has an ASPEED [AST2400], which has BMC/[IPMI] functionality. The BMC firmware resides
-BMC firmware resides in a 32 MiB SOIC-16 chip in the corner of the
+in a 32 MiB SOIC-16 chip in the corner of the mainboard near the [AST2400]. This chip is an
-mainboard near the [AST2400]. This chip is an [MX25L25635F].
+[MX25L25635F].
-
-## Known issues
-
-- Intel SGX causes secondary APs to crash (disabled for now).
-- Tianocore doesn't work with Aspeed NGI, as it's text mode only.
-- SMBus / I2C does not work (interrupt timeout)
 
 ## Tested and working
 
 - USB ports
-- M.2 2280 NVMe slot
+- Ethernet
-- 2x 10GB Ethernet
+- SATA ports
-- SATA
+- RS232 external
-- RS232
-- VGA on Aspeed
-- Super I/O initialisation
 - ECC DRAM detection
 - PCIe slots
-- TPM on TPM expansion header
+- M.2 2280 NVMe slot
 - BMC (IPMI)
+- VGA on Aspeed
+- TPM on TPM expansion header
+
+## Known issues
+
+See general issue section.
+
+## ToDo
+
+- Fix TODOs mentioned in code
 
 ## Technology
 
@@ -51,23 +45,46 @@ mainboard near the [AST2400]. This chip is an [MX25L25635F].
 +------------------+--------------------------------------------------+
 | PCH              | Intel C236                                       |
 +------------------+--------------------------------------------------+
-| Super I/O        | ASPEED AST2400                                   |
-+------------------+--------------------------------------------------+
 | Coprocessor      | Intel SPS (server version of the ME)             |
 +------------------+--------------------------------------------------+
-| Coprocessor      | ASPEED AST2400                                   |
+| Super I/O        | ASPEED AST2400                                   |
++------------------+--------------------------------------------------+
+| Ethernet         | 2x Intel® X550 10GBase-T Ethernet                |
+|                  | 1x dedicated BMC                                 |
++------------------+--------------------------------------------------+
+| PCIe slots       | 1x 3.0 x8                                        |
+|                  | 1x 3.0 x2 (in x4)                                |
+|                  | 1x 3.0 M.2 2260 x4 (Key M, with S-ATA)           |
++------------------+--------------------------------------------------+
+| USB slots        | 2x USB 2.0 (ext)                                 |
+|                  | 2x USB 3.0 (ext)                                 |
+|                  | 1x USB 3.0 (int)                                 |
+|                  | 1x dual USB 3.0 header                           |
+|                  | 2x dual USB 2.0 header                           |
++------------------+--------------------------------------------------+
+| SATA slots       | 8x SATA III                                      |
++------------------+--------------------------------------------------+
+| Other slots      | 1x RS232 (ext)                                   |
+|                  | 1x RS232 header                                  |
+|                  | 1x TPM header                                    |
+|                  | 1x Power SMB header                              |
+|                  | 6x PWM Fan connector                             |
+|                  | 2x I-SGPIO                                       |
+|                  | 2x S-ATA DOM Power connector                     |
+|                  | 1x XDP Port                                      |
+|                  | 1x External BMC I2C Header (for IPMI card)       |
+|                  | 1x Chassis Intrusion Header                      |
 +------------------+--------------------------------------------------+
 ```
 
 ## Extra links
 
+- [Supermicro X11SSH-TF]
 - [Board manual]
 
-[AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376
+[Supermicro X11SSH-TF]: https://www.supermicro.com/en/products/motherboard/X11SSH-TF
 [Board manual]: https://www.supermicro.com/manuals/motherboard/C236/MNL-1783.pdf
-[flashrom]: https://flashrom.org/Flashrom
+[AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376
+[IPMI]: ../../../../drivers/ipmi_kcs.md
 [MX25L25635F]: https://media.digikey.com/pdf/Data%20Sheets/Macronix/MX25L25635F.pdf
 [N25Q128A]: https://www.micron.com/~/media/Documents/Products/Data%20Sheet/NOR%20Flash/Serial%20NOR/N25Q/n25q_128mb_3v_65nm.pdf
-[flashing tutorial]: ../../../../flash_tutorial/ext_power.md
-[Intel FSP2.0]: ../../../../soc/intel/fsp/index.md
-[Supermicro X11SSH-TF]: https://www.supermicro.com/en/products/motherboard/X11SSH-TF

Documentation/mainboard/supermicro/x11-lga1151-series/x11ssm-f/x11ssm-f.md

@@ -0,0 +1,93 @@
+# Supermicro X11SSM-F
+
+This section details how to run coreboot on the [Supermicro X11SSM-F].
+
+## Flashing coreboot
+
+The board can be flashed externally. FTDI FT2232H and FT232H based programmers worked.
+
+The flash IC [MX25L12873F] can be found near PCH PCIe Slot 4. It is socketed on retail boards.
+
+For doing ISP (In-System-Programming) one needs to add a diode between VCC and the flash chip.
+
+## BMC (IPMI)
+
+This board has an ASPEED [AST2400], which has BMC/[IPMI] functionality. The BMC firmware resides in a
+32 MiB SOIC-16 chip in the corner of the mainboard near the PCH PCIe Slot 4. This chip is a
+[MX25L25635F].
+
+## Tested and working
+
+- GRUB2 payload with Debian testing and kernel 5.2
+- ECC ram (Linux' ie31200 driver works)
+- USB ports
+- Ethernet
+- SATA ports
+- RS232 external
+- PCIe slots
+- BMC (IPMI)
+- VGA on Aspeed
+- TPM on TPM expansion header
+
+## Known issues
+
+- See general issue section
+- "only partially covers this bridge" info from Linux kernel (what does that mean?)
+- LNXTHERM missing
+- S3 resume not working
+
+## ToDo
+
+- Fix TODOs mentioned in code
+
+## Technology
+
+```eval_rst
++------------------+--------------------------------------------------+
+| CPU              | Intel Kaby Lake                                  |
++------------------+--------------------------------------------------+
+| PCH              | Intel C236                                       |
++------------------+--------------------------------------------------+
+| Coprocessor      | Intel SPS (server version of the ME)             |
++------------------+--------------------------------------------------+
+| Super I/O        | ASPEED AST2400                                   |
++------------------+--------------------------------------------------+
+| Ethernet         | 2x Intel I210-AT 1 GbE                           |
+|                  | 1x dedicated BMC                                 |
++------------------+--------------------------------------------------+
+| PCIe slots       | 1x 3.0 x8                                        |
+|                  | 1x 3.0 x8 (in x16)                               |
+|                  | 2x 3.0 x4 (in x8)                                |
++------------------+--------------------------------------------------+
+| USB slots        | 2x USB 2.0 (ext)                                 |
+|                  | 2x USB 3.0 (ext)                                 |
+|                  | 1x USB 3.0 (int)                                 |
+|                  | 1x dual USB 3.0 header                           |
+|                  | 2x dual USB 2.0 header                           |
++------------------+--------------------------------------------------+
+| SATA slots       | 8x S-ATA III                                     |
++------------------+--------------------------------------------------+
+| Other slots      | 1x RS232 (ext)                                   |
+|                  | 1x RS232 header                                  |
+|                  | 1x TPM header                                    |
+|                  | 1x Power SMB header                              |
+|                  | 5x PWM Fan connector                             |
+|                  | 2x I-SGPIO                                       |
+|                  | 2x S-ATA DOM Power connector                     |
+|                  | 1x XDP Port                                      |
+|                  | 1x External BMC I2C Header (for IPMI card)       |
+|                  | 1x Chassis Intrusion Header                      |
++------------------+--------------------------------------------------+
+```
+
+## Extra links
+
+- [Supermicro X11SSM-F]
+- [Board manual]
+
+[Supermicro X11SSM-F]: https://www.supermicro.com/en/products/motherboard/X11SSM-F
+[Board manual]: https://www.supermicro.com/manuals/motherboard/C236/MNL-1785.pdf
+[AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376
+[IPMI]: ../../../../drivers/ipmi_kcs.md
+[MX25L25635F]: https://media.digikey.com/pdf/Data%20Sheets/Macronix/MX25L25635F.pdf
+[MX25L12873F]: https://media.digikey.com/pdf/Data%20Sheets/Macronix/MX25L12873F.pdf

Documentation/releases/coreboot-4.11-relnotes.md

@@ -11,7 +11,32 @@ notes.
 * The chip and board additions and removals will be updated right
   before the release, so those do not need to be added.
 
+Clean Up
+--------
+Because there was only a single developer board (AMD Torpedo)
+using AGESA family 12h, and because there were multiple,
+unique Coverity issues with it, the associated vendorcode will
+be removed shortly after this release.
+
 Significant changes
 -------------------
 
 ### Add significant changes here
+
+### `__PRE_RAM__` is deprecated
+
+Preprocessor use of `defined(__PRE_RAM_)` have been mostly replaced with
+`if (ENV_ROMSTAGE_OR_BEFORE)` or the inverse `if (ENV_RAMSTAGE)`.
+
+The remaining cases and `-D__PRE_RAM__` are to be removed soon after release.
+
+### `CAR_GLOBAL` is removed where possible
+
+For all platform code with `NO_CAR_GLOBAL_MIGRATION=y`, any `CAR_GLOBAL`
+attributes have been removed. Remaining cases from common code are to be
+removed soon after release.
+
+### `TSEG` and  `cbmem_top()` mapping
+
+Significant refactoring has bee done to achieve some consistency across platforms
+and to reduce code duplication.

Documentation/releases/index.md

@@ -10,6 +10,7 @@ Release notes for previous releases
 * [4.7 - January 2018](coreboot-4.7-relnotes.md)
 * [4.8 - May 2018](coreboot-4.8.1-relnotes.md)
 * [4.9 - December 2018](coreboot-4.9-relnotes.md)
+* [4.10 - July 2019](coreboot-4.10-relnotes.md)
 
 The checklist contains instructions to ensure that a release covers all
 important things and provides a reliable format for tarballs, branch
@@ -21,4 +22,4 @@ Upcoming release
 ----------------
 
 Please add to the release notes as changes are added:
-* [4.10 - April 2019](coreboot-4.10-relnotes.md)
+* [4.11 - October 2019](coreboot-4.11-relnotes.md)

Documentation/soc/amd/amdblobs_license.md

@@ -0,0 +1,68 @@
+# License Agreement for amd_blobs Repository
+
+## Abstract
+
+AMD has generated a simpler and more flexible license agreement for using
+proprietary precompiled binary images.  The new agreement is intended to cover
+all blobs in the directory structure below where the license resides and
+eliminates any unique agreements previously provided for individual products.
+
+A [3rdparty/amd_blobs](https://review.coreboot.org/admin/repos/amd_blobs) repo
+now exists for distributing new blobs to coreboot developers and consumers.
+Images for older products will be moved to amd_blobs as time permits.
+
+By cloning the amd_blobs repo, you will be agreeing to the license agreement
+contained there.
+
+## Text of License Agreement
+
+The language of the agreement is duplicated below for your reference.  The
+official license agreement may be found inside the Git repository.
+
+> Copyright (c) 2019 ADVANCED MICRO DEVICES, INC.
+>
+> READ CAREFULLY: DO NOT DOWNLOAD, COPY OR USE THE ASSOCIATED AMD SOFTWARE
+> ("LICENSED SOFTWARE") UNTIL YOU HAVE CAREFULLY READ THE FOLLOWING. BY USING
+> THE LICENSED SOFTWARE, YOU ARE AGREEING TO BE BOUND BY THE FOLLOWING TERMS:
+>
+> Redistribution and use in binary form, without modification, is permitted
+> subject to the following conditions:
+>
+> a. Reverse engineering, disassembly, or de-compilation of the Licensed
+> Software is not permitted;
+>
+> b. All the content of this document, including the above copyright notice and
+> below disclaimer, must be included in the documentation or other materials
+> provided with any distribution, and you may not alter or remove any copyright,
+> trademark or patent notice(s) in the Licensed Software; and,
+>
+> c. The name “AMD” or “Advanced Micro Devices” may not be used to promote
+> products derived from the Licensed Software.
+>
+> Except for the limited license expressly granted above, you have no other
+> rights in the Licensed Software, whether express, implied, arising by estoppel
+> or otherwise. The Licensed Software including all Intellectual Property Rights
+> therein is and remains the sole and exclusive property of AMD or its
+> licensors, and You shall have no right, title or interest therein except as
+> expressly set forth above.
+>
+> Disclaimer of Warranty. THE LICENSED SOFTWARE IS PROVIDED "AS IS" WITHOUT
+> WARRANTY OF ANY KIND. AMD DISCLAIMS ALL WARRANTIES, EXPRESS, IMPLIED, OR
+> STATUTORY, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+> MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND NON-
+> INFRINGEMENT, THAT THE LICENSED SOFTWARE WILL RUN UNINTERRUPTED OR ERROR-FREE
+> OR WARRANTIES ARISING FROM CUSTOM OF TRADE OR COURSE OF USAGE. THE ENTIRE RISK
+> ASSOCIATED WITH THE USE OF THE LICENSED SOFTWARE IS ASSUMED BY YOU INCLUDING,
+> WITHOUT LIMITATION, PERFORMANCE AND INTEROPERABILITY ISSUES THAT MAY ADVERSELY
+> AFFECT YOUR EXPERIENCE AND THE STABILITY OF YOUR COMPUTING SYSTEM; AND
+> (C) OTHER EXPERIENCES RESULTING IN ADVERSE EFFECTS, INCLUDING, BUT NOT
+> LIMITED, TO DATA CORRUPTION OR LOSS. AMD WILL NOT, UNDER ANY CIRCUMSTANCES BE
+> LIABLE TO YOU FOR ANY PUNITIVE, DIRECT, INCIDENTAL, INDIRECT, SPECIAL OR
+> CONSEQUENTIAL DAMAGES INCLUDING LOSS OF USE, PROFITS, OR DATA ARISING FROM USE
+> OF THE LICENSED SOFTWARE EVEN IF AMD AND ITS LICENSORS HAVE BEEN ADVISED OF
+> THE POSSIBILITY OF SUCH DAMAGES.
+>
+> The Licensed Software including all Intellectual Property Rights therein is
+> and remains the sole and exclusive property of AMD or its licensors, and You
+> shall have no right, title or interest therein except as expressly set forth
+> above or as required by law.

Documentation/soc/amd/index.md

@@ -7,3 +7,6 @@ This section contains documentation about coreboot on specific AMD SOCs.
 - [Family 15h](family15h.md)
 - [Family 17h](family17h.md)
 
+## amd_blobs Repository License
+
+- [amd_blobs](amdblobs_license.md)

Documentation/soc/index.md

@@ -7,3 +7,4 @@ This section contains documentation about coreboot on specific SOCs.
 - [AMD](amd/index.md)
 - [Cavium](cavium/index.md)
 - [Intel](intel/index.md)
+- [Qualcomm](qualcomm/index.md)

Documentation/soc/intel/fsp/index.md

@@ -21,6 +21,12 @@ those are fixed. If possible a workaround is described here as well.
   * Workaround: Don't disable this PCI device
   * Issue on public tracker: [Issue 13]
 
+* FSP Notify(EnumInitPhaseAfterPciEnumeration) hangs if 00:02.03/00:02.03 are hidden
+  * Release MR2
+  * Seems to get stuck on some SKUs only if hidden after MemoryInit
+  * Workaround: Hide before MemoryInit
+  * Issue on public tracker: [Issue 35]
+
 ### KabylakeFsp
 * MfgId and ModulePartNum in the DIMM_INFO struct are empty
   * Release 3.7.1
@@ -59,4 +65,5 @@ those are fixed. If possible a workaround is described here as well.
 [Issue 13]: https://github.com/IntelFsp/FSP/issues/13
 [Issue 15]: https://github.com/IntelFsp/FSP/issues/15
 [Issue 22]: https://github.com/IntelFsp/FSP/issues/22
+[Issue 35]: https://github.com/IntelFsp/FSP/issues/35
 

Documentation/soc/qualcomm/index.md

@@ -0,0 +1,7 @@
+# Qualcomm SOC-specific documentation
+
+This section contains documentation about coreboot on specific Qualcomm SOCs.
+
+## Platforms
+
+- [SC7180 series](sc7180/index.md)

Documentation/soc/qualcomm/sc7180/index.md

@@ -0,0 +1,19 @@
+# Qualcomm SC7180 documentation
+
+## SOC code
+
+The SOC folder contains functions for:
+* MMU
+* CLOCK
+* GPIO
+* QUPv3 FW (provides a bridge to serial interfaces)
+* UART
+* SPI-NOR
+* AOP FW
+* USB
+
+## Notes about the hardware
+
+The timer is used from the ARMv8 architecture specific code.
+
+

Documentation/superio/common/ssdt.md

@@ -19,7 +19,7 @@ I/O range and ISA IRQ number.
 
 This example is based on AST2400.
 
-```code
+```
 # Add a "container" for proper ACPI code generation
 chip superio/common
   device pnp 2e.0 on # just for the base device, not for the LDNs

Documentation/technotes/2015-11-rebuilding-coreboot-image-generation.md

@@ -0,0 +1,268 @@
+Rebuilding coreboot image generation
+====================================
+
+Current situation
+-----------------
+Chrome OS (CrOS) probably has the most complex image bundling process in the
+coreboot ecosystem. To make CrOS features more accessible to the wider
+coreboot community, we want to move these capabilities into upstream
+coreboot’s build system.
+
+Right now, the CrOS build system creates coreboot images, and various
+instances of the payload (with different configuration options), plus some
+more files (eg. EC firmware), then passes them to a CrOS-specific utility
+(`bundle_firmware.py`) to build the final image from that.
+
+`bundle_firmware` adds a flashmap (fmap) to the final image and creates
+additional CBFS filesystems in fmap regions. It then extracts some files from
+the original CBFS region (that was put in place carefully to later match to
+the default fmap region) and copies some of them into the others, as well as
+putting more data (eg. the bitmap data, keys) as raw data into other fmap
+regions.
+
+With the recent addition of more files to CBFS, both on the coreboot side
+(dsdt, FSP, and so on) and with Chrome OS specifics (eg. more files describing
+boot screens) we either need to expand the scope of bundle\_firmware or move
+the capability to build complex images to upstream coreboot’s build system.
+This document proposes to do the latter and outlines how this could be
+achieved.
+
+Problems with the current build system parts
+--------------------------------------------
+One common sentiment is that it should be possible to reuse some of the
+existing mechanisms that are supposed to be supplanted by this.
+The main concern during this design that precluded their use was that none of
+them provides a comprehensive solution to building complex coreboot based
+images:
+* fmap.dts and fmd provide a flash layout, but no assignment of files of regions
+* cbfs-files-y ends up as an internal make variable using
+  `weird|formatting|to|deal|with|make’s|limitations`
+* make isn’t powerful enough to deal with ordering these entries in said
+  variable to guarantee success if there’s enough room for the files. While that
+  could be added, that becomes more make macro work indistinguishable from magic
+  that people fail to understand, break and with good reason complain about
+  to work around such issues, Chrome OS firmware uses a custom tool with even
+  more special cases to finally build the image it needs. If coreboot upstream
+  is to support vboot, it should also be powerful enough not to need magic tools
+  that only live within downstream projects.
+
+Requirements
+------------
+A complete Chrome OS coreboot image consists of (depending on the device)
+* platform specific data in raw fmap regions (eg IFD, ME firmware),
+* the bootblock (coming from the bootblock),
+* three copies of coreboot, consisting of the stages (verstage, romstage,
+  ramstage) plus data,
+* depthcharge plus data (with each of the coreboot copies),
+* EC firmware files (with each of the coreboot copies),
+* signatures over several parts of the image and
+* some final checksumming over parts of the image to satisfy boot ROM
+  tests on ARM
+
+A complete upstream coreboot image (with fallback/normal switch configuration,
+using a yet to be implemented switching scheme based on fmaps) consists of
+* platform specific data in raw fmap regions (eg IFD, ME firmware),
+* two copies of coreboot, consisting of
+ * the bootblock and
+ * the stages (romstage, ramstage) plus data,
+* payload plus data (with each of the coreboot copies),
+
+Since a single platform is potentially built with different payload
+configurations (eg. modding a Chromebook to not use the verified Chrome OS
+boot scheme), some concerns need to be kept separate:
+* Platform requirements that have nothing to do with the payload or boot schemes
+ * IFD, ME, … need to copied to the right place
+ * boot ROM requirements such as checksums must be honored
+* Payload/boot scheme requirements
+ * Having one to three regions with certain files copied into them
+
+Proposal
+--------
+The proposal is based on manifest files that describe certain aspects of the
+final image.
+The number of manifest files may change over time, but this seems to be a
+reasonable approach for now. As long as coreboot uses fmap and cbfs, there
+should be few need to change the language, since composition is done through
+files.
+
+The final image is generated by a utility that is handed a number of manifests
+and the size of the flash (derived from `CONFIG_ROM_SIZE`). These manifest files
+deal with different concerns, with the following an example that should match
+current use cases:
+
+Chipset manifest
+----------------
+The chipset details if there are any non-coreboot regions, and assigns them
+names, locations, sizes and file contents and prepares a region for what is
+“platform visible” (eg. IFD’s BIOS region) that may be of flexible size
+(depending on the flash chip’s size). For the purpose of this document, that
+region is called “BIOS”.
+It can also specify if there’s a post processing requirement on the final
+image.
+
+coreboot manifest
+-----------------
+coreboot provides lists of the files it generates for each category it’s
+building (eg. bootblock, verstage, romstage, ramstage). They not only contain
+the stages themselves, but also additional files (eg. dsdt belongs to ramstage
+since that’s where it is used)
+
+Boot method manifest
+--------------------
+The boot method manifest can subdivide the BIOS region, eg. using it directly
+(for coreboot’s “simple” bootblock), splitting it in two (for coreboot’s
+fallback/normal) or in many parts (for Chrome OS, which requires two CBFS
+regions, one for GBB, several for VPD, …).
+It also specifies which of the file lists specified earlier belong in which
+region (eg. with verstage verifying romstage, verstage needs to be only in
+Chrome OS’ RO region, while romstage belongs in RO and both RW regions).
+It can also specify a post processing step that is executed before the
+chipset’s.
+
+Payload and additional manifests
+--------------------------------
+External components should also provide manifests to add files to categories.
+This way the payload and other components (eg. EC firmware) can be developed
+without needing to touch the central boot method manifest (that likely resides
+in the coreboot tree, given that coreboot needs to deal with choosing fmap
+regions already).
+
+coreboot build system
+---------------------
+The coreboot build system will be split more distinctly in two phases: The
+first is about building the files (with results like romstage.elf), while the
+second phase covers the assembly of the final image.
+
+By having a global picture of the final image’s requirements, we can also
+avoid issues where files added earlier may prevent later additions that have
+stricter constraints - without resorting to hacks like
+https://chromium-review.googlesource.com/289491 that reorder the file addition
+manually.
+
+Example
+-------
+As an example, we’ll define an Intel-based board with a postprocessing tool
+(something that doesn’t exist, but isn’t hard to imagine):
+
+It specifies an IFD region, an ME, and the BIOS region. After the image is
+built, the entire image needs to be processed (although the tool likely works
+only on a small part of it)
+
+It’s built in a Chrome OS-like configuration (simplified at places to avoid
+distracting from the important parts), so it has three CBFS regions, and
+several data regions for its own purpose (similar to GBB, FWID, VPD, …). After
+the regions are filled, one data region must be post-processed to contain
+signatures to enable verifying other regions.
+
+```
+Chipset manifest
+================
+# A region called IFD, starting at 0, ending at 4K
+region IFD: 0 4K
+# Add the specified file “raw” into the region.
+# If the file is smaller than the region, put it at the bottom and fill up
+# with 0xff
+raw IFD: build/ifd.bin align=bottom empty=0xff
+# Call the postprocessor on the data that ends up in IFD (in this example it
+# might lock the IFD)
+postprocess IFD: util/ifdprocess -l
+
+# a region called ME, starting at 4K, ending at 2M
+region ME: 4K 2M
+raw ME: 3rdparty/blobs/soc/intel/xanadu/me.bin align=bottom empty=0x00
+
+# a region called BIOS, starting at 2M, filling up the free space
+# filling up fails (build error) if two regions are requested to fill up
+# against each other
+region BIOS: 2M *
+
+# This would define a region that covers the last 4K of flash.
+# The BIOS region specified above will end right before it instead of
+# expanding to end of flash
+# region AUX: -4K -0
+
+# specify the tool that post-processes the entire image.
+postprocess image: util/intelchksum/intelchksum.sh
+
+coreboot manifest
+=================
+# declare that build/verstage.elf belongs into the group ‘verstage’
+# these groups are later referred to by the “cbfs” command.
+group verstage: build/verstage.elf stage xip name=fallback/verstage
+group romstage: build/romstage.elf stage xip name=fallback/romstage
+group ramstage: build/ramstage.elf stage name=fallback/ramstage
+compression=lzma
+group ramstage: build/dsdt.aml compression=lzma
+
+boot method manifest
+====================
+# Define RO as region inside BIOS, covering the upper half of the image.
+# It’s a build error if the result crosses outside BIOS.
+# math expressions are wrapped with ( ),
+# and mentions of regions therein always refer to their size
+subregion BIOS RO: ( image / 2 ) -0
+
+# Define RW to cover the rest of BIOS.
+# The order of RW and RO doesn’t matter except to keep comments clearer.
+# Dynamic items like RW (“*”) will be sized to fill unused space after
+# everything else is placed.
+subregion BIOS RW: 0 *
+
+# It may be necessary to separate the RO/RW definition into another manifest
+# file
+# that defines the RO configuration of the flash
+
+# Some more subregions, with dynamically calculated sizes
+subregion RW RW_A: 0 ( RW / 2 )
+subregion RW RW_B: * -0
+subregion RW_A FW_MAIN_A: RW_A * -0
+subregion RW_A VBLOCK_A: 0 64K
+# foo +bar specifies start + size, not (start, end)
+# also, start is given as “the end of VBLOCK_A”
+# (while using a region in the “end” field means “start of region”)
+subregion RW_A FWID_A: VBLOCK_A +64
+
+# To make the example not too verbose, RO only has the CBFS region
+subregion RO BOOTSTUB: 0 *
+
+# Postprocess the data that ends up in VBLOCK_A,
+# passing the listed regions as additional arguments.
+# Circular dependencies are build errors.
+postprocess VBLOCK_A(FW_MAIN_A): signtool
+
+# binding files to regions indirectly through groups
+cbfs BOOTSTUB: verstage, romstage, ramstage, payload
+cbfs FW_MAIN_A: romstage, ramstage, payload
+
+# defining defaults: unless overridden, in all regions that use CBFS (“*”),
+# we want all files to come with SHA256 hashes.
+# Wildcard defaults have lower priority than specific defaults.
+# Other conflicts lead to a build error.
+cbfsdefaults *: hash=sha3
+
+payload manifest
+================
+group payload: payload.elf payload
+group payload: bootscreen.jpg name=splashscreen.jpg type=splashscreen
+
+EC firmware manifest
+====================
+# overrides the cbfsdefault above
+group payload: ecrw.bin name=ecrw hash=sha256
+group payload: pdrw.bin name=pdrw hash=sha256
+```
+
+manifest parsing
+----------------
+The exact BNF is work in progress.
+
+Some parser rules are
+* one line per statement
+* '#' introduces a command until the end of line
+
+Some processing rules
+* When there’s a conflict (eg. two statements on what to do to a region,
+  overlap, anything that can’t be determined), that is a build error.
+* the order of statements doesn’t matter, enabling simple addition of more
+  manifests where the need arises.
+

Documentation/technotes/index.md

@@ -0,0 +1,4 @@
+# Technotes
+
+* [Dealing with Untrusted Input in SMM](2017-02-dealing-with-untrusted-input-in-smm.md)
+* [Rebuilding coreboot image generation](2015-11-rebuilding-coreboot-image-generation.md)

Documentation/util.md

@@ -1,4 +1,7 @@
 # Utilities
+
+## List of utils
+
 _Scripts and programs found in the `./util` directory_
 * __abuild__ - coreboot autobuild script builds coreboot images for all
 available targets. `bash`
@@ -131,3 +134,8 @@ CPUs. `C`
 * __x86__ - Generates 32-bit PAE page tables based on a CSV input file.
 `Go`
 * __xcompile__ - Cross compile setup `Bash`
+
+
+## In depth documentation
+
+* [ifdtool](ifdtool/index.md)

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LICENSES/CC-BY-4.0.txt

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LICENSES/CC-BY-SA-3.0.txt

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+d. Except as otherwise agreed in writing by the Licensor or as may be otherwise
+permitted by applicable law, if You Reproduce, Distribute or Publicly Perform
+the Work either by itself or as part of any Adaptations or Collections, You
+must not distort, mutilate, modify or take other derogatory action in relation
+to the Work which would be prejudicial to the Original Author's honor or reputation.
+Licensor agrees that in those jurisdictions (e.g. Japan), in which any exercise
+of the right granted in Section 3(b) of this License (the right to make Adaptations)
+would be deemed to be a distortion, mutilation, modification or other derogatory
+action prejudicial to the Original Author's honor and reputation, the Licensor
+will waive or not assert, as appropriate, this Section, to the fullest extent
+permitted by the applicable national law, to enable You to reasonably exercise
+Your right under Section 3(b) of this License (right to make Adaptations)
+but not otherwise.
+
+   5. Representations, Warranties and Disclaimer
+
+UNLESS OTHERWISE MUTUALLY AGREED TO BY THE PARTIES IN WRITING, LICENSOR OFFERS
+THE WORK AS-IS AND MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND CONCERNING
+THE WORK, EXPRESS, IMPLIED, STATUTORY OR OTHERWISE, INCLUDING, WITHOUT LIMITATION,
+WARRANTIES OF TITLE, MERCHANTIBILITY, FITNESS FOR A PARTICULAR PURPOSE, NONINFRINGEMENT,
+OR THE ABSENCE OF LATENT OR OTHER DEFECTS, ACCURACY, OR THE PRESENCE OF ABSENCE
+OF ERRORS, WHETHER OR NOT DISCOVERABLE. SOME JURISDICTIONS DO NOT ALLOW THE
+EXCLUSION OF IMPLIED WARRANTIES, SO SUCH EXCLUSION MAY NOT APPLY TO YOU.
+
+6. Limitation on Liability. EXCEPT TO THE EXTENT REQUIRED BY APPLICABLE LAW,
+IN NO EVENT WILL LICENSOR BE LIABLE TO YOU ON ANY LEGAL THEORY FOR ANY SPECIAL,
+INCIDENTAL, CONSEQUENTIAL, PUNITIVE OR EXEMPLARY DAMAGES ARISING OUT OF THIS
+LICENSE OR THE USE OF THE WORK, EVEN IF LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGES.
+
+   7. Termination
+
+a. This License and the rights granted hereunder will terminate automatically
+upon any breach by You of the terms of this License. Individuals or entities
+who have received Adaptations or Collections from You under this License,
+however, will not have their licenses terminated provided such individuals
+or entities remain in full compliance with those licenses. Sections 1, 2,
+5, 6, 7, and 8 will survive any termination of this License.
+
+b. Subject to the above terms and conditions, the license granted here is
+perpetual (for the duration of the applicable copyright in the Work). Notwithstanding
+the above, Licensor reserves the right to release the Work under different
+license terms or to stop distributing the Work at any time; provided, however
+that any such election will not serve to withdraw this License (or any other
+license that has been, or is required to be, granted under the terms of this
+License), and this License will continue in full force and effect unless terminated
+as stated above.
+
+   8. Miscellaneous
+
+a. Each time You Distribute or Publicly Perform the Work or a Collection,
+the Licensor offers to the recipient a license to the Work on the same terms
+and conditions as the license granted to You under this License.
+
+b. Each time You Distribute or Publicly Perform an Adaptation, Licensor offers
+to the recipient a license to the original Work on the same terms and conditions
+as the license granted to You under this License.
+
+c. If any provision of this License is invalid or unenforceable under applicable
+law, it shall not affect the validity or enforceability of the remainder of
+the terms of this License, and without further action by the parties to this
+agreement, such provision shall be reformed to the minimum extent necessary
+to make such provision valid and enforceable.
+
+d. No term or provision of this License shall be deemed waived and no breach
+consented to unless such waiver or consent shall be in writing and signed
+by the party to be charged with such waiver or consent.
+
+e. This License constitutes the entire agreement between the parties with
+respect to the Work licensed here. There are no understandings, agreements
+or representations with respect to the Work not specified here. Licensor shall
+not be bound by any additional provisions that may appear in any communication
+from You. This License may not be modified without the mutual written agreement
+of the Licensor and You.
+
+f. The rights granted under, and the subject matter referenced, in this License
+were drafted utilizing the terminology of the Berne Convention for the Protection
+of Literary and Artistic Works (as amended on September 28, 1979), the Rome
+Convention of 1961, the WIPO Copyright Treaty of 1996, the WIPO Performances
+and Phonograms Treaty of 1996 and the Universal Copyright Convention (as revised
+on July 24, 1971). These rights and subject matter take effect in the relevant
+jurisdiction in which the License terms are sought to be enforced according
+to the corresponding provisions of the implementation of those treaty provisions
+in the applicable national law. If the standard suite of rights granted under
+applicable copyright law includes additional rights not granted under this
+License, such additional rights are deemed to be included in the License;
+this License is not intended to restrict the license of any rights under applicable
+law.
+
+Creative Commons Notice
+
+Creative Commons is not a party to this License, and makes no warranty whatsoever
+in connection with the Work. Creative Commons will not be liable to You or
+any party on any legal theory for any damages whatsoever, including without
+limitation any general, special, incidental or consequential damages arising
+in connection to this license. Notwithstanding the foregoing two (2) sentences,
+if Creative Commons has expressly identified itself as the Licensor hereunder,
+it shall have all rights and obligations of Licensor.
+
+Except for the limited purpose of indicating to the public that the Work is
+licensed under the CCPL, Creative Commons does not authorize the use by either
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+Any permitted use will be in compliance with Creative Commons' then-current
+trademark usage guidelines, as may be published on its website or otherwise
+made available upon request from time to time. For the avoidance of doubt,
+this trademark restriction does not form part of the License.
+
+Creative Commons may be contacted at http://creativecommons.org/.

LICENSES/GPL-2.0-only.txt

@@ -0,0 +1,319 @@
+GNU GENERAL PUBLIC LICENSE
+
+Version 2, June 1991
+
+Copyright (C) 1989, 1991 Free Software Foundation, Inc. 
+
+51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+
+Everyone is permitted to copy and distribute verbatim copies of this license
+document, but changing it is not allowed.
+
+Preamble
+
+The licenses for most software are designed to take away your freedom to share
+and change it. By contrast, the GNU General Public License is intended to
+guarantee your freedom to share and change free software--to make sure the
+software is free for all its users. This General Public License applies to
+most of the Free Software Foundation's software and to any other program whose
+authors commit to using it. (Some other Free Software Foundation software
+is covered by the GNU Lesser General Public License instead.) You can apply
+it to your programs, too.
+
+When we speak of free software, we are referring to freedom, not price. Our
+General Public Licenses are designed to make sure that you have the freedom
+to distribute copies of free software (and charge for this service if you
+wish), that you receive source code or can get it if you want it, that you
+can change the software or use pieces of it in new free programs; and that
+you know you can do these things.
+
+To protect your rights, we need to make restrictions that forbid anyone to
+deny you these rights or to ask you to surrender the rights. These restrictions
+translate to certain responsibilities for you if you distribute copies of
+the software, or if you modify it.
+
+For example, if you distribute copies of such a program, whether gratis or
+for a fee, you must give the recipients all the rights that you have. You
+must make sure that they, too, receive or can get the source code. And you
+must show them these terms so they know their rights.
+
+We protect your rights with two steps: (1) copyright the software, and (2)
+offer you this license which gives you legal permission to copy, distribute
+and/or modify the software.
+
+Also, for each author's protection and ours, we want to make certain that
+everyone understands that there is no warranty for this free software. If
+the software is modified by someone else and passed on, we want its recipients
+to know that what they have is not the original, so that any problems introduced
+by others will not reflect on the original authors' reputations.
+
+Finally, any free program is threatened constantly by software patents. We
+wish to avoid the danger that redistributors of a free program will individually
+obtain patent licenses, in effect making the program proprietary. To prevent
+this, we have made it clear that any patent must be licensed for everyone's
+free use or not licensed at all.
+
+The precise terms and conditions for copying, distribution and modification
+follow.
+
+TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
+
+0. This License applies to any program or other work which contains a notice
+placed by the copyright holder saying it may be distributed under the terms
+of this General Public License. The "Program", below, refers to any such program
+or work, and a "work based on the Program" means either the Program or any
+derivative work under copyright law: that is to say, a work containing the
+Program or a portion of it, either verbatim or with modifications and/or translated
+into another language. (Hereinafter, translation is included without limitation
+in the term "modification".) Each licensee is addressed as "you".
+
+Activities other than copying, distribution and modification are not covered
+by this License; they are outside its scope. The act of running the Program
+is not restricted, and the output from the Program is covered only if its
+contents constitute a work based on the Program (independent of having been
+made by running the Program). Whether that is true depends on what the Program
+does.
+
+1. You may copy and distribute verbatim copies of the Program's source code
+as you receive it, in any medium, provided that you conspicuously and appropriately
+publish on each copy an appropriate copyright notice and disclaimer of warranty;
+keep intact all the notices that refer to this License and to the absence
+of any warranty; and give any other recipients of the Program a copy of this
+License along with the Program.
+
+You may charge a fee for the physical act of transferring a copy, and you
+may at your option offer warranty protection in exchange for a fee.
+
+2. You may modify your copy or copies of the Program or any portion of it,
+thus forming a work based on the Program, and copy and distribute such modifications
+or work under the terms of Section 1 above, provided that you also meet all
+of these conditions:
+
+a) You must cause the modified files to carry prominent notices stating that
+you changed the files and the date of any change.
+
+b) You must cause any work that you distribute or publish, that in whole or
+in part contains or is derived from the Program or any part thereof, to be
+licensed as a whole at no charge to all third parties under the terms of this
+License.
+
+c) If the modified program normally reads commands interactively when run,
+you must cause it, when started running for such interactive use in the most
+ordinary way, to print or display an announcement including an appropriate
+copyright notice and a notice that there is no warranty (or else, saying that
+you provide a warranty) and that users may redistribute the program under
+these conditions, and telling the user how to view a copy of this License.
+(Exception: if the Program itself is interactive but does not normally print
+such an announcement, your work based on the Program is not required to print
+an announcement.)
+
+These requirements apply to the modified work as a whole. If identifiable
+sections of that work are not derived from the Program, and can be reasonably
+considered independent and separate works in themselves, then this License,
+and its terms, do not apply to those sections when you distribute them as
+separate works. But when you distribute the same sections as part of a whole
+which is a work based on the Program, the distribution of the whole must be
+on the terms of this License, whose permissions for other licensees extend
+to the entire whole, and thus to each and every part regardless of who wrote
+it.
+
+Thus, it is not the intent of this section to claim rights or contest your
+rights to work written entirely by you; rather, the intent is to exercise
+the right to control the distribution of derivative or collective works based
+on the Program.
+
+In addition, mere aggregation of another work not based on the Program with
+the Program (or with a work based on the Program) on a volume of a storage
+or distribution medium does not bring the other work under the scope of this
+License.
+
+3. You may copy and distribute the Program (or a work based on it, under Section
+2) in object code or executable form under the terms of Sections 1 and 2 above
+provided that you also do one of the following:
+
+a) Accompany it with the complete corresponding machine-readable source code,
+which must be distributed under the terms of Sections 1 and 2 above on a medium
+customarily used for software interchange; or,
+
+b) Accompany it with a written offer, valid for at least three years, to give
+any third party, for a charge no more than your cost of physically performing
+source distribution, a complete machine-readable copy of the corresponding
+source code, to be distributed under the terms of Sections 1 and 2 above on
+a medium customarily used for software interchange; or,
+
+c) Accompany it with the information you received as to the offer to distribute
+corresponding source code. (This alternative is allowed only for noncommercial
+distribution and only if you received the program in object code or executable
+form with such an offer, in accord with Subsection b above.)
+
+The source code for a work means the preferred form of the work for making
+modifications to it. For an executable work, complete source code means all
+the source code for all modules it contains, plus any associated interface
+definition files, plus the scripts used to control compilation and installation
+of the executable. However, as a special exception, the source code distributed
+need not include anything that is normally distributed (in either source or
+binary form) with the major components (compiler, kernel, and so on) of the
+operating system on which the executable runs, unless that component itself
+accompanies the executable.
+
+If distribution of executable or object code is made by offering access to
+copy from a designated place, then offering equivalent access to copy the
+source code from the same place counts as distribution of the source code,
+even though third parties are not compelled to copy the source along with
+the object code.
+
+4. You may not copy, modify, sublicense, or distribute the Program except
+as expressly provided under this License. Any attempt otherwise to copy, modify,
+sublicense or distribute the Program is void, and will automatically terminate
+your rights under this License. However, parties who have received copies,
+or rights, from you under this License will not have their licenses terminated
+so long as such parties remain in full compliance.
+
+5. You are not required to accept this License, since you have not signed
+it. However, nothing else grants you permission to modify or distribute the
+Program or its derivative works. These actions are prohibited by law if you
+do not accept this License. Therefore, by modifying or distributing the Program
+(or any work based on the Program), you indicate your acceptance of this License
+to do so, and all its terms and conditions for copying, distributing or modifying
+the Program or works based on it.
+
+6. Each time you redistribute the Program (or any work based on the Program),
+the recipient automatically receives a license from the original licensor
+to copy, distribute or modify the Program subject to these terms and conditions.
+You may not impose any further restrictions on the recipients' exercise of
+the rights granted herein. You are not responsible for enforcing compliance
+by third parties to this License.
+
+7. If, as a consequence of a court judgment or allegation of patent infringement
+or for any other reason (not limited to patent issues), conditions are imposed
+on you (whether by court order, agreement or otherwise) that contradict the
+conditions of this License, they do not excuse you from the conditions of
+this License. If you cannot distribute so as to satisfy simultaneously your
+obligations under this License and any other pertinent obligations, then as
+a consequence you may not distribute the Program at all. For example, if a
+patent license would not permit royalty-free redistribution of the Program
+by all those who receive copies directly or indirectly through you, then the
+only way you could satisfy both it and this License would be to refrain entirely
+from distribution of the Program.
+
+If any portion of this section is held invalid or unenforceable under any
+particular circumstance, the balance of the section is intended to apply and
+the section as a whole is intended to apply in other circumstances.
+
+It is not the purpose of this section to induce you to infringe any patents
+or other property right claims or to contest validity of any such claims;
+this section has the sole purpose of protecting the integrity of the free
+software distribution system, which is implemented by public license practices.
+Many people have made generous contributions to the wide range of software
+distributed through that system in reliance on consistent application of that
+system; it is up to the author/donor to decide if he or she is willing to
+distribute software through any other system and a licensee cannot impose
+that choice.
+
+This section is intended to make thoroughly clear what is believed to be a
+consequence of the rest of this License.
+
+8. If the distribution and/or use of the Program is restricted in certain
+countries either by patents or by copyrighted interfaces, the original copyright
+holder who places the Program under this License may add an explicit geographical
+distribution limitation excluding those countries, so that distribution is
+permitted only in or among countries not thus excluded. In such case, this
+License incorporates the limitation as if written in the body of this License.
+
+9. The Free Software Foundation may publish revised and/or new versions of
+the General Public License from time to time. Such new versions will be similar
+in spirit to the present version, but may differ in detail to address new
+problems or concerns.
+
+Each version is given a distinguishing version number. If the Program specifies
+a version number of this License which applies to it and "any later version",
+you have the option of following the terms and conditions either of that version
+or of any later version published by the Free Software Foundation. If the
+Program does not specify a version number of this License, you may choose
+any version ever published by the Free Software Foundation.
+
+10. If you wish to incorporate parts of the Program into other free programs
+whose distribution conditions are different, write to the author to ask for
+permission. For software which is copyrighted by the Free Software Foundation,
+write to the Free Software Foundation; we sometimes make exceptions for this.
+Our decision will be guided by the two goals of preserving the free status
+of all derivatives of our free software and of promoting the sharing and reuse
+of software generally.
+
+   NO WARRANTY
+
+11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY FOR
+THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE
+STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM
+"AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING,
+BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE
+OF THE PROGRAM IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME
+THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
+
+12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
+WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR REDISTRIBUTE
+THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY
+GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE
+OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF DATA
+OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES
+OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH
+HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+END OF TERMS AND CONDITIONS
+
+How to Apply These Terms to Your New Programs
+
+If you develop a new program, and you want it to be of the greatest possible
+use to the public, the best way to achieve this is to make it free software
+which everyone can redistribute and change under these terms.
+
+To do so, attach the following notices to the program. It is safest to attach
+them to the start of each source file to most effectively convey the exclusion
+of warranty; and each file should have at least the "copyright" line and a
+pointer to where the full notice is found.
+
+<one line to give the program's name and an idea of what it does.>
+
+Copyright (C)< yyyy> <name of author>
+
+This program is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software
+Foundation; either version 2 of the License, or (at your option) any later
+version.
+
+This program is distributed in the hope that it will be useful, but WITHOUT
+ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along with
+this program; if not, write to the Free Software Foundation, Inc., 51 Franklin
+Street, Fifth Floor, Boston, MA 02110-1301, USA.
+
+Also add information on how to contact you by electronic and paper mail.
+
+If the program is interactive, make it output a short notice like this when
+it starts in an interactive mode:
+
+Gnomovision version 69, Copyright (C) year name of author Gnomovision comes
+with ABSOLUTELY NO WARRANTY; for details type `show w'. This is free software,
+and you are welcome to redistribute it under certain conditions; type `show
+c' for details.
+
+The hypothetical commands `show w' and `show c' should show the appropriate
+parts of the General Public License. Of course, the commands you use may be
+called something other than `show w' and `show c'; they could even be mouse-clicks
+or menu items--whatever suits your program.
+
+You should also get your employer (if you work as a programmer) or your school,
+if any, to sign a "copyright disclaimer" for the program, if necessary. Here
+is a sample; alter the names:
+
+Yoyodyne, Inc., hereby disclaims all copyright interest in the program `Gnomovision'
+(which makes passes at compilers) written by James Hacker.
+
+<signature of Ty Coon >, 1 April 1989 Ty Coon, President of Vice This General
+Public License does not permit incorporating your program into proprietary
+programs. If your program is a subroutine library, you may consider it more
+useful to permit linking proprietary applications with the library. If this
+is what you want to do, use the GNU Lesser General Public License instead
+of this License.

LICENSES/GPL-2.0-or-later.txt

@@ -0,0 +1,319 @@
+GNU GENERAL PUBLIC LICENSE
+
+Version 2, June 1991
+
+Copyright (C) 1989, 1991 Free Software Foundation, Inc. 
+
+51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+
+Everyone is permitted to copy and distribute verbatim copies of this license
+document, but changing it is not allowed.
+
+Preamble
+
+The licenses for most software are designed to take away your freedom to share
+and change it. By contrast, the GNU General Public License is intended to
+guarantee your freedom to share and change free software--to make sure the
+software is free for all its users. This General Public License applies to
+most of the Free Software Foundation's software and to any other program whose
+authors commit to using it. (Some other Free Software Foundation software
+is covered by the GNU Lesser General Public License instead.) You can apply
+it to your programs, too.
+
+When we speak of free software, we are referring to freedom, not price. Our
+General Public Licenses are designed to make sure that you have the freedom
+to distribute copies of free software (and charge for this service if you
+wish), that you receive source code or can get it if you want it, that you
+can change the software or use pieces of it in new free programs; and that
+you know you can do these things.
+
+To protect your rights, we need to make restrictions that forbid anyone to
+deny you these rights or to ask you to surrender the rights. These restrictions
+translate to certain responsibilities for you if you distribute copies of
+the software, or if you modify it.
+
+For example, if you distribute copies of such a program, whether gratis or
+for a fee, you must give the recipients all the rights that you have. You
+must make sure that they, too, receive or can get the source code. And you
+must show them these terms so they know their rights.
+
+We protect your rights with two steps: (1) copyright the software, and (2)
+offer you this license which gives you legal permission to copy, distribute
+and/or modify the software.
+
+Also, for each author's protection and ours, we want to make certain that
+everyone understands that there is no warranty for this free software. If
+the software is modified by someone else and passed on, we want its recipients
+to know that what they have is not the original, so that any problems introduced
+by others will not reflect on the original authors' reputations.
+
+Finally, any free program is threatened constantly by software patents. We
+wish to avoid the danger that redistributors of a free program will individually
+obtain patent licenses, in effect making the program proprietary. To prevent
+this, we have made it clear that any patent must be licensed for everyone's
+free use or not licensed at all.
+
+The precise terms and conditions for copying, distribution and modification
+follow.
+
+TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
+
+0. This License applies to any program or other work which contains a notice
+placed by the copyright holder saying it may be distributed under the terms
+of this General Public License. The "Program", below, refers to any such program
+or work, and a "work based on the Program" means either the Program or any
+derivative work under copyright law: that is to say, a work containing the
+Program or a portion of it, either verbatim or with modifications and/or translated
+into another language. (Hereinafter, translation is included without limitation
+in the term "modification".) Each licensee is addressed as "you".
+
+Activities other than copying, distribution and modification are not covered
+by this License; they are outside its scope. The act of running the Program
+is not restricted, and the output from the Program is covered only if its
+contents constitute a work based on the Program (independent of having been
+made by running the Program). Whether that is true depends on what the Program
+does.
+
+1. You may copy and distribute verbatim copies of the Program's source code
+as you receive it, in any medium, provided that you conspicuously and appropriately
+publish on each copy an appropriate copyright notice and disclaimer of warranty;
+keep intact all the notices that refer to this License and to the absence
+of any warranty; and give any other recipients of the Program a copy of this
+License along with the Program.
+
+You may charge a fee for the physical act of transferring a copy, and you
+may at your option offer warranty protection in exchange for a fee.
+
+2. You may modify your copy or copies of the Program or any portion of it,
+thus forming a work based on the Program, and copy and distribute such modifications
+or work under the terms of Section 1 above, provided that you also meet all
+of these conditions:
+
+a) You must cause the modified files to carry prominent notices stating that
+you changed the files and the date of any change.
+
+b) You must cause any work that you distribute or publish, that in whole or
+in part contains or is derived from the Program or any part thereof, to be
+licensed as a whole at no charge to all third parties under the terms of this
+License.
+
+c) If the modified program normally reads commands interactively when run,
+you must cause it, when started running for such interactive use in the most
+ordinary way, to print or display an announcement including an appropriate
+copyright notice and a notice that there is no warranty (or else, saying that
+you provide a warranty) and that users may redistribute the program under
+these conditions, and telling the user how to view a copy of this License.
+(Exception: if the Program itself is interactive but does not normally print
+such an announcement, your work based on the Program is not required to print
+an announcement.)
+
+These requirements apply to the modified work as a whole. If identifiable
+sections of that work are not derived from the Program, and can be reasonably
+considered independent and separate works in themselves, then this License,
+and its terms, do not apply to those sections when you distribute them as
+separate works. But when you distribute the same sections as part of a whole
+which is a work based on the Program, the distribution of the whole must be
+on the terms of this License, whose permissions for other licensees extend
+to the entire whole, and thus to each and every part regardless of who wrote
+it.
+
+Thus, it is not the intent of this section to claim rights or contest your
+rights to work written entirely by you; rather, the intent is to exercise
+the right to control the distribution of derivative or collective works based
+on the Program.
+
+In addition, mere aggregation of another work not based on the Program with
+the Program (or with a work based on the Program) on a volume of a storage
+or distribution medium does not bring the other work under the scope of this
+License.
+
+3. You may copy and distribute the Program (or a work based on it, under Section
+2) in object code or executable form under the terms of Sections 1 and 2 above
+provided that you also do one of the following:
+
+a) Accompany it with the complete corresponding machine-readable source code,
+which must be distributed under the terms of Sections 1 and 2 above on a medium
+customarily used for software interchange; or,
+
+b) Accompany it with a written offer, valid for at least three years, to give
+any third party, for a charge no more than your cost of physically performing
+source distribution, a complete machine-readable copy of the corresponding
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+
+4. You may not copy, modify, sublicense, or distribute the Program except
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+sublicense or distribute the Program is void, and will automatically terminate
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+
+This section is intended to make thoroughly clear what is believed to be a
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+8. If the distribution and/or use of the Program is restricted in certain
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+
+9. The Free Software Foundation may publish revised and/or new versions of
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+Each version is given a distinguishing version number. If the Program specifies
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+10. If you wish to incorporate parts of the Program into other free programs
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+
+   NO WARRANTY
+
+11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY FOR
+THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE
+STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM
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+BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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+
+12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
+WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR REDISTRIBUTE
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+OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH
+HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+END OF TERMS AND CONDITIONS
+
+How to Apply These Terms to Your New Programs
+
+If you develop a new program, and you want it to be of the greatest possible
+use to the public, the best way to achieve this is to make it free software
+which everyone can redistribute and change under these terms.
+
+To do so, attach the following notices to the program. It is safest to attach
+them to the start of each source file to most effectively convey the exclusion
+of warranty; and each file should have at least the "copyright" line and a
+pointer to where the full notice is found.
+
+<one line to give the program's name and an idea of what it does.>
+
+Copyright (C) <yyyy> <name of author>
+
+This program is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software
+Foundation; either version 2 of the License, or (at your option) any later
+version.
+
+This program is distributed in the hope that it will be useful, but WITHOUT
+ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along with
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+Street, Fifth Floor, Boston, MA 02110-1301, USA.
+
+Also add information on how to contact you by electronic and paper mail.
+
+If the program is interactive, make it output a short notice like this when
+it starts in an interactive mode:
+
+Gnomovision version 69, Copyright (C) year name of author Gnomovision comes
+with ABSOLUTELY NO WARRANTY; for details type `show w'. This is free software,
+and you are welcome to redistribute it under certain conditions; type `show
+c' for details.
+
+The hypothetical commands `show w' and `show c' should show the appropriate
+parts of the General Public License. Of course, the commands you use may be
+called something other than `show w' and `show c'; they could even be mouse-clicks
+or menu items--whatever suits your program.
+
+You should also get your employer (if you work as a programmer) or your school,
+if any, to sign a "copyright disclaimer" for the program, if necessary. Here
+is a sample; alter the names:
+
+Yoyodyne, Inc., hereby disclaims all copyright interest in the program `Gnomovision'
+(which makes passes at compilers) written by James Hacker.
+
+<signature of Ty Coon>, 1 April 1989 Ty Coon, President of Vice This General
+Public License does not permit incorporating your program into proprietary
+programs. If your program is a subroutine library, you may consider it more
+useful to permit linking proprietary applications with the library. If this
+is what you want to do, use the GNU Lesser General Public License instead
+of this License.

LICENSES/GPL-3.0-only.txt

@@ -0,0 +1,625 @@
+GNU GENERAL PUBLIC LICENSE
+
+Version 3, 29 June 2007
+
+Copyright © 2007 Free Software Foundation, Inc. <https://fsf.org/>
+
+Everyone is permitted to copy and distribute verbatim copies of this license
+document, but changing it is not allowed.
+
+Preamble
+
+The GNU General Public License is a free, copyleft license for software and
+other kinds of works.
+
+The licenses for most software and other practical works are designed to take
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+Public License is intended to guarantee your freedom to share and change all
+versions of a program--to make sure it remains free software for all its users.
+We, the Free Software Foundation, use the GNU General Public License for most
+of our software; it applies also to any other work released this way by its
+authors. You can apply it to your programs, too.
+
+When we speak of free software, we are referring to freedom, not price. Our
+General Public Licenses are designed to make sure that you have the freedom
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+Developers that use the GNU GPL protect your rights with two steps: (1) assert
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+TERMS AND CONDITIONS
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+   0. Definitions.
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+   "This License" refers to version 3 of the GNU General Public License.
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+or options, such as a menu, a prominent item in the list meets this criterion.
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+   1. Source Code.
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+The "source code" for a work means the preferred form of the work for making
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+You may convey verbatim copies of the Program's source code as you receive
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+You may convey a covered work in object code form under the terms of sections
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+
+   7. Additional Terms.
+
+"Additional permissions" are terms that supplement the terms of this License
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+were included in this License, to the extent that they are valid under applicable
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+may be used separately under those permissions, but the entire Program remains
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+When you convey a copy of a covered work, you may at your option remove any
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+
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+
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+licenses /why-not-lgpl.html>.

LICENSES/GPL-3.0-or-later.txt

@@ -0,0 +1,625 @@
+GNU GENERAL PUBLIC LICENSE
+
+Version 3, 29 June 2007
+
+Copyright © 2007 Free Software Foundation, Inc. <https://fsf.org/>
+
+Everyone is permitted to copy and distribute verbatim copies of this license
+document, but changing it is not allowed.
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+Preamble
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+The licenses for most software and other practical works are designed to take
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+All other non-permissive additional terms are considered "further restrictions"
+within the meaning of section 10. If the Program as you received it, or any
+part of it, contains a notice stating that it is governed by this License
+along with a term that is a further restriction, you may remove that term.
+If a license document contains a further restriction but permits relicensing
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+If you add terms to a covered work in accord with this section, you must place,
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+
+Additional terms, permissive or non-permissive, may be stated in the form
+of a separately written license, or stated as exceptions; the above requirements
+apply either way.
+
+   8. Termination.
+
+You may not propagate or modify a covered work except as expressly provided
+under this License. Any attempt otherwise to propagate or modify it is void,
+and will automatically terminate your rights under this License (including
+any patent licenses granted under the third paragraph of section 11).
+
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+
+Moreover, your license from a particular copyright holder is reinstated permanently
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+
+Termination of your rights under this section does not terminate the licenses
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+If your rights have been terminated and not permanently reinstated, you do
+not qualify to receive new licenses for the same material under section 10.
+
+   9. Acceptance Not Required for Having Copies.
+
+You are not required to accept this License in order to receive or run a copy
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+a consequence of using peer-to-peer transmission to receive a copy likewise
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+
+   10. Automatic Licensing of Downstream Recipients.
+
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+by making, using, selling, offering for sale, or importing the Program or
+any portion of it.
+
+   11. Patents.
+
+A "contributor" is a copyright holder who authorizes use under this License
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+is called the contributor's "contributor version".
+
+A contributor's "essential patent claims" are all patent claims owned or controlled
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+cause the Corresponding Source to be so available, or (2) arrange to deprive
+yourself of the benefit of the patent license for this particular work, or
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+means you have actual knowledge that, but for the patent license, your conveying
+the covered work in a country, or your recipient's use of the covered work
+in a country, would infringe one or more identifiable patents in that country
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+
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+a patent license to some of the parties receiving the covered work authorizing
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+of the covered work and works based on it.
+
+A patent license is "discriminatory" if it does not include within the scope
+of its coverage, prohibits the exercise of, or is conditioned on the non-exercise
+of one or more of the rights that are specifically granted under this License.
+You may not convey a covered work if you are a party to an arrangement with
+a third party that is in the business of distributing software, under which
+you make payment to the third party based on the extent of your activity of
+conveying the work, and under which the third party grants, to any of the
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+with specific products or compilations that contain the covered work, unless
+you entered into that arrangement, or that patent license was granted, prior
+to 28 March 2007.
+
+Nothing in this License shall be construed as excluding or limiting any implied
+license or other defenses to infringement that may otherwise be available
+to you under applicable patent law.
+
+   12. No Surrender of Others' Freedom.
+
+If conditions are imposed on you (whether by court order, agreement or otherwise)
+that contradict the conditions of this License, they do not excuse you from
+the conditions of this License. If you cannot convey a covered work so as
+to satisfy simultaneously your obligations under this License and any other
+pertinent obligations, then as a consequence you may not convey it at all.
+For example, if you agree to terms that obligate you to collect a royalty
+for further conveying from those to whom you convey the Program, the only
+way you could satisfy both those terms and this License would be to refrain
+entirely from conveying the Program.
+
+   13. Use with the GNU Affero General Public License.
+
+Notwithstanding any other provision of this License, you have permission to
+link or combine any covered work with a work licensed under version 3 of the
+GNU Affero General Public License into a single combined work, and to convey
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+part which is the covered work, but the special requirements of the GNU Affero
+General Public License, section 13, concerning interaction through a network
+will apply to the combination as such.
+
+   14. Revised Versions of this License.
+
+The Free Software Foundation may publish revised and/or new versions of the
+GNU General Public License from time to time. Such new versions will be similar
+in spirit to the present version, but may differ in detail to address new
+problems or concerns.
+
+Each version is given a distinguishing version number. If the Program specifies
+that a certain numbered version of the GNU General Public License "or any
+later version" applies to it, you have the option of following the terms and
+conditions either of that numbered version or of any later version published
+by the Free Software Foundation. If the Program does not specify a version
+number of the GNU General Public License, you may choose any version ever
+published by the Free Software Foundation.
+
+If the Program specifies that a proxy can decide which future versions of
+the GNU General Public License can be used, that proxy's public statement
+of acceptance of a version permanently authorizes you to choose that version
+for the Program.
+
+Later license versions may give you additional or different permissions. However,
+no additional obligations are imposed on any author or copyright holder as
+a result of your choosing to follow a later version.
+
+   15. Disclaimer of Warranty.
+
+THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE
+LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR
+OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
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+TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE PROGRAM
+PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR
+CORRECTION.
+
+   16. Limitation of Liability.
+
+IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL
+ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS THE PROGRAM
+AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL,
+INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO
+USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED
+INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE
+PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR OTHER
+PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+
+   17. Interpretation of Sections 15 and 16.
+
+If the disclaimer of warranty and limitation of liability provided above cannot
+be given local legal effect according to their terms, reviewing courts shall
+apply local law that most closely approximates an absolute waiver of all civil
+liability in connection with the Program, unless a warranty or assumption
+of liability accompanies a copy of the Program in return for a fee. END OF
+TERMS AND CONDITIONS
+
+How to Apply These Terms to Your New Programs
+
+If you develop a new program, and you want it to be of the greatest possible
+use to the public, the best way to achieve this is to make it free software
+which everyone can redistribute and change under these terms.
+
+To do so, attach the following notices to the program. It is safest to attach
+them to the start of each source file to most effectively state the exclusion
+of warranty; and each file should have at least the "copyright" line and a
+pointer to where the full notice is found.
+
+<one line to give the program's name and a brief idea of what it does.>
+
+Copyright (C) <year> <name of author>
+
+This program is free software: you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software
+Foundation, either version 3 of the License, or (at your option) any later
+version.
+
+This program is distributed in the hope that it will be useful, but WITHOUT
+ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along with
+this program. If not, see <https://www.gnu.org/licenses/>.
+
+Also add information on how to contact you by electronic and paper mail.
+
+If the program does terminal interaction, make it output a short notice like
+this when it starts in an interactive mode:
+
+<program> Copyright (C) <year> <name of author>
+
+This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+
+This is free software, and you are welcome to redistribute it under certain
+conditions; type `show c' for details.
+
+The hypothetical commands `show w' and `show c' should show the appropriate
+parts of the General Public License. Of course, your program's commands might
+be different; for a GUI interface, you would use an "about box".
+
+You should also get your employer (if you work as a programmer) or school,
+if any, to sign a "copyright disclaimer" for the program, if necessary. For
+more information on this, and how to apply and follow the GNU GPL, see <https://www.gnu.org/licenses/>.
+
+The GNU General Public License does not permit incorporating your program
+into proprietary programs. If your program is a subroutine library, you may
+consider it more useful to permit linking proprietary applications with the
+library. If this is what you want to do, use the GNU Lesser General Public
+License instead of this License. But first, please read <https://www.gnu.org/
+licenses /why-not-lgpl.html>.

LICENSES/ISC.txt

@@ -0,0 +1,14 @@
+ISC License Copyright (c) 2004-2010 by Internet Systems Consortium, Inc. ("ISC")
+
+Copyright (c) 1995-2003 by Internet Software Consortium
+
+Permission to use, copy, modify, and /or distribute this software for any
+purpose with or without fee is hereby granted, provided that the above copyright
+notice and this permission notice appear in all copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND ISC DISCLAIMS ALL WARRANTIES WITH REGARD
+TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS.
+IN NO EVENT SHALL ISC BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,
+WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

LICENSES/MIT.txt

@@ -0,0 +1,19 @@
+MIT License Copyright (c) <year> <copyright holders>
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is furnished
+to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice (including the next
+paragraph) shall be included in all copies or substantial portions of the
+Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
+OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

LICENSES/X11.txt

@@ -0,0 +1,24 @@
+X11 License Copyright (C) 1996 X Consortium
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is furnished
+to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM
+BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH
+THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+Except as contained in this notice, the name of the X Consortium shall not
+be used in advertising or otherwise to promote the sale, use or other dealings
+in this Software without prior written authorization from the X Consortium.
+
+X Window System is a trademark of X Consortium, Inc.

MAINTAINERS

@@ -391,6 +391,11 @@ M:	Tristan Corrick <tristan@corrick.kiwi>
 S:	Maintained
 F:	src/mainboard/supermicro/x10slm-f/
 
+SUPERMICRO X11-LGA1151-SERIES
+M:	Michael Niewöhner <foss@mniewoehner.de>
+S:	Maintained
+F:	src/mainboard/supermicro/x11-lga1151-series
+
 FACEBOOK FBG1701 MAINBOARD
 M:	Frans Hendriks <fhendriks@eltan.com>
 M:	Wim Vervoorn <wvervoorn@eltan.com>

Makefile

@@ -144,12 +144,11 @@ endif
 	\mv -f $@.tmp $@ 2> /dev/null
 	rm -f $@.tmp
 
--include $(TOPLEVEL)/site-local/Makefile.inc
-
 ifeq ($(NOCOMPILE),1)
 include $(TOPLEVEL)/Makefile.inc
 include $(TOPLEVEL)/payloads/Makefile.inc
 include $(TOPLEVEL)/util/testing/Makefile.inc
+-include $(TOPLEVEL)/site-local/Makefile.inc
 real-all:
 	@echo "Error: Expected config file ($(DOTCONFIG)) not present." >&2
 	@echo "Please specify a config file or run 'make menuconfig' to" >&2
@@ -195,7 +194,7 @@ $(KCONFIG_AUTOHEADER): $(KCONFIG_CONFIG) $(objutil)/kconfig/conf
 $(KCONFIG_AUTOCONFIG): $(KCONFIG_AUTOHEADER)
 	true
 
-$(KCONFIG_AUTOADS): $(KCONFIG_AUTOCONFIG) $(objutil)/kconfig/toada
+$(KCONFIG_AUTOADS): $(KCONFIG_CONFIG) $(KCONFIG_AUTOHEADER) $(objutil)/kconfig/toada
 	$(objutil)/kconfig/toada CB.Config <$< >$@
 
 $(obj)/%/$(notdir $(KCONFIG_AUTOADS)): $(KCONFIG_AUTOADS)
@@ -253,13 +252,13 @@ includemakefiles= \
 	$(foreach class,classes subdirs $(classes) $(special-classes), $(eval $(class)-y:=)) \
 	$(eval -include $(1)) \
 	$(foreach class,$(classes-y), $(call add-class,$(class))) \
+	$(foreach special,$(special-classes), \
+		$(foreach item,$($(special)-y), $(call $(special)-handler,$(dir $(1)),$(item)))) \
 	$(foreach class,$(classes), \
 		$(eval $(class)-srcs+= \
 			$$(subst $(absobj)/,$(obj)/, \
 			$$(subst $(top)/,, \
 			$$(abspath $$(subst $(dir $(1))/,/,$$(addprefix $(dir $(1)),$$($(class)-y)))))))) \
-	$(foreach special,$(special-classes), \
-		$(foreach item,$($(special)-y), $(call $(special)-handler,$(dir $(1)),$(item)))) \
 	$(eval subdirs+=$$(subst $(CURDIR)/,,$$(wildcard $$(abspath $$(addprefix $(dir $(1)),$$(subdirs-y))))))
 
 # For each path in $(subdirs) call includemakefiles

Makefile.inc

@@ -93,7 +93,7 @@ subdirs-y += $(wildcard src/soc/*/*) $(wildcard src/northbridge/*/*)
 subdirs-y += src/superio
 subdirs-y += $(wildcard src/drivers/*) $(wildcard src/drivers/*/*)
 subdirs-y += src/cpu src/vendorcode
-subdirs-y += util/cbfstool util/sconfig util/nvramtool
+subdirs-y += util/cbfstool util/sconfig util/nvramtool util/pgtblgen
 subdirs-y += util/futility util/marvell util/bincfg
 subdirs-y += $(wildcard src/arch/*)
 subdirs-y += src/mainboard/$(MAINBOARDDIR)
@@ -107,6 +107,10 @@ subdirs-y += util/checklist util/testing
 # Add source classes and their build options
 classes-y := ramstage romstage bootblock decompressor postcar smm smmstub cpu_microcode verstage
 
+# Add a special 'all' class to add sources to all stages
+$(call add-special-class,all)
+all-handler = $(foreach class,bootblock verstage romstage postcar ramstage,$(eval $(class)-y += $(2)))
+
 # Add dynamic classes for rmodules
 $(foreach supported_arch,$(ARCH_SUPPORTED), \
 	    $(eval $(call define_class,rmodules_$(supported_arch),$(supported_arch))))
@@ -193,15 +197,16 @@ ifneq ($(UPDATED_SUBMODULES),1)
 # try to fetch non-optional submodules if the source is under git
 forgetthis:=$(if $(GIT),$(shell git submodule update --init))
 ifeq ($(CONFIG_USE_BLOBS),y)
-# this is necessary because 3rdparty/{blobs,intel-microcode} is update=none, and so is ignored
+# These items are necessary because each has update=none in .gitmodules.  They are ignored
-# unless explicitly requested and enabled through --checkout
+# until expressly requested and enabled with --checkout
 forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/blobs))
 forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/intel-microcode))
 ifeq ($(CONFIG_PLATFORM_USES_FSP1_0)$(CONFIG_PLATFORM_USES_FSP1_1)$(CONFIG_PLATFORM_USES_FSP2_0),y)
-# this is necessary because 3rdparty/fsp is update=none, and so is ignored
-# unless explicitly requested and enabled through --checkout
 forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/fsp))
 endif
+ifeq ($(CONFIG_USE_AMD_BLOBS),y)
+forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/amd_blobs))
+endif
 endif
 UPDATED_SUBMODULES:=1
 COREBOOT_EXPORTS += UPDATED_SUBMODULES
@@ -591,11 +596,12 @@ OVERRIDE_DEVICETREE_FILE := $(src)/mainboard/$(MAINBOARDDIR)/$(CONFIG_OVERRIDE_D
 endif
 
 DEVICETREE_STATIC_C := $(obj)/mainboard/$(MAINBOARDDIR)/static.c
+DEVICETREE_STATIC_H := $(obj)/static.h
 
 $(DEVICETREE_STATIC_C): $(DEVICETREE_FILE) $(OVERRIDE_DEVICETREE_FILE) $(objutil)/sconfig/sconfig
 	@printf "    SCONFIG    $(subst $(src)/,,$(<))\n"
 	mkdir -p $(dir $(DEVICETREE_STATIC_C))
-	$(objutil)/sconfig/sconfig $(DEVICETREE_FILE) $(DEVICETREE_STATIC_C) $(OVERRIDE_DEVICETREE_FILE)
+	$(objutil)/sconfig/sconfig $(DEVICETREE_FILE) $(DEVICETREE_STATIC_C) $(DEVICETREE_STATIC_H) $(OVERRIDE_DEVICETREE_FILE)
 
 ramstage-y+=$(DEVICETREE_STATIC_C)
 romstage-y+=$(DEVICETREE_STATIC_C)
@@ -677,6 +683,18 @@ find-class = $(if $(filter $(1),$(basename $(1))),$(if $(CC_$(1)), $(1), $(call
 # the linker marked it NOBITS automatically because there are only zeroes in it.
 preserve-bss-flags := --set-section-flags .bss=load,alloc,data --set-section-flags .data=load,alloc,data
 
+# For Intel TXT files in the CBFS needs to be marked as 'Initial Boot Block'.
+# As CBFS attributes aren't cheap, only mark them if TXT is enabled.
+ifeq ($(CONFIG_INTEL_TXT),y)
+
+TXTIBB := --ibb
+
+else
+
+TXTIBB :=
+
+endif
+
 ifeq ($(CONFIG_COMPRESS_BOOTBLOCK),y)
 
 $(objcbfs)/bootblock.lz4: $(objcbfs)/bootblock.elf $(objutil)/cbfstool/cbfs-compression-tool
@@ -1030,6 +1048,7 @@ ifeq ($(CONFIG_ARCH_X86),y)
 		-f $(objcbfs)/bootblock.bin \
 		-n bootblock \
 		-t bootblock \
+		$(TXTIBB) \
 		-b -$(call file-size,$(objcbfs)/bootblock.bin) $(cbfs-autogen-attributes) \
 		$(TS_OPTIONS)
 else # ifeq ($(CONFIG_ARCH_X86),y)
@@ -1167,6 +1186,9 @@ endif    # CONFIG_NO_FIXED_XIP_ROM_SIZE
 
 endif   # CONFIG_NO_XIP_EARLY_STAGES
 endif   # CONFIG_ARCH_ROMSTAGE_X86_32 / CONFIG_ARCH_ROMSTAGE_X86_64
+ifeq ($(CONFIG_VBOOT_STARTS_IN_ROMSTAGE),y)
+$(CONFIG_CBFS_PREFIX)/romstage-options += $(TXTIBB)
+endif
 
 cbfs-files-$(CONFIG_HAVE_RAMSTAGE) += $(CONFIG_CBFS_PREFIX)/ramstage
 $(CONFIG_CBFS_PREFIX)/ramstage-file := $(RAMSTAGE)

configs/config.lenovo_t400_vboot_and_debug

@@ -11,3 +11,5 @@ CONFIG_DEBUG_MALLOC=y
 CONFIG_DEBUG_ACPI=y
 CONFIG_DEBUG_BOOT_STATE=y
 CONFIG_DEBUG_ADA_CODE=y
+CONFIG_H8_FN_KEY_AS_VBOOT_RECOVERY_SW=y
+CONFIG_VBOOT=y

payloads/external/GRUB2/Makefile

@@ -1,4 +1,4 @@
-TAG-$(CONFIG_GRUB2_MASTER)=
+TAG-$(CONFIG_GRUB2_MASTER)=origin/HEAD
 TAG-$(CONFIG_GRUB2_REVISION)=$(CONFIG_GRUB2_REVISION_ID)
 TAG-$(CONFIG_GRUB2_STABLE)=grub-2.04
 NAME-$(CONFIG_GRUB2_MASTER)=HEAD
@@ -15,14 +15,14 @@ all: grub2
 
 checkout:
 	echo "    GIT        GRUB2 $(NAME-y)"
-	test -d grub2 || \
+	test -d $(project_dir) || git clone $(project_git_repo) $(project_dir)
-		git clone $(project_git_repo) $(project_dir)
+	git -C $(project_dir) fetch
-	cd grub2 && \
+ifeq ("$(shell git -C $(project_dir) status --ignored=no --untracked-files=no --porcelain)",)
-		git checkout master && \
+	git -C $(project_dir) checkout -f $(TAG-y)
-		git pull; \
+else
-		test -n "$(TAG-y)" && \
+	echo "WARNING: index/tree not clean, skipping update / force checkout."
-			git branch -f $(NAME-y) $(TAG-y) && \
+	echo "         Checkout manually with `git -C $(project_dir) checkout -f`."
-			git checkout $(NAME-y) || true
+endif
 
 grub2/build/config.h: $(CONFIG_DEP) | checkout
 	echo "    CONFIG     GRUB2 $(NAME-y)"

payloads/libpayload/Makefile

@@ -221,12 +221,12 @@ includemakefiles= \
 	$(foreach class,classes subdirs $(classes) $(special-classes), $(eval $(class)-y:=)) \
 	$(eval -include $(1)) \
 	$(foreach class,$(classes-y), $(call add-class,$(class))) \
+	$(foreach special,$(special-classes), \
+		$(foreach item,$($(special)-y), $(call $(special)-handler,$(dir $(1)),$(item)))) \
 	$(foreach class,$(classes), \
 		$(eval $(class)-srcs+= \
 			$$(subst $(top)/,, \
 			$$(abspath $$(addprefix $(dir $(1)),$$($(class)-y)))))) \
-	$(foreach special,$(special-classes), \
-		$(foreach item,$($(special)-y), $(call $(special)-handler,$(dir $(1)),$(item)))) \
 	$(eval subdirs+=$$(subst $(CURDIR)/,,$$(abspath $$(addprefix $(dir $(1)),$$(subdirs-y)))))
 
 # For each path in $(subdirs) call includemakefiles

payloads/libpayload/include/cbfs_core.h

@@ -144,6 +144,7 @@ struct cbfs_file {
 #define CBFS_FILE_ATTR_TAG_UNUSED2 0xffffffff
 #define CBFS_FILE_ATTR_TAG_COMPRESSION 0x42435a4c
 #define CBFS_FILE_ATTR_TAG_HASH 0x68736148
+#define CBFS_FILE_ATTR_TAG_IBB 0x32494242 /* Initial BootBlock */
 
 /* The common fields of extended cbfs file attributes.
    Attributes are expected to start with tag/len, then append their

src/Kconfig

@@ -37,9 +37,26 @@ config CONFIGURABLE_CBFS_PREFIX
 	help
 	  Select this to prompt to use to configure the prefix for cbfs files.
 
+choice
+	prompt "CBFS prefix to use"
+	depends on CONFIGURABLE_CBFS_PREFIX
+	default CBFS_PREFIX_FALLBACK
+
+config CBFS_PREFIX_FALLBACK
+	bool "fallback"
+
+config CBFS_PREFIX_NORMAL
+	bool "normal"
+
+config CBFS_PREFIX_DIY
+	bool "Define your own cbfs prefix"
+
+endchoice
+
 config CBFS_PREFIX
-	string "CBFS prefix to use" if CONFIGURABLE_CBFS_PREFIX
+	string "CBFS prefix to use" if CBFS_PREFIX_DIY
-	default "fallback"
+	default "fallback" if !CONFIGURABLE_CBFS_PREFIX || CBFS_PREFIX_FALLBACK
+	default "normal" if CBFS_PREFIX_NORMAL
 	help
 	  Select the prefix to all files put into the image. It's "fallback"
 	  by default, "normal" is a common alternative.
@@ -218,6 +235,20 @@ config USE_BLOBS
 	  might be required for some chipsets or boards.
 	  This flag ensures that a "Free" option remains available for users.
 
+config USE_AMD_BLOBS
+	bool "Allow AMD blobs repository (with license agreement)"
+	depends on USE_BLOBS
+	help
+	  This draws in the amd_blobs repository, which contains binary files
+	  distributed by AMD, including VBIOS, PSP bootloaders, SMU firmwares,
+	  etc.  Selecting this item to download or clone the repo implies your
+	  agreement to the AMD license agreement.  A copy of the license text
+	  may be reviewed by reading Documentation/soc/amd/amdblobs_license.md,
+	  and your copy of the license is present in the repo once downloaded.
+
+	  Note that for some products, omitting PSP, SMU images, or other items
+	  may result in a nonbooting coreboot.rom.
+
 config COVERAGE
 	bool "Code coverage support"
 	depends on COMPILER_GCC
@@ -1212,11 +1243,6 @@ config HAVE_ROMSTAGE
 	bool
 	default y
 
-config HAVE_POSTCAR
-	bool
-	depends on POSTCAR_STAGE
-	default y
-
 config HAVE_RAMSTAGE
 	bool
 	default n if RAMPAYLOAD

src/arch/arm/Kconfig

@@ -17,6 +17,7 @@ config ARCH_ROMSTAGE_ARM
 config ARCH_RAMSTAGE_ARM
 	bool
 	select ARCH_ARM
+	select RAMSTAGE_CBMEM_TOP_ARG
 
 source src/arch/arm/armv4/Kconfig
 source src/arch/arm/armv7/Kconfig

src/arch/arm/include/arch/stages.h

@@ -14,8 +14,9 @@
 #ifndef __ARCH_STAGES_H
 #define __ARCH_STAGES_H
 
+#include <stdint.h>
 #include <main_decl.h>
 
-void stage_entry(void);
+void stage_entry(uintptr_t stage_arg);
 
 #endif

src/arch/arm/libgcc/udivmoddi4.c

@@ -17,7 +17,7 @@ uint64_t __udivmoddi4(uint64_t num, uint64_t den, uint64_t *rem_p)
 {
 	uint64_t quot = 0, qbit = 1;
 	if (den == 0) {
-		return 1 / ((unsigned)den); /* Intentional divide by zero, without
+		return 1 / ((unsigned int)den); /* Intentional divide by zero, without
 					       triggering a compiler warning which
 					       would abort the build */
 	}

src/arch/arm/stages.c

@@ -22,13 +22,16 @@
  * .text.stage_entry section created by -ffunction-sections).
  */
 
+#include <cbmem.h>
 #include <arch/stages.h>
 #include <arch/cache.h>
 
 /**
  * generic stage entry point. override this if board specific code is needed.
  */
-__weak void stage_entry(void)
+__weak void stage_entry(uintptr_t stage_arg)
 {
+	if (!ENV_ROMSTAGE_OR_BEFORE)
+		_cbmem_top_ptr = stage_arg;
 	main();
 }

src/arch/arm64/Kconfig

@@ -17,6 +17,7 @@ config ARCH_ROMSTAGE_ARM64
 config ARCH_RAMSTAGE_ARM64
 	bool
 	select ARCH_ARM64
+	select RAMSTAGE_CBMEM_TOP_ARG
 
 source src/arch/arm64/armv8/Kconfig
 

src/arch/arm64/boot.c

@@ -11,6 +11,7 @@
  * GNU General Public License for more details.
  */
 
+#include <cbmem.h>
 #include <arch/cache.h>
 #include <arch/lib_helpers.h>
 #include <arch/stages.h>
@@ -48,7 +49,10 @@ void arch_prog_run(struct prog *prog)
 }
 
 /* Generic stage entry point. Can be overridden by board/SoC if needed. */
-__weak void stage_entry(void)
+__weak void stage_entry(uintptr_t stage_arg)
 {
+	if (!ENV_ROMSTAGE_OR_BEFORE)
+		_cbmem_top_ptr = stage_arg;
+
 	main();
 }

src/arch/arm64/include/arch/stages.h

@@ -17,7 +17,7 @@
 #include <stdint.h>
 #include <main_decl.h>
 
-void stage_entry(void);
+void stage_entry(uintptr_t stage_arg);
 
 /* This function is the romstage platform entry point, and should contain all
    chipset and mainboard setup until DRAM is initialized and accessible. */

src/arch/mips/Kconfig

@@ -22,6 +22,7 @@ config ARCH_BOOTBLOCK_MIPS
 	default n
 	select BOOTBLOCK_CUSTOM
 	select C_ENVIRONMENT_BOOTBLOCK
+	select RAMSTAGE_CBMEM_TOP_ARG
 
 config ARCH_VERSTAGE_MIPS
 	bool

src/arch/mips/include/arch/stages.h

@@ -14,8 +14,9 @@
 #ifndef __MIPS_ARCH_STAGES_H
 #define __MIPS_ARCH_STAGES_H
 
+#include <stdint.h>
 #include <main_decl.h>
 
-void stage_entry(void);
+void stage_entry(uintptr_t stage_arg);
 
 #endif /* __MIPS_ARCH_STAGES_H */

src/arch/mips/stages.c

@@ -11,10 +11,13 @@
  * GNU General Public License for more details.
  */
 
+#include <cbmem.h>
 #include <arch/stages.h>
 #include <arch/cache.h>
 
-void stage_entry(void)
+void stage_entry(uintptr_t stage_arg)
 {
+	if (!ENV_ROMSTAGE_OR_BEFORE)
+		_cbmem_top_ptr = stage_arg;
 	main();
 }

src/arch/ppc64/Kconfig

@@ -1,5 +1,6 @@
 config ARCH_PPC64
 	bool
+	select RAMSTAGE_CBMEM_TOP_ARG
 
 config ARCH_BOOTBLOCK_PPC64
 	bool

src/arch/ppc64/include/arch/stages.h

@@ -16,6 +16,6 @@
 
 #include <main_decl.h>
 
-void stage_entry(void) __attribute__((section(".text.stage_entry")));
+void stage_entry(uintptr_t stage_arg) __attribute__((section(".text.stage_entry")));
 
 #endif

src/arch/ppc64/stages.c

@@ -22,9 +22,12 @@
  * linker script.
  */
 
+#include <cbmem.h>
 #include <arch/stages.h>
 
-void stage_entry(void)
+void stage_entry(uintptr_t stage_arg)
 {
+	if (!ENV_ROMSTAGE_OR_BEFORE)
+		_cbmem_top_ptr = stage_arg;
 	main();
 }

src/arch/riscv/fit_payload.c

@@ -18,7 +18,6 @@
 #include <bootmem.h>
 #include <stdlib.h>
 #include <program_loading.h>
-#include <string.h>
 #include <commonlib/compression.h>
 #include <commonlib/cbfs_serialized.h>
 #include <lib.h>

src/arch/x86/Kconfig

@@ -16,6 +16,7 @@ config ARCH_X86
 	default n
 	select PCI
 	select RELOCATABLE_MODULES
+	select RAMSTAGE_CBMEM_TOP_ARG
 
 # stage selectors for x86
 
@@ -65,6 +66,14 @@ config ARCH_RAMSTAGE_X86_64
 	bool
 	default n
 
+config ARCH_X86_64_PGTBL_LOC
+	hex "x86_64 page table location in CBFS"
+	depends on ARCH_BOOTBLOCK_X86_64
+	default 0xfffea000
+	help
+	  The position where to place pagetables. Needs to be known at
+	  compile time. Must not overlap other files in CBFS.
+
 config USE_MARCH_586
 	def_bool n
 	help
@@ -169,15 +178,6 @@ config BOOTBLOCK_NORTHBRIDGE_INIT
 config BOOTBLOCK_RESETS
 	string
 
-config BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP
-	bool
-	default n
-	help
-	  Select this value to provide a routine to save the BIST and timestamp
-	  values.  The default code places the BIST value in MM0 and the
-	  timestamp value in MM2:MM1.  Another file is necessary when the CPU
-	  does not support the MMx register set.
-
 config HAVE_CMOS_DEFAULT
 	def_bool n
 	depends on HAVE_OPTION_TABLE

src/arch/x86/Makefile.inc

@@ -47,12 +47,6 @@ cbfs-files-$(CONFIG_VGA_BIOS_DGPU) += pci$(stripped_vgabios_dgpu_id).rom
 pci$(stripped_vgabios_dgpu_id).rom-file := $(call strip_quotes,$(CONFIG_VGA_BIOS_DGPU_FILE))
 pci$(stripped_vgabios_dgpu_id).rom-type := optionrom
 
-verstage-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c
-bootblock-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c
-romstage-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c
-ramstage-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c
-postcar-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c
-
 ###############################################################################
 # common support for early assembly includes
 ###############################################################################
@@ -94,18 +88,28 @@ $$(objcbfs)/$(1).debug: $$$$($(1)-libs) $$$$($(1)-objs)
 	fi
 endef
 
+###############################################################################
+# all (bootblock,verstage,romstage,postcar,ramstage)
+###############################################################################
+
+ifeq ($(CONFIG_ARCH_X86),y)
+
+all-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c
+all-y += boot.c
+all-y += memcpy.c
+all-y += memset.c
+all-y += cpu_common.c
+
+endif
+
 ###############################################################################
 # bootblock
 ###############################################################################
 
 ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32)$(CONFIG_ARCH_BOOTBLOCK_X86_64),y)
 
-bootblock-y += boot.c
-bootblock-y += cpu_common.c
 bootblock-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c
 bootblock-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S
-bootblock-y += memcpy.c
-bootblock-y += memset.c
 bootblock-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c
 bootblock-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c
 
@@ -183,14 +187,10 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 
 ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y)
 
-verstage-y += boot.c
 verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += gdt_init.S
 verstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c
 verstage-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S
 
-verstage-y += cpu_common.c
-verstage-y += memset.c
-verstage-y += memcpy.c
 verstage-y += memmove.c
 verstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c
 # If verstage is a separate stage it means there's no need
@@ -219,19 +219,15 @@ endif # CONFIG_ARCH_VERSTAGE_X86_32 / CONFIG_ARCH_VERSTAGE_X86_64
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 
 romstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c
-romstage-y += boot.c
 # gdt_init.S is included by entry32.inc when romstage is the first C
 # environment.
 romstage-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += gdt_init.S
 romstage-y += cbmem.c
 romstage-y += cbfs_and_run.c
-romstage-y += cpu_common.c
 romstage-$(CONFIG_EARLY_EBDA_INIT) += ebda.c
 romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c
 romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S
-romstage-y += memcpy.c
 romstage-y += memmove.c
-romstage-y += memset.c
 romstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c
 romstage-y += postcar_loader.c
 romstage-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c
@@ -261,18 +257,13 @@ $(eval $(call create_class_compiler,postcar,x86_32))
 postcar-generic-ccopts += -D__POSTCAR__
 
 postcar-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c
-postcar-y += boot.c
 postcar-y += gdt_init.S
 postcar-y += cbfs_and_run.c
-postcar-y += cbmem.c
-postcar-y += cpu_common.c
 postcar-$(CONFIG_EARLY_EBDA_INIT) += ebda.c
 postcar-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c
 postcar-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S
 postcar-y += exit_car.S
-postcar-y += memcpy.c
 postcar-y += memmove.c
-postcar-y += memset.c
 postcar-y += memlayout.ld
 postcar-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c
 postcar-y += postcar.c
@@ -306,20 +297,15 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi_device.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi_pld.c
 ramstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c
 ramstage-$(CONFIG_ACPI_BERT) += acpi_bert_storage.c
-ramstage-y += boot.c
 ramstage-y += c_start.S
-ramstage-y += cbmem.c
 ramstage-y += cpu.c
-ramstage-y += cpu_common.c
 ramstage-y += ebda.c
 ramstage-y += exception.c
 ramstage-y += idt.S
 ramstage-y += gdt.c
 ramstage-$(CONFIG_IOAPIC) += ioapic.c
-ramstage-y += memcpy.c
 ramstage-y += memlayout.ld
 ramstage-y += memmove.c
-ramstage-y += memset.c
 ramstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c
 ramstage-$(CONFIG_GENERATE_MP_TABLE) += mpspec.c
 ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += pirq_routing.c

src/arch/x86/acpi.c

@@ -37,6 +37,8 @@
 #include <version.h>
 #include <commonlib/sort.h>
 
+static acpi_rsdp_t *valid_rsdp(acpi_rsdp_t *rsdp);
+
 u8 acpi_checksum(u8 *table, u32 length)
 {
 	u8 ret = 0;
@@ -125,7 +127,7 @@ int acpi_create_mcfg_mmconfig(acpi_mcfg_mmconfig_t *mmconfig, u32 base,
 
 int acpi_create_madt_lapic(acpi_madt_lapic_t *lapic, u8 cpu, u8 apic)
 {
-	lapic->type = 0; /* Local APIC structure */
+	lapic->type = LOCAL_APIC; /* Local APIC structure */
 	lapic->length = sizeof(acpi_madt_lapic_t);
 	lapic->flags = (1 << 0); /* Processor/LAPIC enabled */
 	lapic->processor_id = cpu;
@@ -163,7 +165,7 @@ unsigned long acpi_create_madt_lapics(unsigned long current)
 int acpi_create_madt_ioapic(acpi_madt_ioapic_t *ioapic, u8 id, u32 addr,
 				u32 gsi_base)
 {
-	ioapic->type = 1; /* I/O APIC structure */
+	ioapic->type = IO_APIC; /* I/O APIC structure */
 	ioapic->length = sizeof(acpi_madt_ioapic_t);
 	ioapic->reserved = 0x00;
 	ioapic->gsi_base = gsi_base;
@@ -176,7 +178,7 @@ int acpi_create_madt_ioapic(acpi_madt_ioapic_t *ioapic, u8 id, u32 addr,
 int acpi_create_madt_irqoverride(acpi_madt_irqoverride_t *irqoverride,
 		u8 bus, u8 source, u32 gsirq, u16 flags)
 {
-	irqoverride->type = 2; /* Interrupt source override */
+	irqoverride->type = IRQ_SOURCE_OVERRIDE; /* Interrupt source override */
 	irqoverride->length = sizeof(acpi_madt_irqoverride_t);
 	irqoverride->bus = bus;
 	irqoverride->source = source;
@@ -189,7 +191,7 @@ int acpi_create_madt_irqoverride(acpi_madt_irqoverride_t *irqoverride,
 int acpi_create_madt_lapic_nmi(acpi_madt_lapic_nmi_t *lapic_nmi, u8 cpu,
 				u16 flags, u8 lint)
 {
-	lapic_nmi->type = 4; /* Local APIC NMI structure */
+	lapic_nmi->type = LOCAL_APIC_NMI; /* Local APIC NMI structure */
 	lapic_nmi->length = sizeof(acpi_madt_lapic_nmi_t);
 	lapic_nmi->flags = flags;
 	lapic_nmi->processor_id = cpu;
@@ -735,14 +737,14 @@ void acpi_create_hpet(acpi_hpet_t *hpet)
 }
 
 void acpi_create_vfct(struct device *device,
-		      struct acpi_vfct *vfct,
+		      acpi_vfct_t *vfct,
 		      unsigned long (*acpi_fill_vfct)(struct device *device,
-		      struct acpi_vfct *vfct_struct, unsigned long current))
+		      acpi_vfct_t *vfct_struct, unsigned long current))
 {
 	acpi_header_t *header = &(vfct->header);
-	unsigned long current = (unsigned long)vfct + sizeof(struct acpi_vfct);
+	unsigned long current = (unsigned long)vfct + sizeof(acpi_vfct_t);
 
-	memset((void *)vfct, 0, sizeof(struct acpi_vfct));
+	memset((void *)vfct, 0, sizeof(acpi_vfct_t));
 
 	if (!header)
 		return;
@@ -1260,9 +1262,51 @@ unsigned long write_acpi_tables(unsigned long start)
 	/* Align ACPI tables to 16byte */
 	current = acpi_align_current(current);
 
+	/* Special case for qemu */
 	fw = fw_cfg_acpi_tables(current);
-	if (fw)
+	if (fw) {
+		rsdp = NULL;
+		/* Find RSDP. */
+		for (void *p = (void *)current; p < (void *)fw; p += 16) {
+			if (valid_rsdp((acpi_rsdp_t *)p)) {
+				rsdp = p;
+				break;
+			}
+		}
+		if (!rsdp)
+			return fw;
+
+		/* Add BOOT0000 for Linux google firmware driver */
+		printk(BIOS_DEBUG, "ACPI:     * SSDT\n");
+		ssdt = (acpi_header_t *)fw;
+		current = (unsigned long)ssdt + sizeof(acpi_header_t);
+
+		memset((void *)ssdt, 0, sizeof(acpi_header_t));
+
+		memcpy(&ssdt->signature, "SSDT", 4);
+		ssdt->revision = get_acpi_table_revision(SSDT);
+		memcpy(&ssdt->oem_id, OEM_ID, 6);
+		memcpy(&ssdt->oem_table_id, oem_table_id, 8);
+		ssdt->oem_revision = 42;
+		memcpy(&ssdt->asl_compiler_id, ASLC, 4);
+		ssdt->asl_compiler_revision = asl_revision;
+		ssdt->length = sizeof(acpi_header_t);
+
+		acpigen_set_current((char *) current);
+
+		/* Write object to declare coreboot tables */
+		acpi_ssdt_write_cbtable();
+
+		/* (Re)calculate length and checksum. */
+		ssdt->length = current - (unsigned long)ssdt;
+		ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length);
+
+		acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
+
+		acpi_add_table(rsdp, ssdt);
+
 		return fw;
+	}
 
 	dsdt_file = cbfs_boot_map_with_leak(
 				     CONFIG_CBFS_PREFIX "/dsdt.aml",

src/arch/x86/boot.c

@@ -30,13 +30,12 @@ int payload_arch_usable_ram_quirk(uint64_t start, uint64_t size)
 
 void arch_prog_run(struct prog *prog)
 {
-	__asm__ volatile (
 #ifdef __x86_64__
-		"jmp  *%%rdi\n"
+	void (*doit)(void *arg);
 #else
-		"jmp  *%%edi\n"
+	/* Ensure the argument is pushed on the stack. */
+	asmlinkage void (*doit)(void *arg);
 #endif
-
+	doit = prog_entry(prog);
-		:: "D"(prog_entry(prog))
+	doit(prog_entry_arg(prog));
-	);
 }

src/arch/x86/bootblock_crt0.S

@@ -31,6 +31,12 @@
 #include <cpu/x86/16bit/reset16.inc>
 #include <cpu/x86/32bit/entry32.inc>
 
+	/* BIST result in eax */
+	mov	%eax, %ebx
+	/* entry64.inc preserves ebx. */
+#include <cpu/x86/64bit/entry64.inc>
+	mov	%ebx, %eax
+
 #if CONFIG(BOOTBLOCK_DEBUG_SPINLOOP)
 
 	/* Wait for a JTAG debugger to break in and set EBX non-zero */

src/arch/x86/bootblock_simple.c

@@ -27,12 +27,7 @@ static void main(unsigned long bist)
 #endif
 	}
 
-#if CONFIG(VBOOT_SEPARATE_VERSTAGE)
-	const char *target1 = "fallback/verstage";
-#else
 	const char *target1 = "fallback/romstage";
-#endif
-
 	unsigned long entry;
 	entry = findstage(target1);
 	if (entry)

src/arch/x86/c_start.S

@@ -12,6 +12,7 @@
  */
 
 #include <cpu/x86/post_code.h>
+#include <arch/ram_segs.h>
 
 /* Place the stack in the bss section. It's not necessary to define it in the
  * the linker script. */
@@ -42,16 +43,16 @@ _start:
 	cli
 	lgdt	%cs:gdtaddr
 #ifndef __x86_64__
-	ljmp	$0x10, $1f
+	ljmp	$RAM_CODE_SEG, $1f
 #endif
-1:	movl	$0x18, %eax
+1:	movl	$RAM_DATA_SEG, %eax
 	movl	%eax, %ds
 	movl	%eax, %es
 	movl	%eax, %ss
 	movl	%eax, %fs
 	movl	%eax, %gs
 #ifdef __x86_64__
-	mov	$0x48, %ecx
+	mov	$RAM_CODE_SEG64, %ecx
 	call	SetCodeSelector
 #endif
 
@@ -59,6 +60,14 @@ _start:
 
 	cld
 
+#ifdef	__x86_64__
+	mov	%rdi, _cbmem_top_ptr
+#else
+	/* The return argument is at 0(%esp), the calling argument at 4(%esp) */
+	movl	4(%esp), %eax
+	movl	%eax, _cbmem_top_ptr
+#endif
+
 	/** poison the stack. Code should not count on the
 	 * stack being full of zeros. This stack poisoning
 	 * recently uncovered a bug in the broadcast SIPI

src/arch/x86/cbmem.c

@@ -16,21 +16,10 @@
 
 #if CONFIG(CBMEM_TOP_BACKUP)
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
-	static void *cbmem_top_backup;
-	void *top_backup;
-
-	if (ENV_RAMSTAGE && cbmem_top_backup != NULL)
-		return cbmem_top_backup;
-
 	/* Top of CBMEM is at highest usable DRAM address below 4GiB. */
-	top_backup = (void *)restore_top_of_low_cacheable();
+	return (void *)restore_top_of_low_cacheable();
-
-	if (ENV_RAMSTAGE)
-		cbmem_top_backup = top_backup;
-
-	return top_backup;
 }
 
 #endif /* CBMEM_TOP_BACKUP */

src/arch/x86/cpu.c

@@ -315,7 +315,7 @@ void lb_arch_add_records(struct lb_header *header)
 	struct lb_tsc_info *tsc_info;
 
 	/* Don't advertise a TSC rate unless it's constant. */
-	if (!CONFIG(TSC_CONSTANT_RATE))
+	if (!tsc_constant_rate())
 		return;
 
 	freq_khz = tsc_freq_mhz() * 1000;

src/arch/x86/exit_car.S

@@ -31,6 +31,14 @@ _start:
 	/* Migrate GDT to this text segment */
 	call	gdt_init
 
+#ifdef	__x86_64__
+	mov	%rdi, _cbmem_top_ptr
+#else
+	/* The return argument is at 0(%esp), the calling argument at 4(%esp) */
+	movl	4(%esp), %eax
+	movl	%eax, _cbmem_top_ptr
+#endif
+
 	/* chipset_teardown_car() is expected to disable cache-as-ram. */
 	call	chipset_teardown_car
 

src/arch/x86/include/arch/acpi.h

@@ -147,21 +147,21 @@ typedef struct acpi_table_header {
 
 /* RSDT (Root System Description Table) */
 typedef struct acpi_rsdt {
-	struct acpi_table_header header;
+	acpi_header_t header;
 	u32 entry[MAX_ACPI_TABLES];
 } __packed acpi_rsdt_t;
 
 /* XSDT (Extended System Description Table) */
 typedef struct acpi_xsdt {
-	struct acpi_table_header header;
+	acpi_header_t header;
 	u64 entry[MAX_ACPI_TABLES];
 } __packed acpi_xsdt_t;
 
 /* HPET timers */
 typedef struct acpi_hpet {
-	struct acpi_table_header header;
+	acpi_header_t header;
 	u32 id;
-	struct acpi_gen_regaddr addr;
+	acpi_addr_t addr;
 	u8 number;
 	u16 min_tick;
 	u8 attributes;
@@ -169,19 +169,19 @@ typedef struct acpi_hpet {
 
 /* MCFG (PCI Express MMIO config space BAR description table) */
 typedef struct acpi_mcfg {
-	struct acpi_table_header header;
+	acpi_header_t header;
 	u8 reserved[8];
 } __packed acpi_mcfg_t;
 
 typedef struct acpi_tcpa {
-	struct acpi_table_header header;
+	acpi_header_t header;
 	u16 platform_class;
 	u32 laml;
 	u64 lasa;
 } __packed acpi_tcpa_t;
 
 typedef struct acpi_tpm2 {
-	struct acpi_table_header header;
+	acpi_header_t header;
 	u16 platform_class;
 	u8  reserved[2];
 	u64 control_area;
@@ -202,7 +202,7 @@ typedef struct acpi_mcfg_mmconfig {
 
 /* SRAT (System Resource Affinity Table) */
 typedef struct acpi_srat {
-	struct acpi_table_header header;
+	acpi_header_t header;
 	u32 resv;
 	u64 resv1;
 	/* Followed by static resource allocation structure[n] */
@@ -239,19 +239,19 @@ typedef struct acpi_srat_mem {
 
 /* SLIT (System Locality Distance Information Table) */
 typedef struct acpi_slit {
-	struct acpi_table_header header;
+	acpi_header_t header;
 	/* Followed by static resource allocation 8+byte[num*num] */
 } __packed acpi_slit_t;
 
 /* MADT (Multiple APIC Description Table) */
 typedef struct acpi_madt {
-	struct acpi_table_header header;
+	acpi_header_t header;
 	u32 lapic_addr;			/* Local APIC address */
 	u32 flags;			/* Multiple APIC flags */
 } __packed acpi_madt_t;
 
 /* VFCT image header */
-struct acpi_vfct_image_hdr {
+typedef struct acpi_vfct_image_hdr {
 	u32 PCIBus;
 	u32 PCIDevice;
 	u32 PCIFunction;
@@ -262,17 +262,17 @@ struct acpi_vfct_image_hdr {
 	u32 Revision;
 	u32 ImageLength;
 	u8  VbiosContent;	// dummy - copy VBIOS here
-} __packed;
+} __packed acpi_vfct_image_hdr_t;
 
 /* VFCT (VBIOS Fetch Table) */
-struct acpi_vfct {
+typedef struct acpi_vfct {
-	struct acpi_table_header header;
+	acpi_header_t header;
 	u8  TableUUID[16];
 	u32 VBIOSImageOffset;
 	u32 Lib1ImageOffset;
 	u32 Reserved[4];
-	struct acpi_vfct_image_hdr image_hdr;
+	acpi_vfct_image_hdr_t image_hdr;
-} __packed;
+} __packed acpi_vfct_t;
 
 typedef struct acpi_ivrs_info {
 } __packed acpi_ivrs_info_t;
@@ -294,7 +294,7 @@ typedef struct acpi_ivrs_ivhd {
 
 /* IVRS (I/O Virtualization Reporting Structure) Type 10h */
 typedef struct acpi_ivrs {
-	struct acpi_table_header header;
+	acpi_header_t header;
 	uint32_t iv_info;
 	uint32_t reserved[2];
 	struct acpi_ivrs_ivhd ivhd;
@@ -382,7 +382,7 @@ typedef struct dmar_andd_entry {
 
 /* DMAR (DMA Remapping Reporting Structure) */
 typedef struct acpi_dmar {
-	struct acpi_table_header header;
+	acpi_header_t header;
 	u8 host_address_width;
 	u8 flags;
 	u8 reserved[10];
@@ -390,24 +390,23 @@ typedef struct acpi_dmar {
 } __packed acpi_dmar_t;
 
 /* MADT: APIC Structure Types */
-/* TODO: Convert to ALLCAPS. */
 enum acpi_apic_types {
-	LocalApic		= 0,	/* Processor local APIC */
+	LOCAL_APIC,			/* Processor local APIC */
-	IOApic			= 1,	/* I/O APIC */
+	IO_APIC,			/* I/O APIC */
-	IRQSourceOverride	= 2,	/* Interrupt source override */
+	IRQ_SOURCE_OVERRIDE,		/* Interrupt source override */
-	NMIType			= 3,	/* NMI source */
+	NMI_TYPE,			/* NMI source */
-	LocalApicNMI		= 4,	/* Local APIC NMI */
+	LOCAL_APIC_NMI,			/* Local APIC NMI */
-	LApicAddressOverride	= 5,	/* Local APIC address override */
+	LAPIC_ADDRESS_OVERRIDE,		/* Local APIC address override */
-	IOSApic			= 6,	/* I/O SAPIC */
+	IO_SAPIC,			/* I/O SAPIC */
-	LocalSApic		= 7,	/* Local SAPIC */
+	LOCAL_SAPIC,			/* Local SAPIC */
-	PlatformIRQSources	= 8,	/* Platform interrupt sources */
+	PLATFORM_IRQ_SOURCES,		/* Platform interrupt sources */
-	Localx2Apic		= 9,	/* Processor local x2APIC */
+	LOCAL_X2APIC,			/* Processor local x2APIC */
-	Localx2ApicNMI		= 10,	/* Local x2APIC NMI */
+	LOCAL_X2APIC_NMI,		/* Local x2APIC NMI */
-	GICC			= 11,	/* GIC CPU Interface */
+	GICC,				/* GIC CPU Interface */
-	GICD			= 12,	/* GIC Distributor */
+	GICD,				/* GIC Distributor */
-	GIC_MSI_FRAME		= 13,	/* GIC MSI Frame */
+	GIC_MSI_FRAME,			/* GIC MSI Frame */
-	GICR			= 14,	/* GIC Redistributor */
+	GICR,				/* GIC Redistributor */
-	GIC_ITS			= 15,	/* Interrupt Translation Service */
+	GIC_ITS,			/* Interrupt Translation Service */
 	/* 0x10-0x7f: Reserved */
 	/* 0x80-0xff: Reserved for OEM use */
 };
@@ -466,7 +465,7 @@ typedef struct acpi_madt_irqoverride {
 
 /* DBG2: Microsoft Debug Port Table 2 header */
 typedef struct acpi_dbg2_header {
-	struct acpi_table_header header;
+	acpi_header_t header;
 	uint32_t devices_offset;
 	uint32_t devices_count;
 } __attribute__((packed)) acpi_dbg2_header_t;
@@ -489,7 +488,7 @@ typedef struct acpi_dbg2_device {
 
 /* FADT (Fixed ACPI Description Table) */
 typedef struct acpi_fadt {
-	struct acpi_table_header header;
+	acpi_header_t header;
 	u32 firmware_ctrl;
 	u32 dsdt;
 	u8 reserved;	/* Should be 0 */
@@ -528,7 +527,7 @@ typedef struct acpi_fadt {
 	u16 iapc_boot_arch;
 	u8 res2;
 	u32 flags;
-	struct acpi_gen_regaddr reset_reg;
+	acpi_addr_t reset_reg;
 	u8 reset_value;
 	u16 ARM_boot_arch;
 	u8 FADT_MinorVersion;
@@ -536,14 +535,14 @@ typedef struct acpi_fadt {
 	u32 x_firmware_ctl_h;
 	u32 x_dsdt_l;
 	u32 x_dsdt_h;
-	struct acpi_gen_regaddr x_pm1a_evt_blk;
+	acpi_addr_t x_pm1a_evt_blk;
-	struct acpi_gen_regaddr x_pm1b_evt_blk;
+	acpi_addr_t x_pm1b_evt_blk;
-	struct acpi_gen_regaddr x_pm1a_cnt_blk;
+	acpi_addr_t x_pm1a_cnt_blk;
-	struct acpi_gen_regaddr x_pm1b_cnt_blk;
+	acpi_addr_t x_pm1b_cnt_blk;
-	struct acpi_gen_regaddr x_pm2_cnt_blk;
+	acpi_addr_t x_pm2_cnt_blk;
-	struct acpi_gen_regaddr x_pm_tmr_blk;
+	acpi_addr_t x_pm_tmr_blk;
-	struct acpi_gen_regaddr x_gpe0_blk;
+	acpi_addr_t x_gpe0_blk;
-	struct acpi_gen_regaddr x_gpe1_blk;
+	acpi_addr_t x_gpe1_blk;
 } __packed acpi_fadt_t;
 
 /* FADT TABLE Revision values */
@@ -634,9 +633,9 @@ typedef struct acpi_facs {
 
 /* ECDT (Embedded Controller Boot Resources Table) */
 typedef struct acpi_ecdt {
-	struct acpi_table_header header;
+	acpi_header_t header;
-	struct acpi_gen_regaddr ec_control;	/* EC control register */
+	acpi_addr_t ec_control;	/* EC control register */
-	struct acpi_gen_regaddr ec_data;	/* EC data register */
+	acpi_addr_t ec_data;	/* EC data register */
 	u32 uid;				/* UID */
 	u8 gpe_bit;				/* GPE bit */
 	u8 ec_id[];				/* EC ID  */
@@ -644,7 +643,7 @@ typedef struct acpi_ecdt {
 
 /* HEST (Hardware Error Source Table) */
 typedef struct acpi_hest {
-	struct acpi_table_header header;
+	acpi_header_t header;
 	u32 error_source_count;
 	/* error_source_struct(s) */
 } __packed acpi_hest_t;
@@ -677,7 +676,7 @@ typedef struct acpi_hest_hen {
 
 /* BERT (Boot Error Record Table) */
 typedef struct acpi_bert {
-	struct acpi_table_header header;
+	acpi_header_t header;
 	u32 region_length;
 	u64 error_region;
 } __packed acpi_bert_t;
@@ -794,7 +793,7 @@ enum acpi_ipmi_interface_type {
 
 /* ACPI IPMI 2.0 */
 struct acpi_spmi {
-	struct acpi_table_header header;
+	acpi_header_t header;
 	u8 interface_type;
 	u8 reserved;
 	u16 specification_revision;
@@ -864,9 +863,9 @@ void acpi_create_slit(acpi_slit_t *slit,
 		      unsigned long (*acpi_fill_slit)(unsigned long current));
 
 void acpi_create_vfct(struct device *device,
-		      struct acpi_vfct *vfct,
+		      acpi_vfct_t *vfct,
 		      unsigned long (*acpi_fill_vfct)(struct device *device,
-				struct acpi_vfct *vfct_struct,
+				acpi_vfct_t *vfct_struct,
 				unsigned long current));
 
 void acpi_create_ipmi(struct device *device,

src/arch/x86/include/arch/cpu.h

@@ -141,6 +141,11 @@ static inline unsigned int cpuid_edx(unsigned int op)
 	return edx;
 }
 
+static inline unsigned int cpuid_get_max_func(void)
+{
+	return cpuid_eax(0);
+}
+
 #define X86_VENDOR_INVALID    0
 #define X86_VENDOR_INTEL      1
 #define X86_VENDOR_CYRIX      2

src/arch/x86/include/arch/ram_segs.h

@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef RAM_SEGS_H
+#define RAM_SEGS_H
+
+#define RAM_CODE_SEG            0x10
+#define RAM_DATA_SEG            0x18
+#define RAM_CODE16_SEG          0x28
+#define RAM_DATA16_SEG          0x30
+#define RAM_CODE_ACPI_SEG       0x38
+#define RAM_DATA_ACPI_SEG       0x40
+#define RAM_CODE_SEG64          0x48
+
+#endif /* RAM_SEGS_H */

src/arch/x86/postcar_loader.c

@@ -225,5 +225,7 @@ void run_postcar_phase(struct postcar_frame *pcf)
 	/* As postcar exist, it's end of romstage here */
 	timestamp_add_now(TS_END_ROMSTAGE);
 
+	prog_set_arg(&prog, cbmem_top());
+
 	prog_run(&prog);
 }

src/arch/x86/smbios.c

@@ -492,7 +492,7 @@ smbios_board_type __weak smbios_mainboard_board_type(void)
 	return SMBIOS_BOARD_TYPE_UNKNOWN;
 }
 
-u8 __weak smbios_mainboard_enclosure_type(void)
+smbios_enclosure_type __weak smbios_mainboard_enclosure_type(void)
 {
 	return CONFIG_SMBIOS_ENCLOSURE_TYPE;
 }
@@ -522,6 +522,16 @@ void __weak smbios_system_set_uuid(u8 *uuid)
 	/* leave all zero */
 }
 
+unsigned int __weak smbios_cpu_get_max_speed_mhz(void)
+{
+	return 0; /* Unknown */
+}
+
+unsigned int __weak smbios_cpu_get_current_speed_mhz(void)
+{
+	return 0; /* Unknown */
+}
+
 const char *__weak smbios_system_sku(void)
 {
 	return "";
@@ -648,11 +658,20 @@ static int smbios_write_type4(unsigned long *current, int handle)
 	t->processor_family = (res.eax > 0) ? 0x0c : 0x6;
 	t->processor_type = 3; /* System Processor */
 	t->core_count = (res.ebx >> 16) & 0xff;
+	/* Assume we enable all the cores always, capped only by MAX_CPUS */
+	t->core_enabled = MAX(t->core_count, CONFIG_MAX_CPUS);
 	t->l1_cache_handle = 0xffff;
 	t->l2_cache_handle = 0xffff;
 	t->l3_cache_handle = 0xffff;
 	t->processor_upgrade = get_socket_type();
 	len = t->length + smbios_string_table_len(t->eos);
+	if (cpu_have_cpuid() && cpuid_get_max_func() >= 0x16) {
+		t->max_speed = cpuid_ebx(0x16);
+		t->current_speed = cpuid_eax(0x16); /* base frequency */
+	} else {
+		t->max_speed = smbios_cpu_get_max_speed_mhz();
+		t->current_speed = smbios_cpu_get_current_speed_mhz();
+	}
 	*current += len;
 	return len;
 }

src/arch/x86/timestamp.c

@@ -22,7 +22,7 @@ uint64_t timestamp_get(void)
 int timestamp_tick_freq_mhz(void)
 {
 	/* Chipsets that have a constant TSC provide this value correctly. */
-	if (CONFIG(TSC_CONSTANT_RATE))
+	if (tsc_constant_rate())
 		return tsc_freq_mhz();
 
 	/* Filling tick_freq_mhz = 0 in timestamps-table will trigger

src/commonlib/include/commonlib/cbfs_serialized.h

@@ -157,6 +157,7 @@ struct cbfs_file_attribute {
 #define CBFS_FILE_ATTR_TAG_HASH 0x68736148
 #define CBFS_FILE_ATTR_TAG_POSITION 0x42435350  /* PSCB */
 #define CBFS_FILE_ATTR_TAG_ALIGNMENT 0x42434c41 /* ALCB */
+#define CBFS_FILE_ATTR_TAG_IBB 0x32494242 /* Initial BootBlock */
 
 struct cbfs_file_attr_compression {
 	uint32_t tag;

src/commonlib/include/commonlib/cbmem_id.h

@@ -56,6 +56,8 @@
 #define CBMEM_ID_ROMSTAGE_RAM_STACK 0x90357ac4
 #define CBMEM_ID_ROOT		0xff4007ff
 #define CBMEM_ID_SMBIOS         0x534d4254
+#define CBMEM_ID_BERT_RAW_DATA	0x42455254
+#define CBMEM_ID_SMM_TSEG_SPACE	0x54534547
 #define CBMEM_ID_SMM_SAVE_SPACE	0x07e9acee
 #define CBMEM_ID_STAGEx_META	0x57a9e000
 #define CBMEM_ID_STAGEx_CACHE	0x57a9e100
@@ -119,6 +121,8 @@
 	{ CBMEM_ID_ROMSTAGE_RAM_STACK,	"ROMSTG STCK" }, \
 	{ CBMEM_ID_ROOT,		"CBMEM ROOT " }, \
 	{ CBMEM_ID_SMBIOS,		"SMBIOS     " }, \
+	{ CBMEM_ID_BERT_RAW_DATA,	"BERT DATA  " }, \
+	{ CBMEM_ID_SMM_TSEG_SPACE,	"TSEG       " }, \
 	{ CBMEM_ID_SMM_SAVE_SPACE,	"SMM BACKUP " }, \
 	{ CBMEM_ID_STORAGE_DATA,	"SD/MMC/eMMC" }, \
 	{ CBMEM_ID_TCPA_LOG,		"TCPA LOG   " }, \

src/commonlib/include/commonlib/helpers.h

@@ -137,4 +137,8 @@
 #define __unused __attribute__((unused))
 #endif
 
+#ifndef alloca
+#define alloca(x) __builtin_alloca(x)
+#endif
+
 #endif /* COMMONLIB_HELPERS_H */