intel cache-as-ram: Move DCACHE_RAM_BASE

Having same memory region set as both WRPROT and WRBACK
using MTRRs is undefined behaviour. This could happen if
we allow DCACHE_RAM_BASE to be located within CBFS in SPI
flash memory and XIP romstage is at the same location.

As SPI master by default decodes all of top 16MiB below
4GiB, initial cache-as-ram line fills may have actually
read from SPI flash even in the case DCACHE_RAM_BASE was
below the nominal 4GiB - ROM_SIZE.

There are no reasons to have this as board-specific setting.

Change-Id: I2cce80731ede2e7f78197d9b0c77c7e9957a81b5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17806
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/cpu/intel/ep80579/Kconfig

@@ -14,7 +14,7 @@ if CPU_INTEL_EP80579
 
 config DCACHE_RAM_BASE
 	hex
-	default 0xffaf8000
+	default 0xfefc0000
 
 config DCACHE_RAM_SIZE
 	hex

src/cpu/intel/socket_441/Kconfig

@@ -11,7 +11,7 @@ config SOCKET_SPECIFIC_OPTIONS # dummy
 
 config DCACHE_RAM_BASE
 	hex
-	default 0xffaf8000
+	default 0xfefc0000
 
 config DCACHE_RAM_SIZE
 	hex

src/cpu/intel/socket_BGA956/Kconfig

@@ -8,7 +8,7 @@ if CPU_INTEL_SOCKET_BGA956
 
 config DCACHE_RAM_BASE
 	hex
-	default 0xffaf8000
+	default 0xfefc0000
 
 config DCACHE_RAM_SIZE
 	hex

src/cpu/intel/socket_FCBGA559/Kconfig

@@ -11,7 +11,7 @@ config SOCKET_SPECIFIC_OPTIONS
 
 config DCACHE_RAM_BASE
 	hex
-	default 0xffafc000
+	default 0xfefc0000
 
 config DCACHE_RAM_SIZE
 	hex

src/cpu/intel/socket_LGA771/Kconfig

@@ -4,3 +4,15 @@ config CPU_INTEL_SOCKET_LGA771
 	select SSE2
 	select MMX
 	select AP_IN_SIPI_WAIT
+
+if CPU_INTEL_SOCKET_LGA771
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xfefc0000
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x8000
+
+endif

src/cpu/intel/socket_mFCPGA478/Kconfig

@@ -12,7 +12,7 @@ config SOCKET_SPECIFIC_OPTIONS # dummy
 
 config DCACHE_RAM_BASE
 	hex
-	default 0xffaf8000
+	default 0xfefc0000
 
 config DCACHE_RAM_SIZE
 	hex

src/cpu/intel/socket_mPGA478MN/Kconfig

@@ -9,7 +9,7 @@ if CPU_INTEL_SOCKET_MPGA478MN
 
 config DCACHE_RAM_BASE
 	hex
-	default 0xffaf8000
+	default 0xfefc0000
 
 config DCACHE_RAM_SIZE
 	hex

src/cpu/intel/socket_mPGA604/Kconfig

@@ -22,7 +22,7 @@ config SSE2
 
 config DCACHE_RAM_BASE
 	hex
-	default 0x0ffafc000
+	default 0xfefc0000
 
 config DCACHE_RAM_SIZE
 	hex