mb/cwwk: Add CWWK CW-ADL-4L-V1.0 board
This board is the CWWK variant based upon Alder Lake with 4 2.5 GbE ports, similar boards are available in other port configurations. As a low cost, relatively high performance board with 4 NICs, it is well suited for networking or 'homelab' tasks. CPU: Intel N100 or N350 Memory: DDR5-4800 SODIMM (max 16 GB) NIC: 4x Intel I226-V 2.5 GbE Expansion: - M.2 2230 E key - M.2 2280 M key - USB 2.0 header - Fan header External ports: - DC power - 4x Ethernet - Display Port - HDMI - 4x USB 2.0 - Micro SD Working: - Boots Debian 12 with SeaBIOS and EDK II payloads - Serial port - External USB ports - DisplayPort / HDMI - 4x Intel I226 2.5 GbE NICs - M.2 ports - Micro SD slot - ACPI S3 Not working / not tested: - Fan (ITE IT8613E) - Audio - S0ix - Internal USB ports VBT extracted from vendor UEFI firmware version ADLN 0.01 x64 (04/04/2023 11:42:38). Change-Id: Ice9174d95c10afc6a22ddd15fb3be4fa38d329be Signed-off-by: Brandon Weeks <me@brandonweeks.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Brandon Weeks
Felix Held
parent
57e36a3320
commit
c8b379bb79
17
src/mainboard/cwwk/Kconfig
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17
src/mainboard/cwwk/Kconfig
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@ -0,0 +1,17 @@
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## SPDX-License-Identifier: GPL-2.0-or-later
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if VENDOR_CWWK
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choice
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prompt "Mainboard model"
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source "src/mainboard/cwwk/*/Kconfig.name"
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endchoice
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source "src/mainboard/cwwk/*/Kconfig"
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config MAINBOARD_VENDOR
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default "CWWK"
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endif # VENDOR_CWWK
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4
src/mainboard/cwwk/Kconfig.name
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4
src/mainboard/cwwk/Kconfig.name
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@ -0,0 +1,4 @@
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## SPDX-License-Identifier: GPL-2.0-or-later
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config VENDOR_CWWK
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bool "CWWK"
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27
src/mainboard/cwwk/adl/Kconfig
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27
src/mainboard/cwwk/adl/Kconfig
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@ -0,0 +1,27 @@
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## SPDX-License-Identifier: GPL-2.0-or-later
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if BOARD_CWWK_ADL_N
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_16384
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select DRIVERS_UART_8250IO
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select INTEL_GMA_HAVE_VBT
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select SOC_INTEL_ALDERLAKE_PCH_N
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select SUPERIO_ITE_IT8613E
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config MAINBOARD_DIR
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default "cwwk/adl"
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config MAINBOARD_PART_NUMBER
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default "CW-AL-4L-V1.0"
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config DIMM_MAX
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default 2
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config NO_POST
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default y
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endif
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4
src/mainboard/cwwk/adl/Kconfig.name
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4
src/mainboard/cwwk/adl/Kconfig.name
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@ -0,0 +1,4 @@
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## SPDX-License-Identifier: GPL-2.0-or-later
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config BOARD_CWWK_ADL_N
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bool "CW-ADL-4L-V1.0"
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7
src/mainboard/cwwk/adl/Makefile.mk
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7
src/mainboard/cwwk/adl/Makefile.mk
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@ -0,0 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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bootblock-y += bootblock.c
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romstage-y += romstage_fsp_params.c
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ramstage-y += mainboard.c
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6
src/mainboard/cwwk/adl/board_info.txt
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6
src/mainboard/cwwk/adl/board_info.txt
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@ -0,0 +1,6 @@
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Vendor name: CWWK
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Board name: CW-ADL-4L-V1.0
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Category: eval
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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12
src/mainboard/cwwk/adl/bootblock.c
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12
src/mainboard/cwwk/adl/bootblock.c
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@ -0,0 +1,12 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <bootblock_common.h>
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#include <superio/ite/common/ite.h>
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#include <superio/ite/it8613e/it8613e.h>
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#define UART_DEV PNP_DEV(0x2e, IT8613E_SP1)
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void bootblock_mainboard_early_init(void)
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{
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ite_enable_serial(UART_DEV, CONFIG_TTYS0_BASE);
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}
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BIN
src/mainboard/cwwk/adl/data.vbt
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BIN
src/mainboard/cwwk/adl/data.vbt
Normal file
Binary file not shown.
80
src/mainboard/cwwk/adl/devicetree.cb
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80
src/mainboard/cwwk/adl/devicetree.cb
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@ -0,0 +1,80 @@
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chip soc/intel/alderlake
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register "s0ix_enable" = "1"
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register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)"
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register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)"
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register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)"
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register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)"
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register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # microSD card reader
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register "pch_pcie_rp[PCH_RP(1)]" = "{
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.clk_src = 0,
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.clk_req = 0,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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register "pch_pcie_rp[PCH_RP(7)]" = "{
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.clk_src = 1,
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.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN,
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.pcie_rp_aspm = ASPM_DISABLE,
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}"
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register "pch_pcie_rp[PCH_RP(9)]" = "{
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.clk_src = 2,
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.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN,
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.pcie_rp_aspm = ASPM_DISABLE,
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}"
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register "pch_pcie_rp[PCH_RP(10)]" = "{
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.clk_src = 3,
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.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN,
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.pcie_rp_aspm = ASPM_DISABLE,
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}"
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register "pch_pcie_rp[PCH_RP(11)]" = "{
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.clk_src = 4,
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.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN,
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.pcie_rp_aspm = ASPM_DISABLE,
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}"
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register "pch_pcie_rp[PCH_RP(12)]" = "{
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.clk_src = 5,
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.clk_req = 5,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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# Enable EDP in PortA
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register "ddi_portA_config" = "1"
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device domain 0 on
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device ref igpu on end
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device ref dtt on end
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device ref crashlog off end
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device ref xhci on end
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device ref shared_sram on end
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device ref pcie_rp1 on end
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device ref pcie_rp7 on end
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device ref pcie_rp9 on end
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device ref pcie_rp10 on end
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device ref pcie_rp11 on end
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device ref pcie_rp12 on end # M.2 E key port
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device ref pch_espi on
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chip superio/ite/it8613e
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device pnp 2e.0 off end
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device pnp 2e.1 on # COM 1
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io 0x60 = 0x3f8
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irq 0x70 = 0x4
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irq 0xf0 = 0x1
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end
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device pnp 2e.4 off end # Environment Controller
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device pnp 2e.5 off end # Keyboard
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device pnp 2e.6 off end # Mouse
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device pnp 2e.7 off end # GPIO
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device pnp 2e.a off end # CIR
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end
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end
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device ref hda on end
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device ref smbus on end
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end
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end
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25
src/mainboard/cwwk/adl/dsdt.asl
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25
src/mainboard/cwwk/adl/dsdt.asl
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@ -0,0 +1,25 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <acpi/acpi.h>
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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ACPI_DSDT_REV_2,
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x20110725
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)
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{
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#include <acpi/dsdt_top.asl>
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#include <soc/intel/common/block/acpi/acpi/platform.asl>
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#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
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#include <cpu/intel/common/acpi/cpu.asl>
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Device (\_SB.PCI0) {
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#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
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#include <soc/intel/alderlake/acpi/southbridge.asl>
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}
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#include <southbridge/intel/common/acpi/sleepstates.asl>
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}
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297
src/mainboard/cwwk/adl/gpio.h
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297
src/mainboard/cwwk/adl/gpio.h
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@ -0,0 +1,297 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef CFG_GPIO_H
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#define CFG_GPIO_H
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#include <soc/gpio.h>
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/* Pad configuration was generated automatically using intelp2m utility */
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static const struct pad_config gpio_table[] = {
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/* ------- GPIO Community 0 ------- */
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/* ------- GPIO Group GPP_B ------- */
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PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* CORE_VID0 */
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PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* CORE_VID1 */
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PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), /* VRALERT# */
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PAD_NC(GPP_B3, NONE), /* GPIO */
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PAD_NC(GPP_B4, NONE), /* GPIO */
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PAD_NC(GPP_B5, NONE), /* GPIO */
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PAD_NC(GPP_B6, NONE), /* GPIO */
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PAD_NC(GPP_B7, NONE), /* GPIO */
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PAD_NC(GPP_B8, NONE), /* GPIO */
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PAD_NC(GPP_B9, NONE), /* GPIO */
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PAD_NC(GPP_B10, NONE), /* GPIO */
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//PAD_CFG_NF(GPP_B11, NONE, RSMRST, NF1), /* PMCALERT# */
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PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* SLP_S0# */
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PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PLTRST# */
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PAD_CFG_GPO(GPP_B14, 0, PLTRST), /* GPIO */
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PAD_NC(GPP_B15, NONE), /* GPIO */
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PAD_NC(GPP_B16, NONE), /* GPIO */
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PAD_NC(GPP_B17, NONE), /* GPIO */
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PAD_CFG_GPO(GPP_B18, 0, PLTRST), /* GPIO */
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PAD_NC(GPP_B19, NONE), /* GPIO */
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PAD_NC(GPP_B20, NONE), /* GPIO */
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PAD_NC(GPP_B21, NONE), /* GPIO */
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PAD_NC(GPP_B22, NONE), /* GPIO */
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PAD_CFG_GPO(GPP_B23, 1, PLTRST), /* GPIO */
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PAD_CFG_NF(GPP_B24, NONE, DEEP, NF1), /* GSPI0_CLK_LOOPBK */
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PAD_CFG_NF(GPP_B25, NONE, DEEP, NF1), /* GSPI1_CLK_LOOPBK */
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/* ------- GPIO Group GPP_T ------- */
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PAD_NC(GPP_T0, NONE), /* GPIO */
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PAD_NC(GPP_T1, NONE), /* GPIO */
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PAD_CFG_NF(GPP_T2, DN_20K, DEEP, NF2), /* FUSA_DIAGTEST_EN */
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PAD_CFG_NF(GPP_T3, DN_20K, DEEP, NF2), /* FUSA_DIAGTEST_MODE */
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PAD_NC(GPP_T4, NONE), /* GPIO */
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PAD_NC(GPP_T5, NONE), /* GPIO */
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PAD_NC(GPP_T6, NONE), /* GPIO */
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PAD_NC(GPP_T7, NONE), /* GPIO */
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PAD_NC(GPP_T8, NONE), /* GPIO */
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PAD_NC(GPP_T9, NONE), /* GPIO */
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PAD_NC(GPP_T10, NONE), /* GPIO */
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PAD_NC(GPP_T11, NONE), /* GPIO */
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PAD_NC(GPP_T12, NONE), /* GPIO */
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PAD_NC(GPP_T13, NONE), /* GPIO */
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PAD_NC(GPP_T14, NONE), /* GPIO */
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PAD_NC(GPP_T15, NONE), /* GPIO */
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/* ------- GPIO Group GPP_A ------- */
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PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), /* ESPI_IO0 */
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PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), /* ESPI_IO1 */
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PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), /* ESPI_IO2 */
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PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), /* ESPI_IO3 */
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PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), /* ESPI_CS0# */
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PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), /* ESPI_ALERT0# */
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PAD_CFG_NF(GPP_A6, UP_20K, DEEP, NF1), /* ESPI_ALERT1# */
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PAD_CFG_GPO(GPP_A7, 1, PLTRST), /* GPIO */
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PAD_NC(GPP_A8, NONE), /* GPIO */
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PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), /* ESPI_CLK */
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PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), /* ESPI_RESET# */
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PAD_NC(GPP_A11, NONE), /* GPIO */
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PAD_NC(GPP_A12, NONE), /* GPIO */
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PAD_CFG_GPO(GPP_A13, 1, DEEP), /* GPIO */
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PAD_NC(GPP_A14, NONE), /* GPIO */
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PAD_NC(GPP_A15, NONE), /* GPIO */
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PAD_NC(GPP_A16, NONE), /* GPIO */
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PAD_CFG_GPO(GPP_A17, 1, PLTRST), /* GPIO */
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PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* DDSP_HPDB */
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PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* DDSP_HPD1 */
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PAD_NC(GPP_A20, NONE), /* GPIO */
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PAD_CFG_GPO(GPP_A21, 1, PLTRST), /* GPIO */
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PAD_NC(GPP_A22, NONE), /* GPIO */
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PAD_CFG_NF(GPP_A23, UP_20K, DEEP, NF1), /* ESPI_CS1# */
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PAD_CFG_NF(GPP_ESPI_CLK_LOOPBK, NONE, DEEP, NF1), /* GPP_ESPI_CLK_LOOPBK */
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/* ------- GPIO Community 1 ------- */
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/* ------- GPIO Group GPP_S ------- */
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PAD_NC(GPP_S0, NONE), /* GPIO */
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PAD_NC(GPP_S1, NONE), /* GPIO */
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PAD_NC(GPP_S2, NONE), /* GPIO */
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PAD_NC(GPP_S3, NONE), /* GPIO */
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PAD_NC(GPP_S4, NONE), /* GPIO */
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PAD_NC(GPP_S5, NONE), /* GPIO */
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PAD_NC(GPP_S6, NONE), /* GPIO */
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PAD_NC(GPP_S7, NONE), /* GPIO */
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/* ------- GPIO Group GPP_I ------- */
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PAD_NC(GPP_I0, NONE), /* GPIO */
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PAD_NC(GPP_I1, NONE), /* GPIO */
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PAD_NC(GPP_I2, NONE), /* GPIO */
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PAD_NC(GPP_I3, NONE), /* GPIO */
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PAD_NC(GPP_I4, NONE), /* GPIO */
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PAD_NC(GPP_I5, NONE), /* GPIO */
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PAD_NC(GPP_I6, NONE), /* GPIO */
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PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), /* EMMC_CMD */
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PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), /* EMMC_DATA0 */
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PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), /* EMMC_DATA1 */
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PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), /* EMMC_DATA2 */
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PAD_CFG_NF(GPP_I11, NONE, DEEP, NF1), /* EMMC_DATA3 */
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PAD_CFG_NF(GPP_I12, NONE, DEEP, NF1), /* EMMC_DATA4 */
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PAD_CFG_NF(GPP_I13, NONE, DEEP, NF1), /* EMMC_DATA5 */
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PAD_CFG_NF(GPP_I14, NONE, DEEP, NF1), /* EMMC_DATA6 */
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PAD_CFG_NF(GPP_I15, NONE, DEEP, NF1), /* EMMC_DATA7 */
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PAD_CFG_NF(GPP_I16, NONE, DEEP, NF1), /* EMMC_RCLK */
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PAD_CFG_NF(GPP_I17, NONE, DEEP, NF1), /* EMMC_CLK */
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PAD_CFG_NF(GPP_I18, NONE, DEEP, NF1), /* EMMC_RESET# */
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PAD_NC(GPP_I19, NONE), /* GPIO */
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/* ------- GPIO Group GPP_H ------- */
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PAD_CFG_GPO(GPP_H0, 1, PLTRST), /* GPIO */
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PAD_CFG_GPO(GPP_H1, 0, DEEP), /* GPIO */
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PAD_CFG_GPO(GPP_H2, 1, RSMRST), /* GPIO */
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PAD_NC(GPP_H3, NONE), /* GPIO */
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PAD_NC(GPP_H4, NONE), /* GPIO */
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PAD_NC(GPP_H5, NONE), /* GPIO */
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PAD_NC(GPP_H6, NONE), /* GPIO */
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PAD_NC(GPP_H7, NONE), /* GPIO */
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PAD_NC(GPP_H8, NONE), /* GPIO */
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PAD_NC(GPP_H9, NONE), /* GPIO */
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PAD_NC(GPP_H10, NONE), /* GPIO */
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PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* UART0_TXD */
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PAD_NC(GPP_H12, NONE), /* GPIO */
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PAD_NC(GPP_H13, NONE), /* GPIO */
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PAD_NC(GPP_H14, NONE), /* GPIO */
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PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), /* DDPB_CTRLCLK */
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PAD_NC(GPP_H16, NONE), /* GPIO */
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PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), /* DDPB_CTRLDATA */
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PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), /* PROC_C10_GATE# */
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PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), /* SRCCLKREQ4# */
|
||||
PAD_NC(GPP_H20, NONE), /* GPIO */
|
||||
PAD_NC(GPP_H21, NONE), /* GPIO */
|
||||
PAD_NC(GPP_H22, NONE), /* GPIO */
|
||||
PAD_NC(GPP_H23, NONE), /* GPIO */
|
||||
|
||||
/* ------- GPIO Group GPP_D ------- */
|
||||
PAD_NC(GPP_D0, NONE), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_D1, NONE, PLTRST, OFF, ACPI), /* GPIO */
|
||||
PAD_NC(GPP_D2, NONE), /* GPIO */
|
||||
PAD_NC(GPP_D3, NONE), /* GPIO */
|
||||
PAD_NC(GPP_D4, NONE), /* GPIO */
|
||||
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* SRCCLKREQ0# */
|
||||
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* SRCCLKREQ1# */
|
||||
PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* SRCCLKREQ2# */
|
||||
PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), /* SRCCLKREQ3# */
|
||||
PAD_CFG_NF(GPP_D9, NATIVE, DEEP, NF5), /* BSSB_LS2_RX */
|
||||
PAD_CFG_NF(GPP_D10, NATIVE, DEEP, NF5), /* BSSB_LS2_TX */
|
||||
PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF5), /* BSSB_LS3_RX */
|
||||
PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF5), /* BSSB_LS3_TX */
|
||||
PAD_NC(GPP_D13, NONE), /* GPIO */
|
||||
PAD_NC(GPP_D14, NONE), /* GPIO */
|
||||
PAD_NC(GPP_D15, NONE), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_D16, 1, PLTRST), /* GPIO */
|
||||
PAD_NC(GPP_D17, NONE), /* GPIO */
|
||||
PAD_NC(GPP_D18, NONE), /* GPIO */
|
||||
PAD_NC(GPP_D19, NONE), /* GPIO */
|
||||
PAD_CFG_NF(GPP_GSPI2_CLK_LOOPBK, NONE, DEEP, NF1), /* GPP_GSPI2_CLK_LOOPBK */
|
||||
|
||||
/* ------- GPIO Group vGPIO ------- */
|
||||
|
||||
/* ------- GPIO Community 2 ------- */
|
||||
|
||||
/* ------- GPIO Group GPP_GPD ------- */
|
||||
PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), /* BATLOW# */
|
||||
PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), /* ACPRESENT */
|
||||
PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), /* LAN_WAKE# */
|
||||
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), /* PWRBTN# */
|
||||
PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* SLP_S3# */
|
||||
PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* SLP_S4# */
|
||||
PAD_CFG_NF(GPD6, NONE, PWROK, NF1), /* SLP_A# */
|
||||
PAD_CFG_GPO(GPD7, 0, PWROK), /* GPIO */
|
||||
PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* SUSCLK */
|
||||
PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* SLP_WLAN# */
|
||||
PAD_CFG_NF(GPD10, NONE, PWROK, NF1), /* SLP_S5# */
|
||||
PAD_CFG_GPO(GPD11, 0, PWROK), /* GPIO */
|
||||
PAD_CFG_NF(GPD_INPUT3VSEL, NONE, PWROK, NF1), /* GPD_INPUT3VSEL */
|
||||
PAD_CFG_NF(GPD_SLP_LANB, NONE, PWROK, NF1), /* GPD_SLP_LANB */
|
||||
PAD_CFG_NF(GPD_SLP_SUSB, NONE, PWROK, NF1), /* GPD_SLP_SUSB */
|
||||
PAD_CFG_NF(GPD_WAKEB, NONE, PWROK, NF1), /* GPD_WAKEB */
|
||||
PAD_CFG_NF(GPD_DRAM_RESETB, NONE, PWROK, NF1), /* GPD_DRAM_RESETB */
|
||||
|
||||
/* ------- GPIO Group PCIe vGPIO ------- */
|
||||
|
||||
/* ------- GPIO Community 4 ------- */
|
||||
|
||||
/* ------- GPIO Group GPP_C ------- */
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMBCLK */
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBDATA */
|
||||
PAD_CFG_GPO(GPP_C2, 0, DEEP), /* GPIO */
|
||||
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0CLK */
|
||||
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0DATA */
|
||||
PAD_CFG_GPO(GPP_C5, 0, DEEP), /* GPIO */
|
||||
PAD_CFG_NF(GPP_C6, NONE, RSMRST, NF1), /* SML1CLK */
|
||||
PAD_CFG_NF(GPP_C7, NONE, RSMRST, NF1), /* SML1DATA */
|
||||
PAD_NC(GPP_C8, NONE), /* GPIO */
|
||||
PAD_NC(GPP_C9, NONE), /* GPIO */
|
||||
PAD_NC(GPP_C10, NONE), /* GPIO */
|
||||
PAD_NC(GPP_C11, NONE), /* GPIO */
|
||||
PAD_NC(GPP_C12, NONE), /* GPIO */
|
||||
PAD_NC(GPP_C13, NONE), /* GPIO */
|
||||
PAD_NC(GPP_C14, NONE), /* GPIO */
|
||||
PAD_NC(GPP_C15, NONE), /* GPIO */
|
||||
PAD_NC(GPP_C16, NONE), /* GPIO */
|
||||
PAD_NC(GPP_C17, NONE), /* GPIO */
|
||||
PAD_NC(GPP_C18, NONE), /* GPIO */
|
||||
PAD_NC(GPP_C19, NONE), /* GPIO */
|
||||
PAD_NC(GPP_C20, NONE), /* GPIO */
|
||||
PAD_NC(GPP_C21, NONE), /* GPIO */
|
||||
PAD_NC(GPP_C22, NONE), /* GPIO */
|
||||
PAD_NC(GPP_C23, NONE), /* GPIO */
|
||||
|
||||
/* ------- GPIO Group GPP_F ------- */
|
||||
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* CNV_BRI_DT */
|
||||
PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), /* CNV_BRI_RSP */
|
||||
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), /* CNV_RGI_DT */
|
||||
PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), /* CNV_RGI_RSP */
|
||||
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* CNV_RF_RESET# */
|
||||
PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), /* MODEM_CLKREQ */
|
||||
PAD_NC(GPP_F6, NONE), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_F7, 0, DEEP), /* GPIO */
|
||||
PAD_NC(GPP_F8, NONE), /* GPIO */
|
||||
PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* BOOTMPC */
|
||||
PAD_CFG_GPO(GPP_F10, 1, PLTRST), /* GPIO */
|
||||
PAD_NC(GPP_F11, NONE), /* GPIO */
|
||||
PAD_NC(GPP_F12, NONE), /* GPIO */
|
||||
PAD_NC(GPP_F13, NONE), /* GPIO */
|
||||
PAD_NC(GPP_F14, NONE), /* GPIO */
|
||||
PAD_NC(GPP_F15, NONE), /* GPIO */
|
||||
PAD_NC(GPP_F16, NONE), /* GPIO */
|
||||
PAD_NC(GPP_F17, NONE), /* GPIO */
|
||||
PAD_NC(GPP_F18, NONE), /* GPIO */
|
||||
PAD_NC(GPP_F19, NONE), /* GPIO */
|
||||
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), /* Reserved */
|
||||
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* Reserved */
|
||||
PAD_NC(GPP_F22, NONE), /* GPIO */
|
||||
PAD_NC(GPP_F23, NONE), /* GPIO */
|
||||
PAD_NC(GPP_F_CLK_LOOPBK, NONE), /* GPIO */
|
||||
|
||||
/* ------- GPIO Group GPP_HVCMOS ------- */
|
||||
PAD_CFG_NF(GPP_L_BKLTEN, NONE, DEEP, NF1), /* n/a */
|
||||
PAD_CFG_NF(GPP_L_BKLTCTL, NONE, DEEP, NF1), /* n/a */
|
||||
PAD_CFG_NF(GPP_L_VDDEN, NONE, DEEP, NF1), /* n/a */
|
||||
PAD_CFG_NF(GPP_SYS_PWROK, NONE, DEEP, NF1), /* n/a */
|
||||
PAD_CFG_NF(GPP_SYS_RESETB, NONE, DEEP, NF1), /* n/a */
|
||||
PAD_CFG_NF(GPP_MLK_RSTB, NONE, DEEP, NF1), /* n/a */
|
||||
|
||||
/* ------- GPIO Group GPP_E ------- */
|
||||
PAD_NC(GPP_E0, NONE), /* GPIO */
|
||||
PAD_NC(GPP_E1, NONE), /* GPIO */
|
||||
PAD_NC(GPP_E2, NONE), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_E3, 1, DEEP), /* GPIO */
|
||||
PAD_NC(GPP_E4, NONE), /* GPIO */
|
||||
PAD_NC(GPP_E5, NONE), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_E6, 0, DEEP), /* GPIO */
|
||||
PAD_NC(GPP_E7, NONE), /* GPIO */
|
||||
PAD_NC(GPP_E8, NONE), /* GPIO */
|
||||
PAD_NC(GPP_E9, NONE), /* GPIO */
|
||||
PAD_NC(GPP_E10, NONE), /* GPIO */
|
||||
PAD_NC(GPP_E11, NONE), /* GPIO */
|
||||
PAD_NC(GPP_E12, NONE), /* GPIO */
|
||||
PAD_NC(GPP_E13, NONE), /* GPIO */
|
||||
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDSP_HPDA */
|
||||
PAD_CFG_GPO(GPP_E15, 1, PLTRST), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_E16, 0, PLTRST), /* GPIO */
|
||||
PAD_NC(GPP_E17, NONE), /* GPIO */
|
||||
PAD_CFG_NF(GPP_E18, NATIVE, DEEP, NF5), /* BSSB_LS0_RX */
|
||||
PAD_CFG_NF(GPP_E19, NATIVE, DEEP, NF5), /* BSSB_LS0_TX */
|
||||
PAD_CFG_GPO(GPP_E20, 1, PLTRST), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_E21, 0, PLTRST), /* GPIO */
|
||||
PAD_CFG_NF(GPP_E22, DN_20K, DEEP, NF1), /* DDPA_CTRLCLK */
|
||||
PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), /* DDPA_CTRLDATA */
|
||||
PAD_NC(GPP_E_CLK_LOOPBK, NONE), /* GPIO */
|
||||
|
||||
/* ------- GPIO Community 5 ------- */
|
||||
|
||||
/* ------- GPIO Group GPP_R ------- */
|
||||
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), /* HDA_BCLK */
|
||||
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), /* HDA_SYNC */
|
||||
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), /* HDA_SDO */
|
||||
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), /* HDA_SDI0 */
|
||||
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), /* HDA_RST# */
|
||||
PAD_NC(GPP_R5, NONE), /* GPIO */
|
||||
PAD_NC(GPP_R6, NONE), /* GPIO */
|
||||
PAD_NC(GPP_R7, NONE), /* GPIO */
|
||||
};
|
||||
|
||||
#endif /* CFG_GPIO_H */
|
||||
13
src/mainboard/cwwk/adl/mainboard.c
Normal file
13
src/mainboard/cwwk/adl/mainboard.c
Normal file
@ -0,0 +1,13 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <soc/ramstage.h>
|
||||
#include "gpio.h"
|
||||
|
||||
static void mainboard_init(void *chip_info)
|
||||
{
|
||||
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.init = mainboard_init,
|
||||
};
|
||||
28
src/mainboard/cwwk/adl/romstage_fsp_params.c
Normal file
28
src/mainboard/cwwk/adl/romstage_fsp_params.c
Normal file
@ -0,0 +1,28 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <fsp/api.h>
|
||||
#include <soc/meminit.h>
|
||||
#include <soc/romstage.h>
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *memupd)
|
||||
{
|
||||
static const struct mb_cfg ddr5_mem_config = {
|
||||
.type = MEM_TYPE_DDR5,
|
||||
|
||||
.ect = true, /* Early Command Training */
|
||||
|
||||
.UserBd = BOARD_TYPE_MOBILE,
|
||||
|
||||
.LpDdrDqDqsReTraining = 1,
|
||||
};
|
||||
|
||||
const struct mem_spd dimm_module_spd_info = {
|
||||
.topo = MEM_TOPO_DIMM_MODULE,
|
||||
.smbus = {
|
||||
[0] = { .addr_dimm[0] = 0x50, },
|
||||
},
|
||||
};
|
||||
|
||||
const bool half_populated = false;
|
||||
memcfg_init(memupd, &ddr5_mem_config, &dimm_module_spd_info, half_populated);
|
||||
}
|
||||
Loading…
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Reference in New Issue
Block a user