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cml-u: Sync devicetree changes from lemp9

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Change-Id: I69855d082708b185815343b2d92807f3028b2478
This commit is contained in:
Jeremy Soller
2020-09-21 19:57:44 -06:00
parent e13bade2dd
commit c97a435978
1 changed files with 5 additions and 15 deletions
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18
src/mainboard/system76/cml-u/devicetree.cb
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@@ -1,7 +1,7 @@
chip soc/intel/cannonlake
# Lock Down
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
/* Touchpad */
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 80,
@@ -13,7 +13,7 @@ chip soc/intel/cannonlake
register "SendVrMbxCmd" = "2"
# ACPI (soc/intel/cannonlake/acpi.c)
# Enable s0ix
# Disable s0ix
register "s0ix_enable" = "0"
# PM Timer Enabled
@@ -42,18 +42,8 @@ chip soc/intel/cannonlake
# FSP Silicon (soc/intel/cannonlake/fsp_params.c)
# Serial I/O
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
[PchSerialIoIndexSPI0] = PchSerialIoDisabled,
[PchSerialIoIndexSPI1] = PchSerialIoDisabled,
[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
[PchSerialIoIndexUART0] = PchSerialIoDisabled,
[PchSerialIoIndexUART1] = PchSerialIoDisabled,
[PchSerialIoIndexUART2] = PchSerialIoPci,
[PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad
[PchSerialIoIndexUART2] = PchSerialIoSkipInit, // LPSS UART
}"
# SATA