Fix freeze during chipset lockdown on Nehalem
Remove locking of PCI device 00:00.0 registers (nehalem/finalize.c)
and remove setting the zeroth bit of the MSR_LT_LOCK_MEMORY = 0x2e7 MSR
register (model_2065x/finalize.c) to fix a frozen boot and S3 resume issue
which became apparent with commit d533b16669
.
More detailed, either setting the LSB of the 32 bit register at 0x98
of the PCI device 00:00.0 (in the intel_nehalem_finalize_smm function) or
setting the LSB of the the MSR register MSR_LT_LOCK_MEMORY = 0x2e7 (in the
intel_model_2065x_finalize_smm function) indepentenly causes a freeze
during bootup or a complete session loss on resuming from S3 as described
here: https://mail.coreboot.org/pipermail/coreboot/2018-April/086564.html
It seems like Nehalem CPUs do not have a MSR_LT_LOCK_MEMORY register.
Additionally, the "Intel Core i7-600, i5-500, i5-400 and i3-300 Mobile
Processor Series, Datasheet Volume Two" indicates that registers of the
PCI device 00:00.0 cannot be locked manually. Instead, they can only be
locked by TXT, VT-d, CMD.LOCK.MEMCONFIG, ME_SM_LOCK or D_LCK.
Finally, the addresses and sizes of these registers were partially wrong.
Tested on Lenovo X201i with a Core i3 330M (no AES-NI, no VT-d and no TXT
support compared to the Core i5 and Core i7 processors of a X201).
Change-Id: I9d568d5c05807ebf7e131b3e5be8e5445476d61b
Signed-off-by: Matthias Gazzari <mail@qtux.eu>
Reviewed-on: https://review.coreboot.org/25914
Reviewed-by: Nicola Corna <nicola@corna.info>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
committed by
Nico Huber
parent
15f232df08
commit
cc1e3b64ed
@@ -54,7 +54,4 @@ void intel_model_2065x_finalize_smm(void)
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/* Lock TM interupts - route thermal events to all processors */
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msr_set_bit(MSR_MISC_PWR_MGMT, 22);
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/* Lock memory configuration to protect SMM */
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msr_set_bit(MSR_LT_LOCK_MEMORY, 0);
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}
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@@ -39,7 +39,6 @@
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#define ENERGY_POLICY_NORMAL 6
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#define ENERGY_POLICY_POWERSAVE 15
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#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2
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#define MSR_LT_LOCK_MEMORY 0x2e7
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#define IA32_MC0_STATUS 0x401
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#define MSR_PIC_MSG_CONTROL 0x2e
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@@ -23,18 +23,6 @@
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void intel_nehalem_finalize_smm(void)
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{
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pci_or_config16(PCI_DEV_SNB, 0x50, 1 << 0); /* GGC */
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pci_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0); /* DPR */
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pci_or_config32(PCI_DEV_SNB, 0x78, 1 << 10); /* ME */
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pci_or_config32(PCI_DEV_SNB, 0x90, 1 << 0); /* REMAPBASE */
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pci_or_config32(PCI_DEV_SNB, 0x98, 1 << 0); /* REMAPLIMIT */
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pci_or_config32(PCI_DEV_SNB, 0xa0, 1 << 0); /* TOM */
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pci_or_config32(PCI_DEV_SNB, 0xa8, 1 << 0); /* TOUUD */
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pci_or_config32(PCI_DEV_SNB, 0xb0, 1 << 0); /* BDSM */
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pci_or_config32(PCI_DEV_SNB, 0xb4, 1 << 0); /* BGSM */
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pci_or_config32(PCI_DEV_SNB, 0xb8, 1 << 0); /* TSEGMB */
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pci_or_config32(PCI_DEV_SNB, 0xbc, 1 << 0); /* TOLUD */
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MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */
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MCHBAR32_OR(0x5f00, 1 << 31); /* SA PM */
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MCHBAR32_OR(0x6020, 1 << 0); /* UMA GFX */
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