Add tigerlake mainboards
Change-Id: Id239f4bb28a3c755a6ff64d66ec046b0da6c27ef
This commit is contained in:
Jeremy Soller
Jeremy Soller
parent
3be97acaef
commit
cc355edf58
76
src/mainboard/system76/darp7/Kconfig
Normal file
76
src/mainboard/system76/darp7/Kconfig
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@ -0,0 +1,76 @@
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if BOARD_SYSTEM76_DARP7
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_16384
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select DRIVERS_I2C_HID
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select DRIVERS_INTEL_PMC
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select DRIVERS_INTEL_USB4_RETIMER
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select EC_SYSTEM76_EC
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select EC_SYSTEM76_EC_BAT_THRESHOLDS
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select EC_SYSTEM76_EC_COLOR_KEYBOARD
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select HAVE_ACPI_TABLES
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select HAVE_CMOS_DEFAULT
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select HAVE_OPTION_TABLE
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select HAVE_SMI_HANDLER
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select INTEL_GMA_HAVE_VBT
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select INTEL_LPSS_UART_FOR_CONSOLE
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select MAINBOARD_HAS_LPC_TPM
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select MAINBOARD_HAS_TPM2
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select NO_UART_ON_SUPERIO
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select PCIEXP_HOTPLUG
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select SOC_INTEL_TIGERLAKE
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select SOC_INTEL_COMMON_BLOCK_HDA
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select SOC_INTEL_COMMON_BLOCK_HDA_VERB
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select SPD_READ_BY_WORD
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select SYSTEM_TYPE_LAPTOP
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select TPM_RDRESP_NEED_DELAY
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select USE_OPTION_TABLE
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config MAINBOARD_DIR
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string
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default "system76/darp7"
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config MAINBOARD_PART_NUMBER
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string
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default "darp7"
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config MAINBOARD_SMBIOS_PRODUCT_NAME
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string
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default "Darter Pro"
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config MAINBOARD_VERSION
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string
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default "darp7"
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#TODO: subsystem IDs
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config CBFS_SIZE
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hex
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default 0xA00000
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config CONSOLE_POST
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bool
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default y
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config DIMM_MAX
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int
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default 4 # Hack to make soc code work
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config DIMM_SPD_SIZE
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int
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default 512
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config MAX_CPUS
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int
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default 8
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config POST_DEVICE
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bool
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default n
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config UART_FOR_CONSOLE
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int
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default 2
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endif
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2
src/mainboard/system76/darp7/Kconfig.name
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2
src/mainboard/system76/darp7/Kconfig.name
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@ -0,0 +1,2 @@
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config BOARD_SYSTEM76_DARP7
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bool "darp7"
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3
src/mainboard/system76/darp7/Makefile.inc
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3
src/mainboard/system76/darp7/Makefile.inc
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@ -0,0 +1,3 @@
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bootblock-y += bootblock.c
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ramstage-y += ramstage.c
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ramstage-y += hda_verb.c
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30
src/mainboard/system76/darp7/acpi/backlight.asl
Normal file
30
src/mainboard/system76/darp7/acpi/backlight.asl
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@ -0,0 +1,30 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <drivers/intel/gma/acpi/gma.asl>
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Scope (GFX0) {
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Name (BRIG, Package (22) {
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40, /* default AC */
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40, /* default Battery */
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5,
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10,
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15,
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20,
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25,
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30,
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35,
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40,
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45,
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50,
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55,
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60,
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65,
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70,
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75,
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80,
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85,
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90,
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95,
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100
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})
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}
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12
src/mainboard/system76/darp7/acpi/mainboard.asl
Normal file
12
src/mainboard/system76/darp7/acpi/mainboard.asl
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@ -0,0 +1,12 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#define EC_GPE_SCI 0x6E
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#define EC_GPE_SWI 0x6E
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#include <ec/system76/ec/acpi/ec.asl>
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Scope (\_SB) {
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#include "sleep.asl"
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Scope (PCI0) {
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#include "backlight.asl"
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}
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}
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46
src/mainboard/system76/darp7/acpi/sleep.asl
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46
src/mainboard/system76/darp7/acpi/sleep.asl
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@ -0,0 +1,46 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <intelblocks/gpio.h>
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Method (PGPM, 1, Serialized)
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{
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For (Local0 = 0, Local0 < 6, Local0++)
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{
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\_SB.PCI0.CGPM (Local0, Arg0)
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}
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}
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/*
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* Method called from _PTS prior to system sleep state entry
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* Enables dynamic clock gating for all 5 GPIO communities
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*/
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Method (MPTS, 1, Serialized)
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{
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\_SB.PCI0.LPCB.EC0.PTS (Arg0)
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PGPM (MISCCFG_ENABLE_GPIO_PM_CONFIG)
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}
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/*
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* Method called from _WAK prior to system sleep state wakeup
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* Disables dynamic clock gating for all 5 GPIO communities
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*/
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Method (MWAK, 1, Serialized)
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{
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PGPM (0)
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\_SB.PCI0.LPCB.EC0.WAK (Arg0)
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}
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/*
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* S0ix Entry/Exit Notifications
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* Called from \_SB.PEPD._DSM
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*/
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Method (MS0X, 1, Serialized)
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{
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If (Arg0 == 1) {
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/* S0ix Entry */
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PGPM (MISCCFG_ENABLE_GPIO_PM_CONFIG)
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} Else {
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/* S0ix Exit */
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PGPM (0)
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}
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}
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8
src/mainboard/system76/darp7/board_info.txt
Normal file
8
src/mainboard/system76/darp7/board_info.txt
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@ -0,0 +1,8 @@
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Vendor name: System76
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Board name: darp7
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Category: laptop
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Release year: 2021
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ROM package: SOIC-8
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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9
src/mainboard/system76/darp7/bootblock.c
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9
src/mainboard/system76/darp7/bootblock.c
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@ -0,0 +1,9 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootblock_common.h>
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#include <gpio.h>
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#include "gpio.h"
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void bootblock_mainboard_init(void) {
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gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
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}
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2
src/mainboard/system76/darp7/cmos.default
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2
src/mainboard/system76/darp7/cmos.default
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boot_option=Fallback
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preserve_smmstore=0
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35
src/mainboard/system76/darp7/cmos.layout
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35
src/mainboard/system76/darp7/cmos.layout
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@ -0,0 +1,35 @@
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# SPDX-License-Identifier: GPL-2.0-only
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entries
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0 384 r 0 reserved_memory
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# RTC_BOOT_BYTE (coreboot hardcoded)
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384 1 e 2 boot_option
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388 4 h 0 reboot_counter
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#395 4 e 3 debug_level
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408 1 h 1 preserve_smmstore
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984 16 h 0 check_sum
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enumerations
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1 0 Disable
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1 1 Enable
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2 0 Fallback
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2 1 Normal
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3 0 Emergency
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3 1 Alert
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3 2 Critical
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3 3 Error
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3 4 Warning
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3 5 Notice
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3 6 Info
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3 7 Debug
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3 8 Spew
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checksums
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checksum 392 983 984
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362
src/mainboard/system76/darp7/devicetree.cb
Normal file
362
src/mainboard/system76/darp7/devicetree.cb
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@ -0,0 +1,362 @@
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chip soc/intel/tigerlake
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register "common_soc_config" = "{
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.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
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// Touchpad I2C bus
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.i2c[0] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 80,
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.fall_time_ns = 110,
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},
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}"
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# ACPI (soc/intel/tigerlake/acpi.c)
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# Disable DPTF
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register "dptf_enable" = "0"
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# Enable Enhanced Intel SpeedStep
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register "eist_enable" = "1"
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# Enable s0ix, required for TGL-U
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register "s0ix_enable" = "1"
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# CPU (soc/intel/tigerlake/cpu.c)
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# Power limits
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register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{
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// /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw
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.tdp_pl1_override = 28,
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// /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw
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.tdp_pl2_override = 51,
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}"
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register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{
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// /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw
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.tdp_pl1_override = 28,
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// /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw
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.tdp_pl2_override = 51,
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}"
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# Finalize (soc/intel/tigerlake/finalize.c)
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# PM Timer Disabled, saves power
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register "PmTimerDisabled" = "1"
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# FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c)
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# Enable C6 DRAM
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register "enable_c6dram" = "1"
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# System Agent dynamic frequency support
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register "SaGv" = "SaGv_Enabled"
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# FSP Silicon (soc/intel/tigerlake/fsp_params.c)
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# Acoustic settings
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register "AcousticNoiseMitigation" = "1"
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register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
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register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
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register "SlowSlewRate[VR_DOMAIN_SA]" = "SLEW_FAST_8"
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register "SlowSlewRate[VR_DOMAIN_VLCC]" = "SLEW_FAST_8"
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register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1"
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register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1"
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register "FastPkgCRampDisable[VR_DOMAIN_SA]" = "1"
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register "FastPkgCRampDisable[VR_DOMAIN_VLCC]" = "1"
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# FIVR configuration
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# Read EXT_RAIL_CONFIG to determine bitmaps
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# sudo devmem2 0xfe0011b8
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# 0x0
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# Read EXT_V1P05_VR_CONFIG
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# sudo devmem2 0xfe0011c0
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# 0x1a42000
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# Read EXT_VNN_VR_CONFIG0
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# sudo devmem2 0xfe0011c4
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# 0x1a42000
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# TODO: v1p05 voltage and vnn icc max?
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register "ext_fivr_settings" = "{
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.configure_ext_fivr = 1,
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.v1p05_enable_bitmap = 0,
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.vnn_enable_bitmap = 0,
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.v1p05_supported_voltage_bitmap = 0,
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.vnn_supported_voltage_bitmap = 0,
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.v1p05_icc_max_ma = 500,
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.vnn_sx_voltage_mv = 1050,
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}"
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# Read LPM_EN, make sure to invert the bits
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# sudo devmem2 0xfe001c78
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# 0x9
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register "LpmStateDisableMask" = "
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LPM_S0i2_1 |
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LPM_S0i2_2 |
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LPM_S0i3_1 |
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LPM_S0i3_2 |
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LPM_S0i3_3 |
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LPM_S0i3_4
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"
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# Thermal
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# rdmsr --bitfield 31:24 --decimal 0x1A2
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register "tcc_offset" = "12"
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# PM Util (soc/intel/tigerlake/pmutil.c)
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# GPE configuration
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# sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
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# 0x432
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register "pmc_gpe0_dw0" = "PMC_GPP_A"
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register "pmc_gpe0_dw1" = "PMC_GPP_R"
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register "pmc_gpe0_dw2" = "PMC_GPD"
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# Actual device tree
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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#From CPU EDS(575683)
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device ref system_agent on end
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device ref igpu on
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# DDIA is eDP
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register "DdiPortAConfig" = "1"
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register "DdiPortAHpd" = "1"
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register "DdiPortADdc" = "0"
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# DDIB is HDMI
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register "DdiPortBConfig" = "0"
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register "DdiPortBHpd" = "1"
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register "DdiPortBDdc" = "1"
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register "gfx" = "GMA_STATIC_DISPLAYS(0)"
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end
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device ref dptf on
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register "Device4Enable" = "1"
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end
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device ref peg on
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# PCIe PEG0 x4, Clock 0 (SSD1)
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register "PcieClkSrcUsage[0]" = "0x40"
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register "PcieClkSrcClkReq[0]" = "0"
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#TODO: causes failure on resume
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# chip soc/intel/common/block/pcie/rtd3
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# register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B16)" # SSD1_PWR_EN
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# register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D13)" # GPP_D13_SSD1_PLT_RST#
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# #TODO: Support disable/enable CPU RP clock
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# register "srcclk_pin" = "-1" # SSD1_CLKREQ#
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# device generic 0 on end
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# end
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#TODO: Hybrid storage mode?
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register "HybridStorageMode" = "0"
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end
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device ref tbt_pcie_rp0 on end # J_TYPEC2
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device ref gna on end
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device ref north_xhci on # J_TYPEC2
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register "TcssXhciEn" = "1"
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chip drivers/usb/acpi
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device ref tcss_root_hub on
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chip drivers/usb/acpi
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register "desc" = ""USB3 J_TYPEC2""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "group" = "ACPI_PLD_GROUP(1, 3)"
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device ref tcss_usb3_port1 on end
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end
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end
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end
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end
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device ref tbt_dma0 on # J_TYPEC2
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chip drivers/intel/usb4/retimer
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register "power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A23)"
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device generic 0 on end
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end
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end
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# From PCH EDS(576591)
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device ref cnvi_bt on end
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device ref south_xhci on
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# USB2
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register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # UJ_USB1
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register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1
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register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # J_USB3_1
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register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
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register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC2
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register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Camera
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register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
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# USB3
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1 CH0
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB3_1
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1 CH1
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# ACPI
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chip drivers/usb/acpi
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device ref xhci_root_hub on
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chip drivers/usb/acpi
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register "desc" = ""USB2 UJ_USB1""
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register "type" = "UPC_TYPE_A"
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device ref usb2_port1 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 J_TYPEC1""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "group" = "ACPI_PLD_GROUP(1, 2)"
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device ref usb2_port2 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 J_USB3_1""
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register "type" = "UPC_TYPE_A"
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register "group" = "ACPI_PLD_GROUP(1, 1)"
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device ref usb2_port3 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Fingerprint""
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register "type" = "UPC_TYPE_INTERNAL"
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device ref usb2_port5 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 J_TYPEC2""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "group" = "ACPI_PLD_GROUP(1, 3)"
|
||||
device ref usb2_port6 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Camera""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device ref usb2_port7 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Bluetooth""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device ref usb2_port10 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 J_TYPEC1 CH0""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "group" = "ACPI_PLD_GROUP(1, 2)"
|
||||
device ref usb3_port2 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 J_USB3_1""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "group" = "ACPI_PLD_GROUP(1, 1)"
|
||||
device ref usb3_port3 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 J_TYPEC1 CH1""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
#TODO register "group" = "ACPI_PLD_GROUP(1, 2)"
|
||||
device ref usb3_port4 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref shared_ram on end
|
||||
device ref cnvi_wifi on
|
||||
chip drivers/wifi/generic
|
||||
register "wake" = "GPE0_PME_B0"
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref i2c0 on
|
||||
# Touchpad I2C bus
|
||||
register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""PNP0C50""
|
||||
register "generic.desc" = ""FocalTech Touchpad""
|
||||
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B3)"
|
||||
register "generic.probed" = "1"
|
||||
register "hid_desc_reg_offset" = "0x01"
|
||||
device i2c 38 on end
|
||||
end
|
||||
end
|
||||
device ref i2c1 on
|
||||
#TODO: USB-PD?
|
||||
register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
|
||||
end
|
||||
device ref heci1 on
|
||||
#TODO Disable ME and HECI
|
||||
register "HeciEnabled" = "1"
|
||||
end
|
||||
device ref uart2 on
|
||||
# Debug console
|
||||
register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit"
|
||||
end
|
||||
device ref sata on
|
||||
# SATA1 (SSD0)
|
||||
register "SataPortsEnable[1]" = "1"
|
||||
register "SataPortsDevSlp[1]" = "1"
|
||||
register "SataPortsEnableDitoConfig[1]" = "1"
|
||||
register "SataSalpSupport" = "1"
|
||||
end
|
||||
device ref pcie_rp6 on
|
||||
# PCIe root port #6 x1, Clock 2 (CARD)
|
||||
register "PcieRpEnable[5]" = "1"
|
||||
register "PcieRpLtrEnable[5]" = "1"
|
||||
register "PcieClkSrcUsage[2]" = "5"
|
||||
register "PcieClkSrcClkReq[2]" = "2"
|
||||
end
|
||||
device ref pcie_rp7 on
|
||||
# PCIe root port #7 x1, Clock 3 (GLAN)
|
||||
register "PcieRpEnable[6]" = "1"
|
||||
register "PcieRpLtrEnable[6]" = "1"
|
||||
register "PcieClkSrcUsage[3]" = "6"
|
||||
register "PcieClkSrcClkReq[3]" = "3"
|
||||
chip soc/intel/common/block/pcie/rtd3
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # GPIO_LAN_EN
|
||||
#TODO: should this be GPIO_LANRTD3 or LAN_PLT_RST# ?
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F7)" # GPIO_LANRTD3
|
||||
register "srcclk_pin" = "3" # GLAN_CLKREQ#
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref pcie_rp8 on
|
||||
# PCIe root port #8 x1, Clock 1 (WLAN)
|
||||
register "PcieRpEnable[7]" = "1"
|
||||
register "PcieRpLtrEnable[7]" = "1"
|
||||
register "PcieClkSrcUsage[1]" = "7"
|
||||
register "PcieClkSrcClkReq[1]" = "1"
|
||||
end
|
||||
device ref pcie_rp9 on
|
||||
# PCIe root port #9 x4, Clock 4 (SSD0)
|
||||
register "PcieRpEnable[8]" = "1"
|
||||
register "PcieRpLtrEnable[8]" = "1"
|
||||
register "PcieClkSrcUsage[4]" = "8"
|
||||
register "PcieClkSrcClkReq[4]" = "4"
|
||||
chip soc/intel/common/block/pcie/rtd3
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD_PWR_EN
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" # GPP_H0_RTD3
|
||||
register "srcclk_pin" = "4"
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref pch_espi on
|
||||
# LPC configuration from lspci -s 1f.0 -xxx
|
||||
# Address 0x84: Decode 0x80 - 0x8F (Port 80)
|
||||
register "gen1_dec" = "0x000c0081"
|
||||
# Address 0x88: Decode 0x68 - 0x6F (PMC)
|
||||
register "gen2_dec" = "0x00040069"
|
||||
# Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command)
|
||||
register "gen3_dec" = "0x00fc0E01"
|
||||
# Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug)
|
||||
register "gen4_dec" = "0x00fc0F01"
|
||||
# LPC TPM
|
||||
chip drivers/pc80/tpm
|
||||
device pnp 0c31.0 on end
|
||||
end
|
||||
end
|
||||
device ref p2sb on end
|
||||
device ref pmc hidden
|
||||
# The pmc_mux chip driver is a placeholder for the
|
||||
# PMC.MUX device in the ACPI hierarchy.
|
||||
chip drivers/intel/pmc_mux
|
||||
device generic 0 on
|
||||
chip drivers/intel/pmc_mux/conn
|
||||
# J_TYPEC2
|
||||
register "usb2_port_number" = "6"
|
||||
register "usb3_port_number" = "1"
|
||||
# SBU & HSL follow CC
|
||||
device generic 0 alias conn0 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref hda on
|
||||
register "PchHdaAudioLinkHdaEnable" = "1"
|
||||
end
|
||||
device ref smbus on
|
||||
register "SmbusEnable" = "1"
|
||||
end
|
||||
device ref fast_spi on end
|
||||
end
|
||||
end
|
||||
41
src/mainboard/system76/darp7/dsdt.asl
Normal file
41
src/mainboard/system76/darp7/dsdt.asl
Normal file
@ -0,0 +1,41 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
//TODO: cleaner solution for ACPI brightness
|
||||
#define SYSTEM76_ACPI_NO_GFX0
|
||||
|
||||
#include <acpi/acpi.h>
|
||||
|
||||
DefinitionBlock(
|
||||
"dsdt.aml",
|
||||
"DSDT",
|
||||
ACPI_DSDT_REV_2,
|
||||
OEM_ID,
|
||||
ACPI_TABLE_CREATOR,
|
||||
0x20110725 // OEM revision
|
||||
)
|
||||
{
|
||||
#include <soc/intel/common/block/acpi/acpi/platform.asl>
|
||||
|
||||
// global NVS and variables
|
||||
#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
|
||||
|
||||
// CPU
|
||||
#include <cpu/intel/common/acpi/cpu.asl>
|
||||
|
||||
Scope (\_SB) {
|
||||
Device (PCI0)
|
||||
{
|
||||
#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
|
||||
#include <soc/intel/tigerlake/acpi/southbridge.asl>
|
||||
#include <soc/intel/tigerlake/acpi/tcss.asl>
|
||||
}
|
||||
}
|
||||
|
||||
Scope (\_SB.PCI0.LPCB) {
|
||||
#include <drivers/pc80/pc/ps2_controller.asl>
|
||||
}
|
||||
|
||||
#include <southbridge/intel/common/acpi/sleepstates.asl>
|
||||
|
||||
#include "acpi/mainboard.asl"
|
||||
}
|
||||
226
src/mainboard/system76/darp7/gpio.h
Normal file
226
src/mainboard/system76/darp7/gpio.h
Normal file
@ -0,0 +1,226 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#ifndef __ACPI__
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
/* Pad configuration in romstage. */
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
// UART2_RXD
|
||||
PAD_CFG_NF(GPP_C20, UP_20K, DEEP, NF1),
|
||||
// UART2_TXD
|
||||
PAD_CFG_NF(GPP_C21, UP_20K, DEEP, NF1),
|
||||
};
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
|
||||
PAD_CFG_GPI(GPD2, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPD7, 1, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
|
||||
PAD_CFG_TERM_GPO(GPD9, 0, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD10, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD11, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_A7, NONE),
|
||||
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_A9, NONE, DEEP, NF3),
|
||||
PAD_NC(GPP_A10, NONE),
|
||||
PAD_NC(GPP_A11, NONE),
|
||||
PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_A13, 1, NONE, PLTRST),
|
||||
PAD_NC(GPP_A14, NONE),
|
||||
PAD_NC(GPP_A15, NONE),
|
||||
PAD_NC(GPP_A16, NONE),
|
||||
PAD_NC(GPP_A17, NONE),
|
||||
PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_A19, NONE),
|
||||
PAD_NC(GPP_A20, NONE),
|
||||
PAD_NC(GPP_A21, NONE),
|
||||
PAD_NC(GPP_A22, NONE),
|
||||
PAD_CFG_TERM_GPO(GPP_A23, 0, NONE, PLTRST),
|
||||
PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_B2, UP_20K, DEEP),
|
||||
// GPP_B3 - touchpad interrupt
|
||||
PAD_CFG_GPI_INT(GPP_B3, NONE, PLTRST, LEVEL),
|
||||
PAD_NC(GPP_B4, NONE),
|
||||
PAD_NC(GPP_B5, NONE),
|
||||
PAD_NC(GPP_B6, NONE),
|
||||
PAD_NC(GPP_B7, NONE),
|
||||
PAD_CFG_TERM_GPO(GPP_B8, 1, NONE, DEEP),
|
||||
PAD_NC(GPP_B9, NONE),
|
||||
PAD_NC(GPP_B10, NONE),
|
||||
PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_B14, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_B15, 1, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_B16, 0x44000301, 0x0000),
|
||||
PAD_NC(GPP_B17, NONE),
|
||||
PAD_NC(GPP_B18, NONE),
|
||||
PAD_NC(GPP_B19, NONE),
|
||||
PAD_NC(GPP_B20, NONE),
|
||||
PAD_NC(GPP_B21, NONE),
|
||||
PAD_NC(GPP_B22, NONE),
|
||||
PAD_CFG_TERM_GPO(GPP_B23, 0, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_C2, NONE),
|
||||
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_C5, NONE),
|
||||
PAD_CFG_NF(GPP_C6, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPP_C7, NONE, PWROK, NF1),
|
||||
PAD_NC(GPP_C8, NONE),
|
||||
PAD_NC(GPP_C9, NONE),
|
||||
PAD_NC(GPP_C10, NONE),
|
||||
PAD_NC(GPP_C11, NONE),
|
||||
PAD_NC(GPP_C12, NONE),
|
||||
PAD_NC(GPP_C13, NONE),
|
||||
_PAD_CFG_STRUCT(GPP_C14, 0x40100100, 0x3000),
|
||||
PAD_NC(GPP_C15, NONE),
|
||||
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
|
||||
// UART2_RXD
|
||||
PAD_CFG_NF(GPP_C20, UP_20K, DEEP, NF1),
|
||||
// UART2_TXD
|
||||
PAD_CFG_NF(GPP_C21, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_C22, 1, NONE, PLTRST),
|
||||
_PAD_CFG_STRUCT(GPP_C23, 0x40880100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_D0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_D1, 1, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_D2, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_D3, NONE, PLTRST),
|
||||
PAD_NC(GPP_D4, NONE),
|
||||
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_D9, NONE),
|
||||
PAD_NC(GPP_D10, NONE),
|
||||
PAD_CFG_GPI(GPP_D11, DN_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D12, DN_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_D13, 1, NONE, PLTRST),
|
||||
PAD_CFG_TERM_GPO(GPP_D14, 1, NONE, PLTRST),
|
||||
PAD_NC(GPP_D15, NONE),
|
||||
PAD_NC(GPP_D16, NONE),
|
||||
PAD_NC(GPP_D17, NONE),
|
||||
PAD_NC(GPP_D18, NONE),
|
||||
PAD_NC(GPP_D19, NONE),
|
||||
PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_E1, 0, NONE, PLTRST),
|
||||
_PAD_CFG_STRUCT(GPP_E2, 0x40880100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_E3, DN_20K, DEEP),
|
||||
PAD_NC(GPP_E4, NONE),
|
||||
PAD_NC(GPP_E5, NONE),
|
||||
PAD_NC(GPP_E6, NONE),
|
||||
_PAD_CFG_STRUCT(GPP_E7, 0x82840100, 0x0000),
|
||||
PAD_NC(GPP_E8, NONE),
|
||||
PAD_NC(GPP_E9, NONE),
|
||||
PAD_NC(GPP_E10, NONE),
|
||||
PAD_NC(GPP_E11, NONE),
|
||||
PAD_NC(GPP_E12, NONE),
|
||||
PAD_NC(GPP_E13, NONE),
|
||||
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_E15, NONE),
|
||||
PAD_CFG_GPI(GPP_E16, DN_20K, DEEP),
|
||||
PAD_NC(GPP_E17, NONE),
|
||||
// GPP_E18_TBT_LSX0_TXD - programmed by FSP, see Intel document 617016
|
||||
PAD_NC(GPP_E18, NATIVE),
|
||||
// GPP_E19_TBT_LSX0_RXD - programmed by FSP, see Intel document 617016
|
||||
PAD_NC(GPP_E19, NATIVE),
|
||||
PAD_NC(GPP_E20, NONE),
|
||||
PAD_NC(GPP_E21, NONE),
|
||||
PAD_NC(GPP_E22, NONE),
|
||||
PAD_NC(GPP_E23, NONE),
|
||||
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
|
||||
PAD_NC(GPP_F4, NONE),
|
||||
PAD_NC(GPP_F5, NONE),
|
||||
PAD_NC(GPP_F6, NONE),
|
||||
PAD_CFG_TERM_GPO(GPP_F7, 1, NONE, DEEP),
|
||||
PAD_NC(GPP_F8, NONE),
|
||||
PAD_CFG_TERM_GPO(GPP_F9, 1, NONE, DEEP),
|
||||
PAD_NC(GPP_F10, NONE),
|
||||
PAD_NC(GPP_F11, NONE),
|
||||
PAD_NC(GPP_F12, NONE),
|
||||
PAD_NC(GPP_F13, NONE),
|
||||
PAD_NC(GPP_F14, NONE),
|
||||
PAD_NC(GPP_F15, NONE),
|
||||
PAD_NC(GPP_F16, NONE),
|
||||
PAD_CFG_GPI(GPP_F17, NONE, PLTRST),
|
||||
PAD_NC(GPP_F18, NONE),
|
||||
PAD_NC(GPP_F19, NONE),
|
||||
PAD_NC(GPP_F20, NONE),
|
||||
PAD_CFG_GPI(GPP_F21, DN_20K, DEEP),
|
||||
PAD_NC(GPP_F22, NONE),
|
||||
PAD_NC(GPP_F23, NONE),
|
||||
PAD_CFG_TERM_GPO(GPP_H0, 1, NONE, PLTRST),
|
||||
PAD_NC(GPP_H1, NONE),
|
||||
PAD_NC(GPP_H2, NONE),
|
||||
PAD_CFG_GPI(GPP_H3, DN_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_H6, NONE),
|
||||
PAD_NC(GPP_H7, NONE),
|
||||
PAD_CFG_GPI(GPP_H8, DN_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H9, DN_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_H11, NONE),
|
||||
PAD_NC(GPP_H12, NONE),
|
||||
PAD_NC(GPP_H13, NONE),
|
||||
PAD_NC(GPP_H14, NONE),
|
||||
PAD_NC(GPP_H15, NONE),
|
||||
PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_H19, NONE),
|
||||
PAD_NC(GPP_H20, NONE),
|
||||
PAD_NC(GPP_H21, NONE),
|
||||
PAD_NC(GPP_H22, NONE),
|
||||
PAD_NC(GPP_H23, NONE),
|
||||
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_R5, NONE),
|
||||
PAD_NC(GPP_R6, NONE),
|
||||
PAD_NC(GPP_R7, NONE),
|
||||
PAD_NC(GPP_S0, NONE),
|
||||
PAD_NC(GPP_S1, NONE),
|
||||
PAD_NC(GPP_S2, NONE),
|
||||
PAD_NC(GPP_S3, NONE),
|
||||
PAD_NC(GPP_S4, NONE),
|
||||
PAD_NC(GPP_S5, NONE),
|
||||
PAD_NC(GPP_S6, NONE),
|
||||
PAD_NC(GPP_S7, NONE),
|
||||
PAD_NC(GPP_T2, NONE),
|
||||
PAD_NC(GPP_T3, NONE),
|
||||
PAD_CFG_TERM_GPO(GPP_U4, 0, NONE, PLTRST),
|
||||
PAD_CFG_TERM_GPO(GPP_U5, 1, NONE, PLTRST),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
26
src/mainboard/system76/darp7/hda_verb.c
Normal file
26
src/mainboard/system76/darp7/hda_verb.c
Normal file
@ -0,0 +1,26 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC293 */
|
||||
0x10ec0293, /* Vendor ID */
|
||||
0x155851a1, /* Subsystem ID */
|
||||
12, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x155851a1),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x13, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x15, 0x02211020),
|
||||
AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x40738205),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
18
src/mainboard/system76/darp7/ramstage.c
Normal file
18
src/mainboard/system76/darp7/ramstage.c
Normal file
@ -0,0 +1,18 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <soc/ramstage.h>
|
||||
#include "gpio.h"
|
||||
|
||||
void mainboard_silicon_init_params(FSP_S_CONFIG *params) {
|
||||
// CPU RP Config
|
||||
params->CpuPcieRpAdvancedErrorReporting[0] = 0;
|
||||
params->CpuPcieRpLtrEnable[0] = 1;
|
||||
params->CpuPcieRpPtmEnabled[0] = 0;
|
||||
|
||||
// IOM config
|
||||
params->PchUsbOverCurrentEnable = 0;
|
||||
params->PortResetMessageEnable[5] = 1; // J_TYPEC2
|
||||
params->UsbTcPortEn = 1;
|
||||
|
||||
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
|
||||
}
|
||||
35
src/mainboard/system76/darp7/romstage.c
Normal file
35
src/mainboard/system76/darp7/romstage.c
Normal file
@ -0,0 +1,35 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <fsp/util.h>
|
||||
#include <soc/meminit.h>
|
||||
#include <soc/romstage.h>
|
||||
|
||||
static const struct mb_ddr4_cfg board_cfg = {
|
||||
// dq_map unused on DDR4
|
||||
// dqs_map unused on DDR4
|
||||
|
||||
// TGL-U does not support interleaved memory
|
||||
.dq_pins_interleaved = 0,
|
||||
|
||||
//TODO: can we use early command training?
|
||||
.ect = 0,
|
||||
};
|
||||
|
||||
static const struct spd_info spd = {
|
||||
.topology = SODIMM,
|
||||
.smbus_info[0] = {
|
||||
.addr_dimm0 = 0x50,
|
||||
},
|
||||
.smbus_info[1] = {
|
||||
.addr_dimm0 = 0x52,
|
||||
},
|
||||
};
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *mupd) {
|
||||
//TODO: Allow memory clocks higher than 2933 MHz
|
||||
mupd->FspmConfig.SaOcSupport = 1;
|
||||
|
||||
//TODO: what is this for?
|
||||
const bool half_populated = false;
|
||||
meminit_ddr4(&mupd->FspmConfig, &board_cfg, &spd, half_populated);
|
||||
}
|
||||
85
src/mainboard/system76/galp5/Kconfig
Normal file
85
src/mainboard/system76/galp5/Kconfig
Normal file
@ -0,0 +1,85 @@
|
||||
if BOARD_SYSTEM76_GALP5
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS
|
||||
def_bool y
|
||||
select BOARD_ROMSIZE_KB_16384
|
||||
select DRIVERS_I2C_HID
|
||||
select DRIVERS_INTEL_PMC
|
||||
select DRIVERS_INTEL_USB4_RETIMER
|
||||
select DRIVERS_SYSTEM76_DGPU
|
||||
select EC_SYSTEM76_EC
|
||||
select EC_SYSTEM76_EC_BAT_THRESHOLDS
|
||||
select EC_SYSTEM76_EC_DGPU
|
||||
select HAVE_ACPI_TABLES
|
||||
select HAVE_CMOS_DEFAULT
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_SMI_HANDLER
|
||||
select INTEL_GMA_HAVE_VBT
|
||||
select INTEL_LPSS_UART_FOR_CONSOLE
|
||||
select MAINBOARD_HAS_LPC_TPM
|
||||
select MAINBOARD_HAS_TPM2
|
||||
select NO_UART_ON_SUPERIO
|
||||
select PCIEXP_HOTPLUG
|
||||
select SOC_INTEL_TIGERLAKE
|
||||
select SOC_INTEL_COMMON_BLOCK_HDA
|
||||
select SOC_INTEL_COMMON_BLOCK_HDA_VERB
|
||||
select SPD_READ_BY_WORD
|
||||
select SYSTEM_TYPE_LAPTOP
|
||||
select TPM_RDRESP_NEED_DELAY
|
||||
select USE_OPTION_TABLE
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default "system76/galp5"
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "galp5"
|
||||
|
||||
config MAINBOARD_SMBIOS_PRODUCT_NAME
|
||||
string
|
||||
default "Galago Pro"
|
||||
|
||||
config MAINBOARD_VERSION
|
||||
string
|
||||
default "galp5"
|
||||
|
||||
#TODO: subsystem IDs
|
||||
|
||||
config CBFS_SIZE
|
||||
hex
|
||||
default 0xA00000
|
||||
|
||||
config CONSOLE_POST
|
||||
bool
|
||||
default y
|
||||
|
||||
config DIMM_MAX
|
||||
int
|
||||
default 4 # Hack to make soc code work
|
||||
|
||||
config DIMM_SPD_SIZE
|
||||
int
|
||||
default 512
|
||||
|
||||
config DRIVERS_SYSTEM76_DGPU_DEVICE
|
||||
hex
|
||||
default 0x1c
|
||||
|
||||
config MAX_CPUS
|
||||
int
|
||||
default 8
|
||||
|
||||
config ONBOARD_VGA_IS_PRIMARY
|
||||
bool
|
||||
default y
|
||||
|
||||
config POST_DEVICE
|
||||
bool
|
||||
default n
|
||||
|
||||
config UART_FOR_CONSOLE
|
||||
int
|
||||
default 2
|
||||
|
||||
endif
|
||||
2
src/mainboard/system76/galp5/Kconfig.name
Normal file
2
src/mainboard/system76/galp5/Kconfig.name
Normal file
@ -0,0 +1,2 @@
|
||||
config BOARD_SYSTEM76_GALP5
|
||||
bool "galp5"
|
||||
3
src/mainboard/system76/galp5/Makefile.inc
Normal file
3
src/mainboard/system76/galp5/Makefile.inc
Normal file
@ -0,0 +1,3 @@
|
||||
bootblock-y += bootblock.c
|
||||
ramstage-y += ramstage.c
|
||||
ramstage-y += hda_verb.c
|
||||
30
src/mainboard/system76/galp5/acpi/backlight.asl
Normal file
30
src/mainboard/system76/galp5/acpi/backlight.asl
Normal file
@ -0,0 +1,30 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <drivers/intel/gma/acpi/gma.asl>
|
||||
|
||||
Scope (GFX0) {
|
||||
Name (BRIG, Package (22) {
|
||||
40, /* default AC */
|
||||
40, /* default Battery */
|
||||
5,
|
||||
10,
|
||||
15,
|
||||
20,
|
||||
25,
|
||||
30,
|
||||
35,
|
||||
40,
|
||||
45,
|
||||
50,
|
||||
55,
|
||||
60,
|
||||
65,
|
||||
70,
|
||||
75,
|
||||
80,
|
||||
85,
|
||||
90,
|
||||
95,
|
||||
100
|
||||
})
|
||||
}
|
||||
30
src/mainboard/system76/galp5/acpi/dgpu.asl
Normal file
30
src/mainboard/system76/galp5/acpi/dgpu.asl
Normal file
@ -0,0 +1,30 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
Scope (\_SB.PCI0.RP01) {
|
||||
Device (DEV0) {
|
||||
Name(_ADR, 0x00000000)
|
||||
|
||||
OperationRegion (PCIC, PCI_Config, 0x00, 0x50)
|
||||
Field (PCIC, DwordAcc, NoLock, Preserve) {
|
||||
Offset (0x40),
|
||||
SSID, 32
|
||||
}
|
||||
|
||||
Name (_PR0, Package () { PWRR })
|
||||
Name (_PR3, Package () { PWRR })
|
||||
PowerResource (PWRR, 0, 0) {
|
||||
Name (_STA, 1)
|
||||
|
||||
Method (_ON) {
|
||||
^^SSID = 0x40181558
|
||||
Printf("GPU _ON %o", ToHexString(^^SSID))
|
||||
_STA = 1
|
||||
}
|
||||
|
||||
Method (_OFF) {
|
||||
Printf("GPU _OFF %o", ToHexString(^^SSID))
|
||||
_STA = 0
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
15
src/mainboard/system76/galp5/acpi/mainboard.asl
Normal file
15
src/mainboard/system76/galp5/acpi/mainboard.asl
Normal file
@ -0,0 +1,15 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include "../gpio.h"
|
||||
#include "dgpu.asl"
|
||||
|
||||
#define EC_GPE_SCI 0x6E
|
||||
#define EC_GPE_SWI 0x6E
|
||||
#include <ec/system76/ec/acpi/ec.asl>
|
||||
|
||||
Scope (\_SB) {
|
||||
#include "sleep.asl"
|
||||
Scope (PCI0) {
|
||||
#include "backlight.asl"
|
||||
}
|
||||
}
|
||||
46
src/mainboard/system76/galp5/acpi/sleep.asl
Normal file
46
src/mainboard/system76/galp5/acpi/sleep.asl
Normal file
@ -0,0 +1,46 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <intelblocks/gpio.h>
|
||||
|
||||
Method (PGPM, 1, Serialized)
|
||||
{
|
||||
For (Local0 = 0, Local0 < 6, Local0++)
|
||||
{
|
||||
\_SB.PCI0.CGPM (Local0, Arg0)
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Method called from _PTS prior to system sleep state entry
|
||||
* Enables dynamic clock gating for all 5 GPIO communities
|
||||
*/
|
||||
Method (MPTS, 1, Serialized)
|
||||
{
|
||||
\_SB.PCI0.LPCB.EC0.PTS (Arg0)
|
||||
PGPM (MISCCFG_ENABLE_GPIO_PM_CONFIG)
|
||||
}
|
||||
|
||||
/*
|
||||
* Method called from _WAK prior to system sleep state wakeup
|
||||
* Disables dynamic clock gating for all 5 GPIO communities
|
||||
*/
|
||||
Method (MWAK, 1, Serialized)
|
||||
{
|
||||
PGPM (0)
|
||||
\_SB.PCI0.LPCB.EC0.WAK (Arg0)
|
||||
}
|
||||
|
||||
/*
|
||||
* S0ix Entry/Exit Notifications
|
||||
* Called from \_SB.PEPD._DSM
|
||||
*/
|
||||
Method (MS0X, 1, Serialized)
|
||||
{
|
||||
If (Arg0 == 1) {
|
||||
/* S0ix Entry */
|
||||
PGPM (MISCCFG_ENABLE_GPIO_PM_CONFIG)
|
||||
} Else {
|
||||
/* S0ix Exit */
|
||||
PGPM (0)
|
||||
}
|
||||
}
|
||||
8
src/mainboard/system76/galp5/board_info.txt
Normal file
8
src/mainboard/system76/galp5/board_info.txt
Normal file
@ -0,0 +1,8 @@
|
||||
Vendor name: System76
|
||||
Board name: galp5
|
||||
Category: laptop
|
||||
Release year: 2020
|
||||
ROM package: SOIC-8
|
||||
ROM protocol: SPI
|
||||
ROM socketed: n
|
||||
Flashrom support: y
|
||||
11
src/mainboard/system76/galp5/bootblock.c
Normal file
11
src/mainboard/system76/galp5/bootblock.c
Normal file
@ -0,0 +1,11 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <bootblock_common.h>
|
||||
#include <gpio.h>
|
||||
#include "gpio.h"
|
||||
#include <drivers/system76/dgpu/bootblock.c>
|
||||
|
||||
void bootblock_mainboard_init(void) {
|
||||
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
|
||||
dgpu_power_enable(1);
|
||||
}
|
||||
2
src/mainboard/system76/galp5/cmos.default
Normal file
2
src/mainboard/system76/galp5/cmos.default
Normal file
@ -0,0 +1,2 @@
|
||||
boot_option=Fallback
|
||||
preserve_smmstore=0
|
||||
35
src/mainboard/system76/galp5/cmos.layout
Normal file
35
src/mainboard/system76/galp5/cmos.layout
Normal file
@ -0,0 +1,35 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
entries
|
||||
|
||||
0 384 r 0 reserved_memory
|
||||
|
||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||
384 1 e 2 boot_option
|
||||
388 4 h 0 reboot_counter
|
||||
|
||||
#395 4 e 3 debug_level
|
||||
408 1 h 1 preserve_smmstore
|
||||
984 16 h 0 check_sum
|
||||
|
||||
enumerations
|
||||
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
|
||||
2 0 Fallback
|
||||
2 1 Normal
|
||||
|
||||
3 0 Emergency
|
||||
3 1 Alert
|
||||
3 2 Critical
|
||||
3 3 Error
|
||||
3 4 Warning
|
||||
3 5 Notice
|
||||
3 6 Info
|
||||
3 7 Debug
|
||||
3 8 Spew
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 983 984
|
||||
367
src/mainboard/system76/galp5/devicetree.cb
Normal file
367
src/mainboard/system76/galp5/devicetree.cb
Normal file
@ -0,0 +1,367 @@
|
||||
chip soc/intel/tigerlake
|
||||
register "common_soc_config" = "{
|
||||
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
|
||||
// Touchpad I2C bus
|
||||
.i2c[0] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.rise_time_ns = 80,
|
||||
.fall_time_ns = 110,
|
||||
},
|
||||
}"
|
||||
|
||||
# ACPI (soc/intel/tigerlake/acpi.c)
|
||||
# Disable DPTF
|
||||
register "dptf_enable" = "0"
|
||||
|
||||
# Enable Enhanced Intel SpeedStep
|
||||
register "eist_enable" = "1"
|
||||
|
||||
# Enable s0ix, required for TGL-U
|
||||
register "s0ix_enable" = "1"
|
||||
|
||||
# CPU (soc/intel/tigerlake/cpu.c)
|
||||
# Power limits
|
||||
register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{
|
||||
// /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw
|
||||
.tdp_pl1_override = 28,
|
||||
// /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw
|
||||
.tdp_pl2_override = 51,
|
||||
}"
|
||||
register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{
|
||||
// /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw
|
||||
.tdp_pl1_override = 28,
|
||||
// /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw
|
||||
.tdp_pl2_override = 51,
|
||||
}"
|
||||
|
||||
# Finalize (soc/intel/tigerlake/finalize.c)
|
||||
# PM Timer Disabled, saves power
|
||||
register "PmTimerDisabled" = "1"
|
||||
|
||||
# FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c)
|
||||
# Enable C6 DRAM
|
||||
register "enable_c6dram" = "1"
|
||||
|
||||
# System Agent dynamic frequency support
|
||||
register "SaGv" = "SaGv_Enabled"
|
||||
|
||||
# FSP Silicon (soc/intel/tigerlake/fsp_params.c)
|
||||
# Acoustic settings
|
||||
register "AcousticNoiseMitigation" = "1"
|
||||
register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
|
||||
register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
|
||||
register "SlowSlewRate[VR_DOMAIN_SA]" = "SLEW_FAST_8"
|
||||
register "SlowSlewRate[VR_DOMAIN_VLCC]" = "SLEW_FAST_8"
|
||||
register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1"
|
||||
register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1"
|
||||
register "FastPkgCRampDisable[VR_DOMAIN_SA]" = "1"
|
||||
register "FastPkgCRampDisable[VR_DOMAIN_VLCC]" = "1"
|
||||
|
||||
# FIVR configuration
|
||||
# Read EXT_RAIL_CONFIG to determine bitmaps
|
||||
# sudo devmem2 0xfe0011b8
|
||||
# 0x0
|
||||
# Read EXT_V1P05_VR_CONFIG
|
||||
# sudo devmem2 0xfe0011c0
|
||||
# 0x1a42000
|
||||
# Read EXT_VNN_VR_CONFIG0
|
||||
# sudo devmem2 0xfe0011c4
|
||||
# 0x1a42000
|
||||
# TODO: v1p05 voltage and vnn icc max?
|
||||
register "ext_fivr_settings" = "{
|
||||
.configure_ext_fivr = 1,
|
||||
.v1p05_enable_bitmap = 0,
|
||||
.vnn_enable_bitmap = 0,
|
||||
.v1p05_supported_voltage_bitmap = 0,
|
||||
.vnn_supported_voltage_bitmap = 0,
|
||||
.v1p05_icc_max_ma = 500,
|
||||
.vnn_sx_voltage_mv = 1050,
|
||||
}"
|
||||
|
||||
# Read LPM_EN, make sure to invert the bits
|
||||
# sudo devmem2 0xfe001c78
|
||||
# 0x9
|
||||
register "LpmStateDisableMask" = "
|
||||
LPM_S0i2_1 |
|
||||
LPM_S0i2_2 |
|
||||
LPM_S0i3_1 |
|
||||
LPM_S0i3_2 |
|
||||
LPM_S0i3_3 |
|
||||
LPM_S0i3_4
|
||||
"
|
||||
|
||||
# Thermal
|
||||
# rdmsr --bitfield 31:24 --decimal 0x1A2
|
||||
register "tcc_offset" = "12"
|
||||
|
||||
# PM Util (soc/intel/tigerlake/pmutil.c)
|
||||
# GPE configuration
|
||||
# sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
|
||||
# 0x432
|
||||
register "pmc_gpe0_dw0" = "PMC_GPP_A"
|
||||
register "pmc_gpe0_dw1" = "PMC_GPP_R"
|
||||
register "pmc_gpe0_dw2" = "PMC_GPD"
|
||||
|
||||
# Actual device tree
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
||||
device domain 0 on
|
||||
#From CPU EDS(575683)
|
||||
device ref system_agent on end
|
||||
device ref igpu on
|
||||
# DDIA is eDP
|
||||
register "DdiPortAConfig" = "1"
|
||||
register "DdiPortAHpd" = "1"
|
||||
register "DdiPortADdc" = "0"
|
||||
|
||||
# DDIB is HDMI
|
||||
register "DdiPortBConfig" = "0"
|
||||
register "DdiPortBHpd" = "1"
|
||||
register "DdiPortBDdc" = "1"
|
||||
|
||||
register "gfx" = "GMA_STATIC_DISPLAYS(0)"
|
||||
end
|
||||
device ref dptf on
|
||||
register "Device4Enable" = "1"
|
||||
end
|
||||
device ref peg on
|
||||
# PCIe PEG0 x4, Clock 0 (SSD1)
|
||||
register "PcieClkSrcUsage[0]" = "0x40"
|
||||
register "PcieClkSrcClkReq[0]" = "0"
|
||||
#TODO: causes failure on resume
|
||||
# chip soc/intel/common/block/pcie/rtd3
|
||||
# register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD1_PWR_DN#
|
||||
# register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" # GPP_H0_RTD3
|
||||
# #TODO: Support disable/enable CPU RP clock
|
||||
# register "srcclk_pin" = "-1" # SSD1_CLKREQ#
|
||||
# device generic 0 on end
|
||||
# end
|
||||
|
||||
#TODO: Hybrid storage mode?
|
||||
register "HybridStorageMode" = "0"
|
||||
end
|
||||
device ref tbt_pcie_rp0 on end # J_TYPEC2
|
||||
device ref gna on end
|
||||
device ref north_xhci on # J_TYPEC2
|
||||
register "TcssXhciEn" = "1"
|
||||
chip drivers/usb/acpi
|
||||
device ref tcss_root_hub on
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 J_TYPEC2""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "group" = "ACPI_PLD_GROUP(1, 1)"
|
||||
device ref tcss_usb3_port1 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref tbt_dma0 on # J_TYPEC2
|
||||
chip drivers/intel/usb4/retimer
|
||||
register "power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A23)"
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
|
||||
# From PCH EDS(576591)
|
||||
device ref cnvi_bt on end
|
||||
device ref south_xhci on
|
||||
# USB2
|
||||
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # J_USB3_2
|
||||
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1
|
||||
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # J_USB3_1
|
||||
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
|
||||
register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC2
|
||||
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Camera
|
||||
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
|
||||
# USB3
|
||||
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB3_2
|
||||
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1 CH0
|
||||
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB3_1
|
||||
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1 CH1
|
||||
# ACPI
|
||||
chip drivers/usb/acpi
|
||||
device ref xhci_root_hub on
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 J_USB3_2""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "group" = "ACPI_PLD_GROUP(1, 2)"
|
||||
device ref usb2_port1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 J_TYPEC1""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "group" = "ACPI_PLD_GROUP(2, 1)"
|
||||
device ref usb2_port2 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 J_USB3_1""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "group" = "ACPI_PLD_GROUP(2, 2)"
|
||||
device ref usb2_port3 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Fingerprint""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device ref usb2_port5 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 J_TYPEC2""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "group" = "ACPI_PLD_GROUP(1, 1)"
|
||||
device ref usb2_port6 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Camera""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device ref usb2_port7 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Bluetooth""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device ref usb2_port10 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 J_USB3_2""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "group" = "ACPI_PLD_GROUP(1, 2)"
|
||||
device ref usb3_port1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 J_TYPEC1 CH0""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "group" = "ACPI_PLD_GROUP(2, 1)"
|
||||
device ref usb3_port2 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 J_USB3_1""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "group" = "ACPI_PLD_GROUP(2, 2)"
|
||||
device ref usb3_port3 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 J_TYPEC1 CH1""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "group" = "ACPI_PLD_GROUP(2, 1)"
|
||||
device ref usb3_port4 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref shared_ram on end
|
||||
device ref cnvi_wifi on
|
||||
chip drivers/wifi/generic
|
||||
register "wake" = "GPE0_PME_B0"
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref i2c0 on
|
||||
# Touchpad I2C bus
|
||||
register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""PNP0C50""
|
||||
register "generic.desc" = ""FocalTech Touchpad""
|
||||
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B3)"
|
||||
register "generic.probed" = "1"
|
||||
register "hid_desc_reg_offset" = "0x01"
|
||||
device i2c 38 on end
|
||||
end
|
||||
end
|
||||
device ref i2c1 on
|
||||
#TODO: USB-PD?
|
||||
register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
|
||||
end
|
||||
device ref i2c2 on
|
||||
#TODO: Pantone ROM?
|
||||
register "SerialIoI2cMode[PchSerialIoIndexI2C2]" = "PchSerialIoPci"
|
||||
end
|
||||
device ref heci1 on
|
||||
#TODO Disable ME and HECI
|
||||
register "HeciEnabled" = "1"
|
||||
end
|
||||
device ref uart2 on
|
||||
# Debug console
|
||||
register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit"
|
||||
end
|
||||
device ref pcie_rp5 on
|
||||
# PCIe root port #5 x4, Clock 2 (NVIDIA GPU)
|
||||
register "PcieRpEnable[4]" = "1"
|
||||
register "PcieRpLtrEnable[4]" = "1"
|
||||
register "PcieClkSrcUsage[2]" = "4"
|
||||
register "PcieClkSrcClkReq[2]" = "2"
|
||||
chip soc/intel/common/block/pcie/rtd3
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_U5)" # DGPU_PWR_EN
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_U4)" # DGPU_RST#_PCH
|
||||
register "srcclk_pin" = "2" # PEG_CLKREQ#
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref pcie_rp9 on
|
||||
# PCIe root port #9 x1, Clock 3 (CARD)
|
||||
register "PcieRpEnable[8]" = "1"
|
||||
register "PcieRpLtrEnable[8]" = "1"
|
||||
register "PcieClkSrcUsage[3]" = "8"
|
||||
register "PcieClkSrcClkReq[3]" = "3"
|
||||
end
|
||||
device ref pcie_rp10 on
|
||||
# PCIe root port #10 x1, Clock 4 (GLAN)
|
||||
register "PcieRpEnable[9]" = "1"
|
||||
register "PcieRpLtrEnable[9]" = "1"
|
||||
register "PcieClkSrcUsage[4]" = "9"
|
||||
register "PcieClkSrcClkReq[4]" = "4"
|
||||
chip soc/intel/common/block/pcie/rtd3
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # GPIO_LAN_EN
|
||||
#TODO: should this be GPIO_LANRTD3 or LAN_PLT_RST# ?
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F7)" # GPIO_LANRTD3
|
||||
register "srcclk_pin" = "4" # LAN_CLKREQ#
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref pcie_rp11 on
|
||||
# PCIe root port #11 x1, Clock 1 (WLAN)
|
||||
register "PcieRpEnable[10]" = "1"
|
||||
register "PcieRpLtrEnable[10]" = "1"
|
||||
register "PcieClkSrcUsage[1]" = "10"
|
||||
register "PcieClkSrcClkReq[1]" = "1"
|
||||
end
|
||||
device ref pch_espi on
|
||||
# LPC configuration from lspci -s 1f.0 -xxx
|
||||
# Address 0x84: Decode 0x80 - 0x8F (Port 80)
|
||||
register "gen1_dec" = "0x000c0081"
|
||||
# Address 0x88: Decode 0x68 - 0x6F (PMC)
|
||||
register "gen2_dec" = "0x00040069"
|
||||
# Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command)
|
||||
register "gen3_dec" = "0x00fc0E01"
|
||||
# Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug)
|
||||
register "gen4_dec" = "0x00fc0F01"
|
||||
# LPC TPM
|
||||
chip drivers/pc80/tpm
|
||||
device pnp 0c31.0 on end
|
||||
end
|
||||
end
|
||||
device ref p2sb on end
|
||||
device ref pmc hidden
|
||||
# The pmc_mux chip driver is a placeholder for the
|
||||
# PMC.MUX device in the ACPI hierarchy.
|
||||
chip drivers/intel/pmc_mux
|
||||
device generic 0 on
|
||||
chip drivers/intel/pmc_mux/conn
|
||||
# J_TYPEC2
|
||||
register "usb2_port_number" = "6"
|
||||
register "usb3_port_number" = "1"
|
||||
# SBU & HSL follow CC
|
||||
device generic 0 alias conn0 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref hda on
|
||||
register "PchHdaAudioLinkHdaEnable" = "1"
|
||||
end
|
||||
device ref smbus on
|
||||
register "SmbusEnable" = "1"
|
||||
end
|
||||
device ref fast_spi on end
|
||||
end
|
||||
end
|
||||
41
src/mainboard/system76/galp5/dsdt.asl
Normal file
41
src/mainboard/system76/galp5/dsdt.asl
Normal file
@ -0,0 +1,41 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
//TODO: cleaner solution for ACPI brightness
|
||||
#define SYSTEM76_ACPI_NO_GFX0
|
||||
|
||||
#include <acpi/acpi.h>
|
||||
|
||||
DefinitionBlock(
|
||||
"dsdt.aml",
|
||||
"DSDT",
|
||||
ACPI_DSDT_REV_2,
|
||||
OEM_ID,
|
||||
ACPI_TABLE_CREATOR,
|
||||
0x20110725 // OEM revision
|
||||
)
|
||||
{
|
||||
#include <soc/intel/common/block/acpi/acpi/platform.asl>
|
||||
|
||||
// global NVS and variables
|
||||
#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
|
||||
|
||||
// CPU
|
||||
#include <cpu/intel/common/acpi/cpu.asl>
|
||||
|
||||
Scope (\_SB) {
|
||||
Device (PCI0)
|
||||
{
|
||||
#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
|
||||
#include <soc/intel/tigerlake/acpi/southbridge.asl>
|
||||
#include <soc/intel/tigerlake/acpi/tcss.asl>
|
||||
}
|
||||
}
|
||||
|
||||
Scope (\_SB.PCI0.LPCB) {
|
||||
#include <drivers/pc80/pc/ps2_controller.asl>
|
||||
}
|
||||
|
||||
#include <southbridge/intel/common/acpi/sleepstates.asl>
|
||||
|
||||
#include "acpi/mainboard.asl"
|
||||
}
|
||||
422
src/mainboard/system76/galp5/gpio.h
Normal file
422
src/mainboard/system76/galp5/gpio.h
Normal file
@ -0,0 +1,422 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#define DGPU_RST_N GPP_U4
|
||||
#define DGPU_PWR_EN GPP_U5
|
||||
#define DGPU_GC6 GPP_D2
|
||||
|
||||
#ifndef __ACPI__
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
/* Pad configuration in romstage. */
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
// UART2_RXD
|
||||
PAD_CFG_NF(GPP_C20, UP_20K, DEEP, NF1),
|
||||
// UART2_TXD
|
||||
PAD_CFG_NF(GPP_C21, UP_20K, DEEP, NF1),
|
||||
// DGPU_RST#_PCH
|
||||
PAD_CFG_TERM_GPO(GPP_U4, 0, NONE, DEEP),
|
||||
// DGPU_PWR_EN
|
||||
PAD_CFG_TERM_GPO(GPP_U5, 0, NONE, DEEP),
|
||||
};
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
// PM_BATLOW#
|
||||
PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
|
||||
// AC_PRESENT
|
||||
PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
|
||||
// LAN_WAKEUP#
|
||||
PAD_CFG_GPI(GPD2, NONE, PWROK),
|
||||
// PWR_BTN#
|
||||
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
|
||||
// SUSB#_PCH
|
||||
PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
|
||||
// SUSC#_PCH
|
||||
PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
|
||||
// SLP_A# - test point
|
||||
PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
|
||||
// GPD7_REST
|
||||
PAD_CFG_TERM_GPO(GPD7, 1, NONE, PWROK),
|
||||
// SUS_CLK
|
||||
PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
|
||||
// GPD9_RTD3
|
||||
PAD_CFG_TERM_GPO(GPD9, 0, NONE, PWROK),
|
||||
// SLP_S5# - test point
|
||||
PAD_CFG_NF(GPD10, UP_20K, DEEP, NF1),
|
||||
// LAN_DISABLE#
|
||||
PAD_CFG_GPI(GPD11, UP_20K, DEEP),
|
||||
// ESPI_IO0_EC
|
||||
PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1),
|
||||
// ESPI_IO1_EC
|
||||
PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
|
||||
// ESPI_IO2_EC
|
||||
PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
|
||||
// ESPI_IO3_EC
|
||||
PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
|
||||
// ESPI_CS_EC#
|
||||
PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
|
||||
// ESPI_CLK_EC
|
||||
PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1),
|
||||
// ESPI_RESET_N
|
||||
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
|
||||
// NC
|
||||
PAD_NC(GPP_A7, NONE),
|
||||
// CNVI_RST#
|
||||
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF2),
|
||||
// CNVI_CLKREQ
|
||||
PAD_CFG_NF(GPP_A9, NONE, DEEP, NF3),
|
||||
// NC
|
||||
PAD_NC(GPP_A10, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_A11, NONE),
|
||||
// SATAGP1
|
||||
PAD_NC(GPP_A12, NONE),
|
||||
// PCH_BT_EN
|
||||
PAD_CFG_TERM_GPO(GPP_A13, 1, NONE, PLTRST),
|
||||
// NC
|
||||
PAD_NC(GPP_A14, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_A15, NONE),
|
||||
// 10K pull-up
|
||||
PAD_NC(GPP_A16, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_A17, NONE),
|
||||
// HDMI_HPD
|
||||
PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
|
||||
// NC
|
||||
PAD_NC(GPP_A19, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_A20, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_A21, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_A22, NONE),
|
||||
// GPPC_A23_TBT_FORCE_PWR
|
||||
PAD_CFG_TERM_GPO(GPP_A23, 0, NONE, PLTRST),
|
||||
// VCCIN_AUX_VID0
|
||||
PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
|
||||
// VCCIN_AUX_VID1
|
||||
PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
|
||||
// VRALERT#_PD
|
||||
PAD_CFG_GPI(GPP_B2, UP_20K, DEEP),
|
||||
// GPP_B3 - touchpad interrupt
|
||||
PAD_CFG_GPI_INT(GPP_B3, NONE, PLTRST, LEVEL),
|
||||
// NC
|
||||
PAD_NC(GPP_B4, NONE),
|
||||
// test point
|
||||
PAD_NC(GPP_B5, NONE),
|
||||
// test point
|
||||
PAD_NC(GPP_B6, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_B7, NONE),
|
||||
// SB_BLON
|
||||
PAD_CFG_TERM_GPO(GPP_B8, 1, NONE, DEEP),
|
||||
// NC
|
||||
PAD_NC(GPP_B9, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_B10, NONE),
|
||||
// TBTA-PCH_I2C_INT
|
||||
PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1),
|
||||
// SLP_S0#
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
// PLT_RST#
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
// PCH_SPKR
|
||||
PAD_CFG_TERM_GPO(GPP_B14, 0, NONE, DEEP),
|
||||
// PCH_GPP_B15 - TODO
|
||||
PAD_CFG_TERM_GPO(GPP_B15, 1, NONE, DEEP),
|
||||
// NC
|
||||
PAD_NC(GPP_B16, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_B17, NONE),
|
||||
// No reboot strap
|
||||
PAD_NC(GPP_B18, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_B19, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_B20, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_B21, NONE),
|
||||
// PCH_GPP_B22 - 20k pull-down
|
||||
PAD_NC(GPP_B22, NONE),
|
||||
// Clock frequency strap
|
||||
PAD_CFG_TERM_GPO(GPP_B23, 0, NONE, DEEP),
|
||||
// SMB_CLK and SMB_CLK_DDR
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
// SMB_DATA and SMB_DAT_DDR
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
// Intel AMT TLS strap
|
||||
PAD_NC(GPP_C2, NONE),
|
||||
// SML0_CLK
|
||||
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
|
||||
// SML0_DATA
|
||||
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
|
||||
// Boot strap bit 0
|
||||
PAD_NC(GPP_C5, NONE),
|
||||
// TBT-PCH_I2C_SCL
|
||||
PAD_CFG_NF(GPP_C6, NONE, PWROK, NF1),
|
||||
// TBT-PCH_I2C_SDA
|
||||
PAD_CFG_NF(GPP_C7, NONE, PWROK, NF1),
|
||||
// NC
|
||||
PAD_NC(GPP_C8, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_C9, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_C10, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_C11, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_C12, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_C13, NONE),
|
||||
// TPM_PIRQ#
|
||||
_PAD_CFG_STRUCT(GPP_C14, 0x40100100, 0x3000),
|
||||
// NC
|
||||
PAD_NC(GPP_C15, NONE),
|
||||
// T_SDA
|
||||
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
|
||||
// T_SCL
|
||||
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
|
||||
// PCH_I2C_SDA
|
||||
PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
|
||||
// PCH_I2C_SCL
|
||||
PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
|
||||
// UART2_RXD
|
||||
PAD_CFG_NF(GPP_C20, UP_20K, DEEP, NF1),
|
||||
// UART2_TXD
|
||||
PAD_CFG_NF(GPP_C21, UP_20K, DEEP, NF1),
|
||||
// LAN_PLT_RST#
|
||||
PAD_CFG_TERM_GPO(GPP_C22, 1, NONE, PLTRST),
|
||||
// PCH_GPP_C23 - 4.7k pull-down
|
||||
_PAD_CFG_STRUCT(GPP_C23, 0x40880100, 0x0000),
|
||||
// DGPU_SELECT#
|
||||
PAD_CFG_GPI(GPP_D0, NONE, DEEP),
|
||||
// GPU_EVENT#
|
||||
PAD_CFG_TERM_GPO(GPP_D1, 1, NONE, PLTRST),
|
||||
// GC6_FB_EN_PCH
|
||||
PAD_CFG_GPI(GPP_D2, NONE, PLTRST),
|
||||
// DGPU_PWRGD_R
|
||||
PAD_CFG_GPI(GPP_D3, NONE, PLTRST),
|
||||
PAD_NC(GPP_D4, NONE),
|
||||
// SSD1_CLKREQ#
|
||||
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
|
||||
// WLAN_CLKREQ#
|
||||
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
|
||||
// PEG_CLKREQ#
|
||||
PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
|
||||
// CARD_CLKREQ#
|
||||
PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
|
||||
// NC
|
||||
PAD_NC(GPP_D9, NONE),
|
||||
// 4.7k pull-up
|
||||
PAD_NC(GPP_D10, NONE),
|
||||
// BOARD_ID - low = GTX 1650Ti, high = GTX 1650 - check GPP_D12
|
||||
PAD_CFG_GPI(GPP_D11, DN_20K, DEEP),
|
||||
// GPP_D12 - low = NVIDIA GPU, high = Intel GPU only
|
||||
PAD_CFG_GPI(GPP_D12, DN_20K, DEEP),
|
||||
// dGPU_OVRM
|
||||
PAD_CFG_TERM_GPO(GPP_D13, 0, NONE, DEEP),
|
||||
// SSD1_PWR_DN#
|
||||
PAD_CFG_TERM_GPO(GPP_D14, 1, NONE, PLTRST),
|
||||
// NC
|
||||
PAD_NC(GPP_D15, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_D16, NONE),
|
||||
// DGPU_PRSNT#
|
||||
PAD_CFG_GPI(GPP_D17, DN_20K, DEEP),
|
||||
// 1V8_MAIN_EN_R
|
||||
PAD_CFG_GPI(GPP_D18, DN_20K, DEEP),
|
||||
// NC
|
||||
PAD_NC(GPP_D19, NONE),
|
||||
// Test point
|
||||
PAD_NC(GPP_E0, NONE),
|
||||
// ROM_I2C_EN
|
||||
PAD_CFG_TERM_GPO(GPP_E1, 0, NONE, PLTRST),
|
||||
// SWI#
|
||||
_PAD_CFG_STRUCT(GPP_E2, 0x40880100, 0x0000),
|
||||
// SCI# - unused, tunneled over eSPI
|
||||
PAD_CFG_GPI(GPP_E3, DN_20K, DEEP),
|
||||
// Test point
|
||||
PAD_NC(GPP_E4, NONE),
|
||||
// DEVSLP1
|
||||
PAD_NC(GPP_E5, NONE),
|
||||
// PCH_GPP_E6
|
||||
PAD_NC(GPP_E6, NONE),
|
||||
// SMI#
|
||||
_PAD_CFG_STRUCT(GPP_E7, 0x82840100, 0x0000),
|
||||
// PCH_SATAHDD_LED#
|
||||
PAD_NC(GPP_E8, NONE),
|
||||
// 10k pull-up
|
||||
PAD_NC(GPP_E9, NONE),
|
||||
// PCH_GPP_E10
|
||||
PAD_NC(GPP_E10, NONE),
|
||||
// PCH_GPP_E11
|
||||
PAD_NC(GPP_E11, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_E12, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_E13, NONE),
|
||||
// EDP_HPD
|
||||
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
|
||||
// ALERT#_R
|
||||
PAD_NC(GPP_E15, NONE),
|
||||
// SB_KBCRST#
|
||||
PAD_CFG_GPI(GPP_E16, DN_20K, DEEP),
|
||||
// NC
|
||||
PAD_NC(GPP_E17, NONE),
|
||||
// GPP_E18_TBT_LSX0_TXD - programmed by FSP, see Intel document 617016
|
||||
PAD_NC(GPP_E18, NONE),
|
||||
// GPP_E19_TBT_LSX0_RXD - programmed by FSP, see Intel document 617016
|
||||
PAD_NC(GPP_E19, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_E20, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_E21, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_E22, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_E23, NONE),
|
||||
// CNVI_BRI_DT
|
||||
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
|
||||
// CNVI_BRI_RSP
|
||||
PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
|
||||
// CNVI_RGI_DT
|
||||
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
|
||||
// CNVI_RGI_RSP
|
||||
PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
|
||||
// NC
|
||||
PAD_NC(GPP_F4, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_F5, NONE),
|
||||
// CNVI_GNSS_PA_PLANKING - TODO
|
||||
PAD_NC(GPP_F6, NONE),
|
||||
// GPIO_LANRTD3
|
||||
PAD_CFG_TERM_GPO(GPP_F7, 1, NONE, DEEP),
|
||||
// NC
|
||||
PAD_NC(GPP_F8, NONE),
|
||||
// GPIO_LAN_EN
|
||||
PAD_CFG_TERM_GPO(GPP_F9, 1, NONE, DEEP),
|
||||
// 4.7k pull-up
|
||||
PAD_NC(GPP_F10, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_F11, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_F12, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_F13, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_F14, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_F15, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_F16, NONE),
|
||||
// TPM_DET#
|
||||
PAD_CFG_GPI(GPP_F17, NONE, PLTRST),
|
||||
// NC
|
||||
PAD_NC(GPP_F18, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_F19, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_F20, NONE),
|
||||
// EXT_PWR_GATE# - TODO
|
||||
PAD_CFG_GPI(GPP_F21, DN_20K, DEEP),
|
||||
// VNN_CTRL - TODO
|
||||
PAD_NC(GPP_F22, NONE),
|
||||
// 1P05_CTRL - TODO
|
||||
PAD_NC(GPP_F23, NONE),
|
||||
// GPP_H0_RTD3
|
||||
PAD_CFG_TERM_GPO(GPP_H0, 1, NONE, PLTRST),
|
||||
// 4.7k pull-up
|
||||
PAD_NC(GPP_H1, NONE),
|
||||
// 4.7k pull-up
|
||||
PAD_NC(GPP_H2, NONE),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_H3, DN_20K, DEEP),
|
||||
// GPPH_I2C2_SDA
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
|
||||
// GPPH_I2C2_SCL
|
||||
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
|
||||
// NC
|
||||
PAD_NC(GPP_H6, NONE),
|
||||
// SWI# - TODO
|
||||
PAD_NC(GPP_H7, NONE),
|
||||
// CNVI_MFUART2_RXD - TODO
|
||||
PAD_CFG_GPI(GPP_H8, DN_20K, DEEP),
|
||||
// CNVI_MFUART2_TXD - TODO
|
||||
PAD_CFG_GPI(GPP_H9, DN_20K, DEEP),
|
||||
// LAN_CLKREQ#
|
||||
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),
|
||||
// NC
|
||||
PAD_NC(GPP_H11, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_H12, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_H13, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_H14, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_H15, NONE),
|
||||
// HDMI_CTRLCLK
|
||||
PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1),
|
||||
// HDMI_CTRLDATA
|
||||
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
|
||||
// CPU_C10_GATE#
|
||||
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
|
||||
// CNVI_WAKE#
|
||||
PAD_NC(GPP_H19, NONE),
|
||||
// PM_CLKRUN#
|
||||
PAD_NC(GPP_H20, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_H21, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_H22, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_H23, NONE),
|
||||
// HDA_BITCLK
|
||||
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
|
||||
// HDA_SYNC
|
||||
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
|
||||
// HDA_SDOUT
|
||||
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
|
||||
// HDA_SDIN0
|
||||
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
|
||||
// AZ_RST#_R
|
||||
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
|
||||
// NC
|
||||
PAD_NC(GPP_R5, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_R6, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_R7, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_S0, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_S1, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_S2, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_S3, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_S4, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_S5, NONE),
|
||||
// GPPC_DMIC_CLK - TODO
|
||||
PAD_NC(GPP_S6, NONE),
|
||||
// GPPC_DMIC_DATA - TODO
|
||||
PAD_NC(GPP_S7, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_T2, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_T3, NONE),
|
||||
// DGPU_RST#_PCH - handled in bootblock.c
|
||||
// DGPU_PWR_EN - handled in bootblock.c
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
26
src/mainboard/system76/galp5/hda_verb.c
Normal file
26
src/mainboard/system76/galp5/hda_verb.c
Normal file
@ -0,0 +1,26 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC293 */
|
||||
0x10ec0293, /* Vendor ID */
|
||||
0x15584018, /* Subsystem ID */
|
||||
12, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x15584018),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x13, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x15, 0x02211020),
|
||||
AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x41748245),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
18
src/mainboard/system76/galp5/ramstage.c
Normal file
18
src/mainboard/system76/galp5/ramstage.c
Normal file
@ -0,0 +1,18 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <soc/ramstage.h>
|
||||
#include "gpio.h"
|
||||
|
||||
void mainboard_silicon_init_params(FSP_S_CONFIG *params) {
|
||||
// CPU RP Config
|
||||
params->CpuPcieRpAdvancedErrorReporting[0] = 0;
|
||||
params->CpuPcieRpLtrEnable[0] = 1;
|
||||
params->CpuPcieRpPtmEnabled[0] = 0;
|
||||
|
||||
// IOM config
|
||||
params->PchUsbOverCurrentEnable = 0;
|
||||
params->PortResetMessageEnable[5] = 1; // J_TYPEC2
|
||||
params->UsbTcPortEn = 1;
|
||||
|
||||
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
|
||||
}
|
||||
37
src/mainboard/system76/galp5/romstage.c
Normal file
37
src/mainboard/system76/galp5/romstage.c
Normal file
@ -0,0 +1,37 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <fsp/util.h>
|
||||
#include <soc/meminit.h>
|
||||
#include <soc/romstage.h>
|
||||
|
||||
static const struct mb_ddr4_cfg board_cfg = {
|
||||
// dq_map unused on DDR4
|
||||
// dqs_map unused on DDR4
|
||||
|
||||
// TGL-U does not support interleaved memory
|
||||
.dq_pins_interleaved = 0,
|
||||
|
||||
//TODO: can we use early command training?
|
||||
.ect = 0,
|
||||
};
|
||||
|
||||
static const struct spd_info spd = {
|
||||
.topology = SODIMM,
|
||||
.smbus_info[0] = {
|
||||
.addr_dimm0 = 0x50,
|
||||
},
|
||||
.smbus_info[1] = {
|
||||
.addr_dimm0 = 0x52,
|
||||
},
|
||||
};
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *mupd) {
|
||||
//TODO: Allow memory clocks higher than 2933 MHz
|
||||
mupd->FspmConfig.SaOcSupport = 1;
|
||||
//TODO: Set primary display to internal graphics
|
||||
mupd->FspmConfig.PrimaryDisplay = 0;
|
||||
|
||||
//TODO: what is this for?
|
||||
const bool half_populated = false;
|
||||
meminit_ddr4(&mupd->FspmConfig, &board_cfg, &spd, half_populated);
|
||||
}
|
||||
76
src/mainboard/system76/lemp10/Kconfig
Normal file
76
src/mainboard/system76/lemp10/Kconfig
Normal file
@ -0,0 +1,76 @@
|
||||
if BOARD_SYSTEM76_LEMP10
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS
|
||||
def_bool y
|
||||
select BOARD_ROMSIZE_KB_16384
|
||||
select DRIVERS_I2C_HID
|
||||
select DRIVERS_INTEL_PMC
|
||||
select DRIVERS_INTEL_USB4_RETIMER
|
||||
select EC_SYSTEM76_EC
|
||||
select EC_SYSTEM76_EC_BAT_THRESHOLDS
|
||||
select HAVE_ACPI_TABLES
|
||||
select HAVE_CMOS_DEFAULT
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_SMI_HANDLER
|
||||
select HAVE_SPD_IN_CBFS
|
||||
select INTEL_GMA_HAVE_VBT
|
||||
select INTEL_LPSS_UART_FOR_CONSOLE
|
||||
select MAINBOARD_HAS_LPC_TPM
|
||||
select MAINBOARD_HAS_TPM2
|
||||
select NO_UART_ON_SUPERIO
|
||||
select PCIEXP_HOTPLUG
|
||||
select SOC_INTEL_TIGERLAKE
|
||||
select SOC_INTEL_COMMON_BLOCK_HDA
|
||||
select SOC_INTEL_COMMON_BLOCK_HDA_VERB
|
||||
select SPD_READ_BY_WORD
|
||||
select SYSTEM_TYPE_LAPTOP
|
||||
select TPM_RDRESP_NEED_DELAY
|
||||
select USE_OPTION_TABLE
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default "system76/lemp10"
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "lemp10"
|
||||
|
||||
config MAINBOARD_SMBIOS_PRODUCT_NAME
|
||||
string
|
||||
default "Lemur Pro"
|
||||
|
||||
config MAINBOARD_VERSION
|
||||
string
|
||||
default "lemp10"
|
||||
|
||||
#TODO: subsystem IDs
|
||||
|
||||
config CBFS_SIZE
|
||||
hex
|
||||
default 0xA00000
|
||||
|
||||
config CONSOLE_POST
|
||||
bool
|
||||
default y
|
||||
|
||||
config DIMM_MAX
|
||||
int
|
||||
default 4 # Hack to make soc code work
|
||||
|
||||
config DIMM_SPD_SIZE
|
||||
int
|
||||
default 512
|
||||
|
||||
config MAX_CPUS
|
||||
int
|
||||
default 8
|
||||
|
||||
config POST_DEVICE
|
||||
bool
|
||||
default n
|
||||
|
||||
config UART_FOR_CONSOLE
|
||||
int
|
||||
default 2
|
||||
|
||||
endif
|
||||
2
src/mainboard/system76/lemp10/Kconfig.name
Normal file
2
src/mainboard/system76/lemp10/Kconfig.name
Normal file
@ -0,0 +1,2 @@
|
||||
config BOARD_SYSTEM76_LEMP10
|
||||
bool "lemp10"
|
||||
4
src/mainboard/system76/lemp10/Makefile.inc
Normal file
4
src/mainboard/system76/lemp10/Makefile.inc
Normal file
@ -0,0 +1,4 @@
|
||||
bootblock-y += bootblock.c
|
||||
ramstage-y += ramstage.c
|
||||
ramstage-y += hda_verb.c
|
||||
SPD_SOURCES = samsung-M471A1G44AB0-CWE
|
||||
30
src/mainboard/system76/lemp10/acpi/backlight.asl
Normal file
30
src/mainboard/system76/lemp10/acpi/backlight.asl
Normal file
@ -0,0 +1,30 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <drivers/intel/gma/acpi/gma.asl>
|
||||
|
||||
Scope (GFX0) {
|
||||
Name (BRIG, Package (22) {
|
||||
40, /* default AC */
|
||||
40, /* default Battery */
|
||||
5,
|
||||
10,
|
||||
15,
|
||||
20,
|
||||
25,
|
||||
30,
|
||||
35,
|
||||
40,
|
||||
45,
|
||||
50,
|
||||
55,
|
||||
60,
|
||||
65,
|
||||
70,
|
||||
75,
|
||||
80,
|
||||
85,
|
||||
90,
|
||||
95,
|
||||
100
|
||||
})
|
||||
}
|
||||
12
src/mainboard/system76/lemp10/acpi/mainboard.asl
Normal file
12
src/mainboard/system76/lemp10/acpi/mainboard.asl
Normal file
@ -0,0 +1,12 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#define EC_GPE_SCI 0x6E
|
||||
#define EC_GPE_SWI 0x6E
|
||||
#include <ec/system76/ec/acpi/ec.asl>
|
||||
|
||||
Scope (\_SB) {
|
||||
#include "sleep.asl"
|
||||
Scope (PCI0) {
|
||||
#include "backlight.asl"
|
||||
}
|
||||
}
|
||||
46
src/mainboard/system76/lemp10/acpi/sleep.asl
Normal file
46
src/mainboard/system76/lemp10/acpi/sleep.asl
Normal file
@ -0,0 +1,46 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <intelblocks/gpio.h>
|
||||
|
||||
Method (PGPM, 1, Serialized)
|
||||
{
|
||||
For (Local0 = 0, Local0 < 6, Local0++)
|
||||
{
|
||||
\_SB.PCI0.CGPM (Local0, Arg0)
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Method called from _PTS prior to system sleep state entry
|
||||
* Enables dynamic clock gating for all 5 GPIO communities
|
||||
*/
|
||||
Method (MPTS, 1, Serialized)
|
||||
{
|
||||
\_SB.PCI0.LPCB.EC0.PTS (Arg0)
|
||||
PGPM (MISCCFG_ENABLE_GPIO_PM_CONFIG)
|
||||
}
|
||||
|
||||
/*
|
||||
* Method called from _WAK prior to system sleep state wakeup
|
||||
* Disables dynamic clock gating for all 5 GPIO communities
|
||||
*/
|
||||
Method (MWAK, 1, Serialized)
|
||||
{
|
||||
PGPM (0)
|
||||
\_SB.PCI0.LPCB.EC0.WAK (Arg0)
|
||||
}
|
||||
|
||||
/*
|
||||
* S0ix Entry/Exit Notifications
|
||||
* Called from \_SB.PEPD._DSM
|
||||
*/
|
||||
Method (MS0X, 1, Serialized)
|
||||
{
|
||||
If (Arg0 == 1) {
|
||||
/* S0ix Entry */
|
||||
PGPM (MISCCFG_ENABLE_GPIO_PM_CONFIG)
|
||||
} Else {
|
||||
/* S0ix Exit */
|
||||
PGPM (0)
|
||||
}
|
||||
}
|
||||
8
src/mainboard/system76/lemp10/board_info.txt
Normal file
8
src/mainboard/system76/lemp10/board_info.txt
Normal file
@ -0,0 +1,8 @@
|
||||
Vendor name: System76
|
||||
Board name: lemp10
|
||||
Category: laptop
|
||||
Release year: 2020
|
||||
ROM package: SOIC-8
|
||||
ROM protocol: SPI
|
||||
ROM socketed: n
|
||||
Flashrom support: y
|
||||
9
src/mainboard/system76/lemp10/bootblock.c
Normal file
9
src/mainboard/system76/lemp10/bootblock.c
Normal file
@ -0,0 +1,9 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <bootblock_common.h>
|
||||
#include <gpio.h>
|
||||
#include "gpio.h"
|
||||
|
||||
void bootblock_mainboard_init(void) {
|
||||
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
|
||||
}
|
||||
2
src/mainboard/system76/lemp10/cmos.default
Normal file
2
src/mainboard/system76/lemp10/cmos.default
Normal file
@ -0,0 +1,2 @@
|
||||
boot_option=Fallback
|
||||
preserve_smmstore=0
|
||||
35
src/mainboard/system76/lemp10/cmos.layout
Normal file
35
src/mainboard/system76/lemp10/cmos.layout
Normal file
@ -0,0 +1,35 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
entries
|
||||
|
||||
0 384 r 0 reserved_memory
|
||||
|
||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||
384 1 e 2 boot_option
|
||||
388 4 h 0 reboot_counter
|
||||
|
||||
#395 4 e 3 debug_level
|
||||
408 1 h 1 preserve_smmstore
|
||||
984 16 h 0 check_sum
|
||||
|
||||
enumerations
|
||||
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
|
||||
2 0 Fallback
|
||||
2 1 Normal
|
||||
|
||||
3 0 Emergency
|
||||
3 1 Alert
|
||||
3 2 Critical
|
||||
3 3 Error
|
||||
3 4 Warning
|
||||
3 5 Notice
|
||||
3 6 Info
|
||||
3 7 Debug
|
||||
3 8 Spew
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 983 984
|
||||
329
src/mainboard/system76/lemp10/devicetree.cb
Normal file
329
src/mainboard/system76/lemp10/devicetree.cb
Normal file
@ -0,0 +1,329 @@
|
||||
chip soc/intel/tigerlake
|
||||
register "common_soc_config" = "{
|
||||
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
|
||||
// Touchpad I2C bus
|
||||
.i2c[0] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.rise_time_ns = 80,
|
||||
.fall_time_ns = 110,
|
||||
},
|
||||
}"
|
||||
|
||||
# ACPI (soc/intel/tigerlake/acpi.c)
|
||||
# Disable DPTF
|
||||
register "dptf_enable" = "0"
|
||||
|
||||
# Enable Enhanced Intel SpeedStep
|
||||
register "eist_enable" = "1"
|
||||
|
||||
# Enable s0ix, required for TGL-U
|
||||
register "s0ix_enable" = "1"
|
||||
|
||||
# CPU (soc/intel/tigerlake/cpu.c)
|
||||
# Power limits
|
||||
register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{
|
||||
// /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw
|
||||
.tdp_pl1_override = 20,
|
||||
// /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw
|
||||
.tdp_pl2_override = 30,
|
||||
}"
|
||||
register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{
|
||||
// /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw
|
||||
.tdp_pl1_override = 20,
|
||||
// /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw
|
||||
.tdp_pl2_override = 30,
|
||||
}"
|
||||
|
||||
# Finalize (soc/intel/tigerlake/finalize.c)
|
||||
# PM Timer Disabled, saves power
|
||||
register "PmTimerDisabled" = "1"
|
||||
|
||||
# FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c)
|
||||
# Enable C6 DRAM
|
||||
register "enable_c6dram" = "1"
|
||||
|
||||
# System Agent dynamic frequency support
|
||||
register "SaGv" = "SaGv_Enabled"
|
||||
|
||||
# FSP Silicon (soc/intel/tigerlake/fsp_params.c)
|
||||
# Acoustic settings
|
||||
register "AcousticNoiseMitigation" = "1"
|
||||
register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
|
||||
register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
|
||||
register "SlowSlewRate[VR_DOMAIN_SA]" = "SLEW_FAST_8"
|
||||
register "SlowSlewRate[VR_DOMAIN_VLCC]" = "SLEW_FAST_8"
|
||||
register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1"
|
||||
register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1"
|
||||
register "FastPkgCRampDisable[VR_DOMAIN_SA]" = "1"
|
||||
register "FastPkgCRampDisable[VR_DOMAIN_VLCC]" = "1"
|
||||
|
||||
# FIVR configuration
|
||||
# Read EXT_RAIL_CONFIG to determine bitmaps
|
||||
# sudo devmem2 0xfe0011b8
|
||||
# 0x0
|
||||
# Read EXT_V1P05_VR_CONFIG
|
||||
# sudo devmem2 0xfe0011c0
|
||||
# 0x1a42000
|
||||
# Read EXT_VNN_VR_CONFIG0
|
||||
# sudo devmem2 0xfe0011c4
|
||||
# 0x1a42000
|
||||
# TODO: v1p05 voltage and vnn icc max?
|
||||
register "ext_fivr_settings" = "{
|
||||
.configure_ext_fivr = 1,
|
||||
.v1p05_enable_bitmap = 0,
|
||||
.vnn_enable_bitmap = 0,
|
||||
.v1p05_supported_voltage_bitmap = 0,
|
||||
.vnn_supported_voltage_bitmap = 0,
|
||||
.v1p05_icc_max_ma = 500,
|
||||
.vnn_sx_voltage_mv = 1050,
|
||||
}"
|
||||
|
||||
# Read LPM_EN, make sure to invert the bits
|
||||
# sudo devmem2 0xfe001c78
|
||||
# 0x9
|
||||
register "LpmStateDisableMask" = "
|
||||
LPM_S0i2_1 |
|
||||
LPM_S0i2_2 |
|
||||
LPM_S0i3_1 |
|
||||
LPM_S0i3_2 |
|
||||
LPM_S0i3_3 |
|
||||
LPM_S0i3_4
|
||||
"
|
||||
|
||||
# Thermal
|
||||
# rdmsr --bitfield 31:24 --decimal 0x1A2
|
||||
register "tcc_offset" = "12"
|
||||
|
||||
# PM Util (soc/intel/tigerlake/pmutil.c)
|
||||
# GPE configuration
|
||||
# sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
|
||||
# TODO: 0x703
|
||||
register "pmc_gpe0_dw0" = "PMC_GPP_R"
|
||||
register "pmc_gpe0_dw1" = "PMC_GPP_B"
|
||||
register "pmc_gpe0_dw2" = "PMC_GPP_D"
|
||||
|
||||
# Actual device tree
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
||||
device domain 0 on
|
||||
#From CPU EDS(575683)
|
||||
device ref system_agent on end
|
||||
device ref igpu on
|
||||
# DDIA is eDP
|
||||
register "DdiPortAConfig" = "1"
|
||||
register "DdiPortAHpd" = "1"
|
||||
register "DdiPortADdc" = "0"
|
||||
|
||||
# DDIB is HDMI
|
||||
register "DdiPortBConfig" = "0"
|
||||
register "DdiPortBHpd" = "1"
|
||||
register "DdiPortBDdc" = "1"
|
||||
|
||||
register "gfx" = "GMA_STATIC_DISPLAYS(0)"
|
||||
end
|
||||
device ref dptf on
|
||||
register "Device4Enable" = "1"
|
||||
end
|
||||
device ref peg on
|
||||
# PCIe PEG0 x4, Clock 3 (SSD1)
|
||||
register "PcieClkSrcUsage[3]" = "0x40"
|
||||
register "PcieClkSrcClkReq[3]" = "3"
|
||||
#TODO
|
||||
# chip soc/intel/common/block/pcie/rtd3
|
||||
# register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C13)" # SSD1_PWR_DN#
|
||||
# register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C22)" # GPP_C12_RTD3 (labeled incorrectly)
|
||||
# #TODO: Support disable/enable CPU RP clock
|
||||
# register "srcclk_pin" = "-1"
|
||||
# device generic 0 on end
|
||||
# end
|
||||
|
||||
#TODO: Hybrid storage mode?
|
||||
register "HybridStorageMode" = "0"
|
||||
end
|
||||
device ref tbt_pcie_rp0 on end # J_TYPEC1
|
||||
device ref gna on end
|
||||
device ref north_xhci on # J_TYPEC1
|
||||
register "TcssXhciEn" = "1"
|
||||
chip drivers/usb/acpi
|
||||
device ref tcss_root_hub on
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 J_TYPEC1""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "group" = "ACPI_PLD_GROUP(1, 1)"
|
||||
device ref tcss_usb3_port1 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref tbt_dma0 on # J_TYPEC1
|
||||
chip drivers/intel/usb4/retimer
|
||||
register "power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A23)"
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
|
||||
# From PCH EDS(576591)
|
||||
device ref cnvi_bt on end
|
||||
device ref south_xhci on
|
||||
# USB2
|
||||
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # J_USB3_1
|
||||
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # J_USB3_2
|
||||
register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1
|
||||
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Camera
|
||||
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
|
||||
# USB3
|
||||
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB3_1
|
||||
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB3_2
|
||||
# ACPI
|
||||
chip drivers/usb/acpi
|
||||
device ref xhci_root_hub on
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 J_USB3_1""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "group" = "ACPI_PLD_GROUP(1, 2)"
|
||||
device ref usb2_port1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 J_USB3_2""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "group" = "ACPI_PLD_GROUP(2, 1)"
|
||||
device ref usb2_port2 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 J_TYPEC1""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "group" = "ACPI_PLD_GROUP(1, 1)"
|
||||
device ref usb2_port3 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Camera""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device ref usb2_port7 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Bluetooth""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device ref usb2_port10 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 J_USB3_1""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "group" = "ACPI_PLD_GROUP(1, 1)"
|
||||
device ref usb3_port1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 J_USB3_2""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "group" = "ACPI_PLD_GROUP(2, 1)"
|
||||
device ref usb3_port2 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref shared_ram on end
|
||||
device ref cnvi_wifi on
|
||||
chip drivers/wifi/generic
|
||||
register "wake" = "GPE0_PME_B0"
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref i2c0 on
|
||||
# Touchpad I2C bus
|
||||
register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""PNP0C50""
|
||||
register "generic.desc" = ""ELAN Touchpad""
|
||||
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B3)"
|
||||
register "generic.probed" = "1"
|
||||
register "hid_desc_reg_offset" = "0x01"
|
||||
device i2c 15 on end
|
||||
end
|
||||
end
|
||||
device ref i2c1 on
|
||||
#TODO: USB-PD?
|
||||
register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
|
||||
end
|
||||
device ref heci1 on
|
||||
#TODO Disable ME and HECI
|
||||
register "HeciEnabled" = "1"
|
||||
end
|
||||
device ref uart2 on
|
||||
# Debug console
|
||||
register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit"
|
||||
end
|
||||
device ref sata on
|
||||
# SATA1 (SSD2)
|
||||
register "SataPortsEnable[1]" = "1"
|
||||
register "SataPortsDevSlp[1]" = "1"
|
||||
register "SataPortsEnableDitoConfig[1]" = "1"
|
||||
register "SataSalpSupport" = "1"
|
||||
end
|
||||
device ref pcie_rp3 on
|
||||
# PCIe root port #3 x1, Clock 1 (WLAN)
|
||||
register "PcieRpEnable[2]" = "1"
|
||||
register "PcieRpLtrEnable[2]" = "1"
|
||||
register "PcieClkSrcUsage[1]" = "2"
|
||||
register "PcieClkSrcClkReq[1]" = "1"
|
||||
end
|
||||
device ref pcie_rp6 on
|
||||
# PCIe root port #6 x1, Clock 2 (CARD)
|
||||
register "PcieRpEnable[5]" = "1"
|
||||
register "PcieRpLtrEnable[5]" = "1"
|
||||
register "PcieClkSrcUsage[2]" = "5"
|
||||
register "PcieClkSrcClkReq[2]" = "2"
|
||||
end
|
||||
device ref pcie_rp9 on
|
||||
# PCIe root port #9 x4, Clock 0 (SSD2)
|
||||
register "PcieRpEnable[8]" = "1"
|
||||
register "PcieRpLtrEnable[8]" = "1"
|
||||
register "PcieClkSrcUsage[0]" = "8"
|
||||
register "PcieClkSrcClkReq[0]" = "0"
|
||||
chip soc/intel/common/block/pcie/rtd3
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD2_PWR_DN#
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D9)" # GPP_D13_RTD3 (labeled incorrectly)
|
||||
register "srcclk_pin" = "0"
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref pch_espi on
|
||||
# LPC configuration from lspci -s 1f.0 -xxx
|
||||
# Address 0x84: Decode 0x80 - 0x8F (Port 80)
|
||||
register "gen1_dec" = "0x000c0081"
|
||||
# Address 0x88: Decode 0x68 - 0x6F (PMC)
|
||||
register "gen2_dec" = "0x00040069"
|
||||
# Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command)
|
||||
register "gen3_dec" = "0x00fc0E01"
|
||||
# Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug)
|
||||
register "gen4_dec" = "0x00fc0F01"
|
||||
# LPC TPM
|
||||
chip drivers/pc80/tpm
|
||||
device pnp 0c31.0 on end
|
||||
end
|
||||
end
|
||||
device ref p2sb on end
|
||||
device ref pmc hidden
|
||||
# The pmc_mux chip driver is a placeholder for the
|
||||
# PMC.MUX device in the ACPI hierarchy.
|
||||
chip drivers/intel/pmc_mux
|
||||
device generic 0 on
|
||||
chip drivers/intel/pmc_mux/conn
|
||||
# J_TYPEC1
|
||||
register "usb2_port_number" = "3"
|
||||
register "usb3_port_number" = "1"
|
||||
# SBU & HSL follow CC
|
||||
device generic 0 alias conn0 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref hda on
|
||||
register "PchHdaAudioLinkHdaEnable" = "1"
|
||||
end
|
||||
device ref smbus on
|
||||
register "SmbusEnable" = "1"
|
||||
end
|
||||
device ref fast_spi on end
|
||||
end
|
||||
end
|
||||
41
src/mainboard/system76/lemp10/dsdt.asl
Normal file
41
src/mainboard/system76/lemp10/dsdt.asl
Normal file
@ -0,0 +1,41 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
//TODO: cleaner solution for ACPI brightness
|
||||
#define SYSTEM76_ACPI_NO_GFX0
|
||||
|
||||
#include <acpi/acpi.h>
|
||||
|
||||
DefinitionBlock(
|
||||
"dsdt.aml",
|
||||
"DSDT",
|
||||
ACPI_DSDT_REV_2,
|
||||
OEM_ID,
|
||||
ACPI_TABLE_CREATOR,
|
||||
0x20110725 // OEM revision
|
||||
)
|
||||
{
|
||||
#include <soc/intel/common/block/acpi/acpi/platform.asl>
|
||||
|
||||
// global NVS and variables
|
||||
#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
|
||||
|
||||
// CPU
|
||||
#include <cpu/intel/common/acpi/cpu.asl>
|
||||
|
||||
Scope (\_SB) {
|
||||
Device (PCI0)
|
||||
{
|
||||
#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
|
||||
#include <soc/intel/tigerlake/acpi/southbridge.asl>
|
||||
#include <soc/intel/tigerlake/acpi/tcss.asl>
|
||||
}
|
||||
}
|
||||
|
||||
Scope (\_SB.PCI0.LPCB) {
|
||||
#include <drivers/pc80/pc/ps2_controller.asl>
|
||||
}
|
||||
|
||||
#include <southbridge/intel/common/acpi/sleepstates.asl>
|
||||
|
||||
#include "acpi/mainboard.asl"
|
||||
}
|
||||
417
src/mainboard/system76/lemp10/gpio.h
Normal file
417
src/mainboard/system76/lemp10/gpio.h
Normal file
@ -0,0 +1,417 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#ifndef __ACPI__
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
/* Pad configuration in romstage. */
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
// UART2_RXD
|
||||
PAD_CFG_NF(GPP_C20, UP_20K, DEEP, NF1),
|
||||
// UART2_TXD
|
||||
PAD_CFG_NF(GPP_C21, UP_20K, DEEP, NF1),
|
||||
};
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
// PM_BATLOW#
|
||||
PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
|
||||
// AC_PRESENT
|
||||
PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPD2, NONE, PWROK),
|
||||
// PWR_BTN#
|
||||
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
|
||||
// SUSB#_PCH
|
||||
PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
|
||||
// SUSC#_PCH
|
||||
PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
|
||||
// SLP_A# - test point
|
||||
PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
|
||||
// GPD7_REST
|
||||
PAD_CFG_TERM_GPO(GPD7, 1, NONE, PWROK),
|
||||
// SUS_CLK
|
||||
PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
|
||||
// GPD9_RTD3
|
||||
PAD_CFG_TERM_GPO(GPD9, 0, NONE, PWROK),
|
||||
// SLP_S5# - test point
|
||||
PAD_CFG_NF(GPD10, UP_20K, DEEP, NF1),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPD11, UP_20K, DEEP),
|
||||
// ESPI_IO_0
|
||||
PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1),
|
||||
// ESPI_IO_1
|
||||
PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
|
||||
// ESPI_IO_2
|
||||
PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
|
||||
// ESPI_IO_3
|
||||
PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
|
||||
// ESPI_CS_N
|
||||
PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
|
||||
// ESPI_CLK
|
||||
PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1),
|
||||
// ESPI_RESET_N
|
||||
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
|
||||
// NC
|
||||
PAD_NC(GPP_A7, NONE),
|
||||
// CNVI_RST#
|
||||
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF2),
|
||||
// CNVI_CLKREQ
|
||||
PAD_CFG_NF(GPP_A9, NONE, DEEP, NF3),
|
||||
// GPPC_DMIC_DATA
|
||||
PAD_NC(GPP_A10, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_A11, NONE),
|
||||
// SATAGP1
|
||||
PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
|
||||
// PCH_BT_EN
|
||||
PAD_CFG_TERM_GPO(GPP_A13, 1, NONE, PLTRST),
|
||||
// GPPC_DMIC_CLK
|
||||
PAD_NC(GPP_A14, NONE),
|
||||
// USB_OC2#
|
||||
PAD_NC(GPP_A15, NONE),
|
||||
// USB_OC3#
|
||||
PAD_NC(GPP_A16, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_A17, NONE),
|
||||
// HDMI_HPD
|
||||
PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
|
||||
// NC
|
||||
PAD_NC(GPP_A19, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_A20, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_A21, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_A22, NONE),
|
||||
// TC_RETIMER_FORCE_PWR
|
||||
PAD_CFG_TERM_GPO(GPP_A23, 0, NONE, PLTRST),
|
||||
// VCCIN_AUX_VID0
|
||||
PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
|
||||
// VCCIN_AUX_VID1
|
||||
PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
|
||||
// VRALERT#
|
||||
PAD_CFG_GPI(GPP_B2, UP_20K, DEEP),
|
||||
// GPP_B3 - touchpad interrupt
|
||||
PAD_CFG_GPI_INT(GPP_B3, NONE, PLTRST, LEVEL),
|
||||
// NC
|
||||
PAD_NC(GPP_B4, NONE),
|
||||
// PCH_FLASH_I2C_SDA - test point
|
||||
PAD_NC(GPP_B5, NONE),
|
||||
// PCH_FLASH_I2C_SCL - test point
|
||||
PAD_NC(GPP_B6, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_B7, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_B8, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_B9, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_B10, NONE),
|
||||
// TBTA_I2C_INT
|
||||
PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1),
|
||||
// SLP_S0#
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
// PLT_RST#
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
// PCH_SPKR
|
||||
PAD_CFG_TERM_GPO(GPP_B14, 0, NONE, DEEP),
|
||||
// NC
|
||||
PAD_NC(GPP_B15, NONE),
|
||||
// PCH_GPP_B16 - test point
|
||||
PAD_NC(GPP_B16, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_B17, NONE),
|
||||
// PCH_GPP_B18 - No reboot strap
|
||||
PAD_NC(GPP_B18, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_B19, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_B20, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_B21, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_B22, NONE),
|
||||
// GPP_B23
|
||||
PAD_CFG_TERM_GPO(GPP_B23, 0, NONE, DEEP),
|
||||
// SMB_CLK
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
// SMB_DATA
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
// PCH_GPP_C2 - ME TLS strap
|
||||
PAD_CFG_TERM_GPO(GPP_C2, 1, NONE, DEEP),
|
||||
// SML0_CLK
|
||||
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
|
||||
// SML0_DATA
|
||||
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
|
||||
// PCH_GPP_C5 - boot strap bit 0
|
||||
PAD_NC(GPP_C5, NONE),
|
||||
// TBT_I2C_SCL
|
||||
PAD_CFG_NF(GPP_C6, NONE, PWROK, NF1),
|
||||
// TBT_I2C_SDA
|
||||
PAD_CFG_NF(GPP_C7, NONE, PWROK, NF1),
|
||||
// NC
|
||||
PAD_NC(GPP_C8, NONE),
|
||||
// TPM_PIRQ#
|
||||
_PAD_CFG_STRUCT(GPP_C9, 0x40100100, 0x3000),
|
||||
// NC
|
||||
PAD_NC(GPP_C10, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_C11, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_C12, NONE),
|
||||
// SSD1_PWR_DN#
|
||||
PAD_CFG_TERM_GPO(GPP_C13, 1, NONE, PLTRST),
|
||||
// NC
|
||||
PAD_NC(GPP_C14, DN_20K),
|
||||
// NC
|
||||
PAD_NC(GPP_C15, NONE),
|
||||
// T_SDA
|
||||
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
|
||||
// T_SCL
|
||||
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
|
||||
// PCH_I2C_SDA
|
||||
PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
|
||||
// PCH_I2C_SCL
|
||||
PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
|
||||
// UART2_RXD
|
||||
PAD_CFG_NF(GPP_C20, UP_20K, DEEP, NF1),
|
||||
// UART2_TXD
|
||||
PAD_CFG_NF(GPP_C21, UP_20K, DEEP, NF1),
|
||||
// GPP_C12_RTD3
|
||||
PAD_CFG_TERM_GPO(GPP_C22, 1, NONE, PLTRST),
|
||||
// PCH_GPP_C23
|
||||
_PAD_CFG_STRUCT(GPP_C23, 0x40880100, 0x0000),
|
||||
// SB_BLON
|
||||
PAD_CFG_TERM_GPO(GPP_D0, 1, NONE, DEEP),
|
||||
// DDR_TYPE_D1
|
||||
PAD_CFG_GPI(GPP_D1, NONE, DEEP),
|
||||
// LEDKB_DET#
|
||||
PAD_CFG_GPI(GPP_D2, DN_20K, DEEP),
|
||||
// BOARD_ID
|
||||
PAD_CFG_GPI(GPP_D3, DN_20K, DEEP),
|
||||
// NC
|
||||
PAD_NC(GPP_D4, NONE),
|
||||
// SSD1_CLKREQ#
|
||||
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
|
||||
// WLAN_CLKREQ#
|
||||
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
|
||||
// CARD_CLKREQ#
|
||||
PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
|
||||
// SSD2_CLKREQ#
|
||||
PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
|
||||
// GPP_D13_RTD3 - named incorrectly in schematic
|
||||
PAD_CFG_TERM_GPO(GPP_D9, 1, NONE, PLTRST),
|
||||
// GPP_D10 - I2C / TBT_LSX2 pin voltage (L=1.8V, H=3.3V)
|
||||
PAD_NC(GPP_D10, NONE),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_D11, DN_20K, DEEP),
|
||||
// GPP_D12 - I2C / TBT_LSX3 pin voltage (L=1.8V, H=3.3V)
|
||||
PAD_NC(GPP_D12, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_D13, NONE),
|
||||
// SSD2_PWR_DN#
|
||||
PAD_CFG_TERM_GPO(GPP_D14, 1, NONE, PLTRST),
|
||||
// NC
|
||||
PAD_NC(GPP_D15, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_D16, NONE),
|
||||
// DDR_TYPE_D17
|
||||
PAD_CFG_GPI(GPP_D17, NONE, DEEP),
|
||||
// DDR_TYPE_D18
|
||||
PAD_CFG_GPI(GPP_D18, NONE, DEEP),
|
||||
// NC
|
||||
PAD_NC(GPP_D19, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_E0, NONE),
|
||||
// ROM_I2C_EN
|
||||
PAD_CFG_TERM_GPO(GPP_E1, 0, NONE, PLTRST),
|
||||
// NC
|
||||
PAD_NC(GPP_E2, NONE),
|
||||
// SB_KBCRST#
|
||||
PAD_CFG_GPI(GPP_E3, DN_20K, DEEP),
|
||||
// DEVSLP0
|
||||
PAD_NC(GPP_E4, NONE),
|
||||
// DEVSLP1
|
||||
PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
|
||||
// PCH_GPP_E6 - reserved strap
|
||||
PAD_NC(GPP_E6, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_E7, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_E8, NONE),
|
||||
// USB_OC0#
|
||||
PAD_NC(GPP_E9, NONE),
|
||||
// PCH_GPP_E10 - THC0_SPI1 chip select
|
||||
PAD_NC(GPP_E10, NONE),
|
||||
// PCH_GPP_E11 - THC0_SPI1 clock
|
||||
PAD_NC(GPP_E11, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_E12, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_E13, NONE),
|
||||
// EDP_HPD
|
||||
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
|
||||
// SCI#
|
||||
PAD_CFG_GPI(GPP_E15, DN_20K, DEEP),
|
||||
// SMI#
|
||||
_PAD_CFG_STRUCT(GPP_E16, 0x82840100, 0x0000),
|
||||
// NC
|
||||
PAD_NC(GPP_E17, NONE),
|
||||
// TBT_LSX0_TXD - programmed by FSP, see Intel document 617016
|
||||
PAD_NC(GPP_E18, NONE),
|
||||
// TBT_LSX0_RXD - programmed by FSP, see Intel document 617016
|
||||
PAD_NC(GPP_E19, NONE),
|
||||
// SWI#
|
||||
_PAD_CFG_STRUCT(GPP_E20, 0x40880100, 0x0000),
|
||||
// GPP_E21 - DDP2 I2C / TBT_LSX1 pin voltage (L=1.8V, H=3.3V)
|
||||
PAD_NC(GPP_E21, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_E22, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_E23, NONE),
|
||||
// CNVI_BRI_DT
|
||||
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
|
||||
// CNVI_BRI_RSP
|
||||
PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
|
||||
// CNVI_RGI_DT
|
||||
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
|
||||
// CNVI_RGI_RSP
|
||||
PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
|
||||
// NC
|
||||
PAD_NC(GPP_F4, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_F5, NONE),
|
||||
// CNVI_GNSS_PA_BLANKING
|
||||
PAD_NC(GPP_F6, NONE),
|
||||
// GPP_F7 - reserved strap
|
||||
PAD_NC(GPP_F7, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_F8, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_F9, NONE),
|
||||
// GPP_F10 - reserved strap
|
||||
PAD_NC(GPP_F10, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_F11, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_F12, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_F13, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_F14, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_F15, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_F16, NONE),
|
||||
// TPM_DET#
|
||||
PAD_CFG_GPI(GPP_F17, NONE, PLTRST),
|
||||
// NC
|
||||
PAD_NC(GPP_F18, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_F19, NONE),
|
||||
// EXT_PWR_GATE#
|
||||
PAD_NC(GPP_F20, NONE),
|
||||
// EXT_PWR_GATE2#
|
||||
PAD_CFG_GPI(GPP_F21, DN_20K, DEEP),
|
||||
// VNN_CTRL
|
||||
PAD_NC(GPP_F22, NONE),
|
||||
// V1P05_CTRL
|
||||
PAD_NC(GPP_F23, NONE),
|
||||
// GPP_H0 - boot strap bit 1
|
||||
PAD_NC(GPP_H0, DN_20K),
|
||||
// GPP_H1 - boot strap bit 2
|
||||
PAD_NC(GPP_H1, DN_20K),
|
||||
// GPP_H2 - boot strap bit 3
|
||||
PAD_NC(GPP_H2, DN_20K),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_H3, DN_20K, DEEP),
|
||||
// NC
|
||||
PAD_NC(GPP_H4, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_H5, NONE),
|
||||
// test point
|
||||
PAD_CFG_GPI(GPP_H6, NONE, DEEP),
|
||||
// test point
|
||||
PAD_NC(GPP_H7, NONE),
|
||||
// CNVI_MFUART2_RXD
|
||||
PAD_CFG_GPI(GPP_H8, DN_20K, DEEP),
|
||||
// CNVI_MFUART2_TXD
|
||||
PAD_CFG_GPI(GPP_H9, DN_20K, DEEP),
|
||||
// NC
|
||||
PAD_NC(GPP_H10, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_H11, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_H12, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_H13, NONE),
|
||||
// G_INT1
|
||||
PAD_NC(GPP_H14, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_H15, NONE),
|
||||
// HDMI_CTRLCLK
|
||||
PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1),
|
||||
// HDMI_CTRLDATA
|
||||
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
|
||||
// CPU_C10_GATE#
|
||||
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
|
||||
// CNVI_WAKE#
|
||||
PAD_NC(GPP_H19, NONE),
|
||||
// PM_CLKRUN#
|
||||
PAD_NC(GPP_H20, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_H21, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_H22, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_H23, NONE),
|
||||
// HDA_BITCLK
|
||||
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
|
||||
// HDA_SYNC
|
||||
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
|
||||
// HDA_SDOUT
|
||||
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
|
||||
// HDA_SDIN0
|
||||
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
|
||||
// AZ_RST#_R
|
||||
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
|
||||
// NC
|
||||
PAD_NC(GPP_R5, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_R6, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_R7, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_S0, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_S1, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_S2, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_S3, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_S4, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_S5, NONE),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_S6, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_S7, NONE, DEEP),
|
||||
// NC
|
||||
PAD_NC(GPP_T2, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_T3, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_U4, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_U5, NONE),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
26
src/mainboard/system76/lemp10/hda_verb.c
Normal file
26
src/mainboard/system76/lemp10/hda_verb.c
Normal file
@ -0,0 +1,26 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC293 */
|
||||
0x10ec0293, /* Vendor ID */
|
||||
0x155814a1, /* Subsystem ID */
|
||||
12, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x155814a1),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x13, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x15, 0x02211020),
|
||||
AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x41748245),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
18
src/mainboard/system76/lemp10/ramstage.c
Normal file
18
src/mainboard/system76/lemp10/ramstage.c
Normal file
@ -0,0 +1,18 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <soc/ramstage.h>
|
||||
#include "gpio.h"
|
||||
|
||||
void mainboard_silicon_init_params(FSP_S_CONFIG *params) {
|
||||
// CPU RP Config
|
||||
params->CpuPcieRpAdvancedErrorReporting[0] = 0;
|
||||
params->CpuPcieRpLtrEnable[0] = 1;
|
||||
params->CpuPcieRpPtmEnabled[0] = 0;
|
||||
|
||||
// IOM config
|
||||
params->PchUsbOverCurrentEnable = 0;
|
||||
params->PortResetMessageEnable[2] = 1; // J_TYPEC1
|
||||
params->UsbTcPortEn = 1;
|
||||
|
||||
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
|
||||
}
|
||||
34
src/mainboard/system76/lemp10/romstage.c
Normal file
34
src/mainboard/system76/lemp10/romstage.c
Normal file
@ -0,0 +1,34 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <fsp/util.h>
|
||||
#include <soc/meminit.h>
|
||||
#include <soc/romstage.h>
|
||||
|
||||
static const struct mb_ddr4_cfg board_cfg = {
|
||||
// dq_map unused on DDR4
|
||||
// dqs_map unused on DDR4
|
||||
|
||||
// TGL-U does not support interleaved memory
|
||||
.dq_pins_interleaved = 0,
|
||||
|
||||
//TODO: can we use early command training?
|
||||
.ect = 0,
|
||||
};
|
||||
|
||||
static const struct spd_info spd = {
|
||||
.topology = MIXED,
|
||||
.md_spd_loc = SPD_CBFS,
|
||||
.cbfs_index = 0,
|
||||
.smbus_info[1] = {
|
||||
.addr_dimm0 = 0x52,
|
||||
},
|
||||
};
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *mupd) {
|
||||
//TODO: Allow memory clocks higher than 2933 MHz
|
||||
mupd->FspmConfig.SaOcSupport = 1;
|
||||
|
||||
//TODO: what is this for?
|
||||
const bool half_populated = false;
|
||||
meminit_ddr4(&mupd->FspmConfig, &board_cfg, &spd, half_populated);
|
||||
}
|
||||
@ -0,0 +1,33 @@
|
||||
# Samsung M471A1G44AB0-CWE
|
||||
23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00
|
||||
00 00 05 0D F8 FF 01 00 6E 6E 6E 11 00 6E F0 0A
|
||||
20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35
|
||||
16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 E8 F5
|
||||
0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
80 CE 00 00 00 00 00 00 00 4D 34 37 31 41 31 47
|
||||
34 34 41 42 30 2D 43 57 45 20 20 20 20 00 80 CE
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
@ -8,6 +8,8 @@ config BOARD_SPECIFIC_OPTIONS
|
||||
select EC_SYSTEM76_EC_BAT_THRESHOLDS
|
||||
select HAVE_ACPI_RESUME
|
||||
select HAVE_ACPI_TABLES
|
||||
select HAVE_CMOS_DEFAULT
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_SMI_HANDLER
|
||||
select HAVE_SPD_IN_CBFS
|
||||
select INTEL_GMA_HAVE_VBT
|
||||
@ -20,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS
|
||||
select SPD_READ_BY_WORD
|
||||
select SYSTEM_TYPE_LAPTOP
|
||||
select TPM_RDRESP_NEED_DELAY
|
||||
select USE_OPTION_TABLE
|
||||
select USE_LEGACY_8254_TIMER # Fix failure to boot GRUB
|
||||
|
||||
config MAINBOARD_DIR
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user