soc/intel: Use common romstage code

This provides stack guards with checking and common
entry into postcar.

The code in cpu/intel/car/romstage.c is candidate
for becoming architectural so function prototype
is moved to <arch/romstage.h>.

Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/northbridge/intel/e7505/memmap.c

@@ -18,7 +18,6 @@
 #include <arch/romstage.h>
 #include <cbmem.h>
 #include <console/console.h>
-#include <cpu/intel/romstage.h>
 #include <cpu/x86/mtrr.h>
 #include <program_loading.h>
 #include "e7505.h"

src/northbridge/intel/gm45/memmap.c

@@ -22,7 +22,6 @@
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <console/console.h>
-#include <cpu/intel/romstage.h>
 #include <cpu/x86/mtrr.h>
 #include <cbmem.h>
 #include <program_loading.h>

src/northbridge/intel/gm45/romstage.c

@@ -21,7 +21,7 @@
 #include <device/pci_ops.h>
 #include <arch/acpi.h>
 #include <cpu/x86/lapic.h>
-#include <cpu/intel/romstage.h>
+#include <arch/romstage.h>
 #include <northbridge/intel/gm45/gm45.h>
 #include <southbridge/intel/i82801ix/i82801ix.h>
 #include <southbridge/intel/common/gpio.h>

src/northbridge/intel/haswell/memmap.c

@@ -18,10 +18,10 @@
 
 #include <arch/romstage.h>
 #include <console/console.h>
+#include <commonlib/helpers.h>
 #include <cpu/x86/mtrr.h>
 #include <device/pci_ops.h>
 #include <cbmem.h>
-#include <cpu/intel/romstage.h>
 #include <stage_cache.h>
 #include "haswell.h"
 

src/northbridge/intel/i440bx/memmap.c

@@ -20,7 +20,6 @@
 #include <cbmem.h>
 #include <console/console.h>
 #include <commonlib/helpers.h>
-#include <cpu/intel/romstage.h>
 #include <cpu/x86/mtrr.h>
 #include <program_loading.h>
 #include "i440bx.h"

src/northbridge/intel/i945/memmap.c

@@ -21,7 +21,6 @@
 #include <cbmem.h>
 #include "i945.h"
 #include <console/console.h>
-#include <cpu/intel/romstage.h>
 #include <cpu/x86/mtrr.h>
 #include <program_loading.h>
 #include <cpu/intel/smm_reloc.h>

src/northbridge/intel/nehalem/memmap.c

@@ -20,7 +20,6 @@
 #include <device/pci_ops.h>
 #include <cbmem.h>
 #include <console/console.h>
-#include <cpu/intel/romstage.h>
 #include <cpu/x86/mtrr.h>
 #include <program_loading.h>
 #include <stage_cache.h>

src/northbridge/intel/pineview/memmap.c

@@ -24,7 +24,6 @@
 #include <cbmem.h>
 #include <northbridge/intel/pineview/pineview.h>
 #include <cpu/x86/mtrr.h>
-#include <cpu/intel/romstage.h>
 #include <cpu/intel/smm_reloc.h>
 #include <stdint.h>
 #include <stage_cache.h>

src/northbridge/intel/pineview/romstage.c

@@ -26,7 +26,7 @@
 #include <southbridge/intel/i82801gx/i82801gx.h>
 #include <southbridge/intel/common/gpio.h>
 #include <southbridge/intel/common/pmclib.h>
-#include <cpu/intel/romstage.h>
+#include <arch/romstage.h>
 #include <cpu/x86/lapic.h>
 #include "raminit.h"
 #include "pineview.h"

src/northbridge/intel/sandybridge/memmap.c

@@ -19,7 +19,6 @@
 #include <device/pci_ops.h>
 #include <cbmem.h>
 #include <console/console.h>
-#include <cpu/intel/romstage.h>
 #include <cpu/intel/smm_reloc.h>
 #include <cpu/x86/mtrr.h>
 #include <program_loading.h>

src/northbridge/intel/sandybridge/romstage.c

@@ -22,7 +22,7 @@
 #include <cpu/x86/lapic.h>
 #include <timestamp.h>
 #include "sandybridge.h"
-#include <cpu/intel/romstage.h>
+#include <arch/romstage.h>
 #include <device/pci_def.h>
 #include <device/device.h>
 #include <northbridge/intel/sandybridge/chip.h>

src/northbridge/intel/x4x/memmap.c

@@ -24,7 +24,6 @@
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <console/console.h>
-#include <cpu/intel/romstage.h>
 #include <cpu/x86/mtrr.h>
 #include <northbridge/intel/x4x/x4x.h>
 #include <program_loading.h>