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Add addw2

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Change-Id: I773fc5561857591da12c31f0f7be9f74cc98a239
This commit is contained in:
Jeremy Soller
2020-05-26 14:28:05 -06:00
committed by Jeremy Soller
parent 5b18ffb566
commit cde1985ec3
25 changed files with 1977 additions and 0 deletions
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92
src/mainboard/system76/addw2/Kconfig Normal file
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if BOARD_SYSTEM76_ADDW2
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_16384
select DRIVERS_I2C_HID
select EC_ACPI
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select HAVE_SMI_HANDLER
select INTEL_GMA_HAVE_VBT
select INTEL_LPSS_UART_FOR_CONSOLE
select MAINBOARD_HAS_LPC_TPM
select MAINBOARD_HAS_TPM2
select NO_UART_ON_SUPERIO
select SOC_INTEL_CANNONLAKE_PCH_H
select SOC_INTEL_COMETLAKE
select SOC_INTEL_COMMON_BLOCK_HDA
select SOC_INTEL_COMMON_BLOCK_HDA_VERB
select SPD_READ_BY_WORD
select SYSTEM_TYPE_LAPTOP
select USE_LEGACY_8254_TIMER # Fix failure to boot GRUB
config MAINBOARD_DIR
string
default system76/addw2
config MAINBOARD_PART_NUMBER
string
default "addw2"
config MAINBOARD_SMBIOS_PRODUCT_NAME
string
default "Adder WS"
config MAINBOARD_VERSION
string
default "addw2"
config CBFS_SIZE
hex
default 0xA00000
config SUBSYSTEM_VENDOR_ID
hex
default 0x1558
config SUBSYSTEM_DEVICE_ID
hex
default 0x65e1
config CONSOLE_POST
bool
default y
config ONBOARD_VGA_IS_PRIMARY
bool
default y
config UART_FOR_CONSOLE
int
default 2
config MAX_CPUS
int
default 16
config DIMM_MAX
int
default 2
config DIMM_SPD_SIZE
int
default 512
config VGA_BIOS_FILE
string
default "pci8086,9bc4.rom"
config VGA_BIOS_ID
string
default "8086,9bc4"
config FSP_M_XIP
bool
default y
config POST_DEVICE
bool
default n
endif

2
src/mainboard/system76/addw2/Kconfig.name Normal file
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config BOARD_SYSTEM76_ADDW2
bool "addw2"

3
src/mainboard/system76/addw2/Makefile.inc Normal file
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bootblock-y += bootblock.c
ramstage-y += ramstage.c
ramstage-y += hda_verb.c

22
src/mainboard/system76/addw2/acpi/ac.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
Device (AC)
{
Name (_HID, "ACPI0003" /* Power Source Device */) // _HID: Hardware ID
Name (_PCL, Package (0x01) // _PCL: Power Consumer List
{
_SB
})
Name (ACFG, One)
Method (_PSR, 0, NotSerialized) // _PSR: Power Source
{
Return (ACFG)
}
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
}

170
src/mainboard/system76/addw2/acpi/battery.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
Device (BAT0)
{
Name (_HID, EisaId ("PNP0C0A") /* Control Method Battery */) // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
Name (_PCL, Package (0x01) // _PCL: Power Consumer List
{
_SB
})
Name (BFCC, Zero)
Method (_STA, 0, NotSerialized) // _STA: Status
{
If (^^PCI0.LPCB.EC0.ECOK)
{
If (^^PCI0.LPCB.EC0.BAT0)
{
Return (0x1F)
}
Else
{
Return (0x0F)
}
}
Else
{
Return (0x0F)
}
}
Name (PBIF, Package (0x0D)
{
One,
0xFFFFFFFF,
0xFFFFFFFF,
One,
0x39D0,
Zero,
Zero,
0x40,
0x40,
"BAT",
"0001",
"LION",
"Notebook"
})
Method (IVBI, 0, NotSerialized)
{
PBIF [One] = 0xFFFFFFFF
PBIF [0x02] = 0xFFFFFFFF
PBIF [0x04] = 0xFFFFFFFF
PBIF [0x09] = " "
PBIF [0x0A] = " "
PBIF [0x0B] = " "
PBIF [0x0C] = " "
BFCC = Zero
}
Method (UPBI, 0, NotSerialized)
{
If (^^PCI0.LPCB.EC0.BAT0)
{
Local0 = (^^PCI0.LPCB.EC0.BDC0 & 0xFFFF)
PBIF [One] = Local0
Local0 = (^^PCI0.LPCB.EC0.BFC0 & 0xFFFF)
PBIF [0x02] = Local0
BFCC = Local0
Local0 = (^^PCI0.LPCB.EC0.BDV0 & 0xFFFF)
PBIF [0x04] = Local0
Local0 = (^^PCI0.LPCB.EC0.BCW0 & 0xFFFF)
PBIF [0x05] = Local0
Local0 = (^^PCI0.LPCB.EC0.BCL0 & 0xFFFF)
PBIF [0x06] = Local0
PBIF [0x09] = "BAT"
PBIF [0x0A] = "0001"
PBIF [0x0B] = "LION"
PBIF [0x0C] = "Notebook"
}
Else
{
IVBI ()
}
}
Method (_BIF, 0, NotSerialized) // _BIF: Battery Information
{
If (^^PCI0.LPCB.EC0.ECOK)
{
UPBI ()
}
Else
{
IVBI ()
}
Return (PBIF) /* \_SB_.BAT0.PBIF */
}
Name (PBST, Package (0x04)
{
Zero,
0xFFFFFFFF,
0xFFFFFFFF,
0x3D90
})
Method (IVBS, 0, NotSerialized)
{
PBST [Zero] = Zero
PBST [One] = 0xFFFFFFFF
PBST [0x02] = 0xFFFFFFFF
PBST [0x03] = 0x2710
}
Method (UPBS, 0, NotSerialized)
{
If (^^PCI0.LPCB.EC0.BAT0)
{
Local0 = Zero
Local1 = Zero
If (^^AC.ACFG)
{
If (((^^PCI0.LPCB.EC0.BST0 & 0x02) == 0x02))
{
Local0 |= 0x02
Local1 = (^^PCI0.LPCB.EC0.BPR0 & 0xFFFF)
}
}
Else
{
Local0 |= One
Local1 = (^^PCI0.LPCB.EC0.BPR0 & 0xFFFF)
}
Local7 = (Local1 & 0x8000)
If ((Local7 == 0x8000))
{
Local1 ^= 0xFFFF
}
Local2 = (^^PCI0.LPCB.EC0.BRC0 & 0xFFFF)
Local3 = (^^PCI0.LPCB.EC0.BPV0 & 0xFFFF)
PBST [Zero] = Local0
PBST [One] = Local1
PBST [0x02] = Local2
PBST [0x03] = Local3
If ((BFCC != ^^PCI0.LPCB.EC0.BFC0))
{
Notify (BAT0, 0x81) // Information Change
}
}
Else
{
IVBS ()
}
}
Method (_BST, 0, NotSerialized) // _BST: Battery Status
{
If (^^PCI0.LPCB.EC0.ECOK)
{
UPBS ()
}
Else
{
IVBS ()
}
Return (PBST) /* \_SB_.BAT0.PBST */
}
}

13
src/mainboard/system76/addw2/acpi/buttons.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
Device (PWRB)
{
Name (_HID, EisaId ("PNP0C0C"))
Name (_PRW, Package () { 0x06 /* GPP_K6 */, 3 })
}
Device (SLPB)
{
Name (_HID, EisaId ("PNP0C0E"))
Name (_PRW, Package () { 0x06 /* GPP_K6 */, 3 })
}

68
src/mainboard/system76/addw2/acpi/dgpu.asl Normal file
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// From https://review.coreboot.org/c/coreboot/+/28380
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017-2018 Patrick Rudolph <siro@das-labor.org>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Nvidia Optimus support methods.
*
* Methods defined here are known to work on Lenovo's Sandy Bridge
* and Ivy Bridge series, which have GPIO21 pulled low on installed dGPU and
* GPIO17 to detect dGPU "PowerGood". They use the same PMH7 functions to
* enable dGPU power and handle dGPU reset.
*/
#define DGPU_RST_N GPP_F22
#define DGPU_PWR_EN GPP_F23
Scope (\_SB.PCI0.PEGP.DEV0)
{
Method (_ON)
{
Debug = "PEGP.DEV0._ON"
If (! GTXS (DGPU_PWR_EN)) {
Debug = "DGPU reset start"
CTXS (DGPU_RST_N)
Debug = "DGPU power enable"
STXS (DGPU_PWR_EN)
Sleep (4)
Debug = "DGPU reset finish"
STXS (DGPU_RST_N)
Sleep (50)
}
}
Method (_OFF)
{
Debug = "PEGP.DEV0._OFF"
If (GTXS (DGPU_PWR_EN)) {
Debug = "DGPU reset start"
CTXS (DGPU_RST_N)
Sleep (4)
Debug = "DGPU power disable"
CTXS (DGPU_PWR_EN)
Sleep (50)
}
}
Method (_STA)
{
If (GTXS (DGPU_PWR_EN)) {
Debug = "PEGP.DEV0._STA F"
Return (0xF)
} Else {
Debug = "PEGP.DEV0._STA 5"
Return (0x5)
}
}
}

217
src/mainboard/system76/addw2/acpi/ec.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
Device (EC0)
{
Name (_HID, EisaId ("PNP0C09") /* Embedded Controller Device */) // _HID: Hardware ID
Name (_GPE, 0x03 /* GPP_K3 */) // _GPE: General Purpose Events
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
IO (Decode16,
0x0062, // Range Minimum
0x0062, // Range Maximum
0x00, // Alignment
0x01, // Length
)
IO (Decode16,
0x0066, // Range Minimum
0x0066, // Range Maximum
0x00, // Alignment
0x01, // Length
)
})
#include "acpi/ec_ram.asl"
Name (ECOK, Zero)
Method (_REG, 2, Serialized) // _REG: Region Availability
{
Debug = Concatenate("EC: _REG", Concatenate(ToHexString(Arg0), Concatenate(" ", ToHexString(Arg1))))
If (((Arg0 == 0x03) && (Arg1 == One))) {
// Enable hardware touchpad lock, airplane mode, and keyboard backlight keys
ECOS = 1
// Enable software display brightness keys
WINF = 1
// Set current AC state
^^^^AC.ACFG = ADP
// Update battery information and status
^^^^BAT0.UPBI()
^^^^BAT0.UPBS()
PNOT ()
// EC is now available
ECOK = Arg1
// Reset System76 Device
^^^^S76D.RSET()
}
}
Method (PTS, 1, Serialized) {
Debug = Concatenate("EC: PTS: ", ToHexString(Arg0))
If (ECOK) {
// Clear wake cause
WFNO = Zero
}
}
Method (WAK, 1, Serialized) {
Debug = Concatenate("EC: WAK: ", ToHexString(Arg0))
If (ECOK) {
// Set current AC state
^^^^AC.ACFG = ADP
// Update battery information and status
^^^^BAT0.UPBI()
^^^^BAT0.UPBS()
// Notify of changes
Notify(^^^^AC, Zero)
Notify(^^^^BAT0, Zero)
// Reset System76 Device
^^^^S76D.RSET()
}
}
Method (_Q0A, 0, NotSerialized) // Touchpad Toggle
{
Debug = "EC: Touchpad Toggle"
}
Method (_Q0B, 0, NotSerialized) // Screen Toggle
{
Debug = "EC: Screen Toggle"
}
Method (_Q0C, 0, NotSerialized) // Mute
{
Debug = "EC: Mute"
}
Method (_Q0D, 0, NotSerialized) // Keyboard Backlight
{
Debug = "EC: Keyboard Backlight"
}
Method (_Q0E, 0, NotSerialized) // Volume Down
{
Debug = "EC: Volume Down"
}
Method (_Q0F, 0, NotSerialized) // Volume Up
{
Debug = "EC: Volume Up"
}
Method (_Q10, 0, NotSerialized) // Switch Video Mode
{
Debug = "EC: Switch Video Mode"
}
Method (_Q11, 0, NotSerialized) // Brightness Down
{
Debug = "EC: Brightness Down"
if (^^^^HIDD.HRDY) {
^^^^HIDD.HPEM (20)
}
}
Method (_Q12, 0, NotSerialized) // Brightness Up
{
Debug = "EC: Brightness Up"
if (^^^^HIDD.HRDY) {
^^^^HIDD.HPEM (19)
}
}
Method (_Q13, 0, NotSerialized) // Camera Toggle
{
Debug = "EC: Camera Toggle"
}
Method (_Q14, 0, NotSerialized) // Airplane Mode
{
Debug = "EC: Airplane Mode"
if (^^^^HIDD.HRDY) {
^^^^HIDD.HPEM (8)
}
// TODO: hardware airplane mode
}
Method (_Q15, 0, NotSerialized) // Suspend Button
{
Debug = "EC: Suspend Button"
Notify (SLPB, 0x80)
}
Method (_Q16, 0, NotSerialized) // AC Detect
{
Debug = "EC: AC Detect"
^^^^AC.ACFG = ADP
Notify (AC, 0x80) // Status Change
If (BAT0)
{
Notify (^^^^BAT0, 0x81) // Information Change
Notify (^^^^BAT0, 0x80) // Status Change
}
}
Method (_Q17, 0, NotSerialized) // BAT0 Update
{
Debug = "EC: BAT0 Update (17)"
Notify (^^^^BAT0, 0x81) // Information Change
}
Method (_Q19, 0, NotSerialized) // BAT0 Update
{
Debug = "EC: BAT0 Update (19)"
Notify (^^^^BAT0, 0x81) // Information Change
}
Method (_Q1B, 0, NotSerialized) // Lid Close
{
Debug = "EC: Lid Close"
Notify (LID0, 0x80)
}
Method (_Q1C, 0, NotSerialized) // Thermal Trip
{
Debug = "EC: Thermal Trip"
/* TODO
Notify (\_TZ.TZ0, 0x81) // Thermal Trip Point Change
Notify (\_TZ.TZ0, 0x80) // Thermal Status Change
*/
}
Method (_Q1D, 0, NotSerialized) // Power Button
{
Debug = "EC: Power Button"
Notify (PWRB, 0x80)
}
Method (_Q50, 0, NotSerialized) // Other Events
{
Local0 = OEM4
If (Local0 == 0x8A) {
Debug = "EC: White Keyboard Backlight"
Notify (^^^^S76D, 0x80)
} ElseIf (Local0 == 0x9F) {
Debug = "EC: Color Keyboard Toggle"
Notify (^^^^S76D, 0x81)
} ElseIf (Local0 == 0x81) {
Debug = "EC: Color Keyboard Down"
Notify (^^^^S76D, 0x82)
} ElseIf (Local0 == 0x82) {
Debug = "EC: Color Keyboard Up"
Notify (^^^^S76D, 0x83)
} ElseIf (Local0 == 0x80) {
Debug = "EC: Color Keyboard Color Change"
Notify (^^^^S76D, 0x84)
} Else {
Debug = Concatenate("EC: Other: ", ToHexString(Local0))
}
}
}

175
src/mainboard/system76/addw2/acpi/ec_ram.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
OperationRegion (ERAM, EmbeddedControl, Zero, 0xFF)
Field (ERAM, ByteAcc, Lock, Preserve)
{
NMSG, 8,
SLED, 4,
Offset (0x02),
MODE, 1,
FAN0, 1,
TME0, 1,
TME1, 1,
FAN1, 1,
, 2,
Offset (0x03),
LSTE, 1,
LSW0, 1,
LWKE, 1,
WAKF, 1,
, 2,
PWKE, 1,
MWKE, 1,
AC0, 8,
PSV, 8,
CRT, 8,
TMP, 8,
AC1, 8,
BBST, 8,
Offset (0x0B),
Offset (0x0C),
Offset (0x0D),
Offset (0x0E),
SLPT, 8,
SWEJ, 1,
SWCH, 1,
Offset (0x10),
ADP, 1,
AFLT, 1,
BAT0, 1,
BAT1, 1,
, 3,
PWOF, 1,
WFNO, 8,
BPU0, 32,
BDC0, 32,
BFC0, 32,
BTC0, 32,
BDV0, 32,
BST0, 32,
BPR0, 32,
BRC0, 32,
BPV0, 32,
BTP0, 16,
BRS0, 16,
BCW0, 32,
BCL0, 32,
BCG0, 32,
BG20, 32,
BMO0, 64,
BIF0, 64,
BSN0, 32,
BTY0, 64,
Offset (0x67),
Offset (0x68),
ECOS, 8,
LNXD, 8,
ECPS, 8,
Offset (0x6C),
BTMP, 16,
EVTN, 8,
Offset (0x72),
PRCL, 8,
PRC0, 8,
PRC1, 8,
PRCM, 8,
PRIN, 8,
PSTE, 8,
PCAD, 8,
PEWL, 8,
PWRL, 8,
PECD, 8,
PEHI, 8,
PECI, 8,
PEPL, 8,
PEPM, 8,
PWFC, 8,
PECC, 8,
PDT0, 8,
PDT1, 8,
PDT2, 8,
PDT3, 8,
PRFC, 8,
PRS0, 8,
PRS1, 8,
PRS2, 8,
PRS3, 8,
PRS4, 8,
PRCS, 8,
PEC0, 8,
PEC1, 8,
PEC2, 8,
PEC3, 8,
CMDR, 8,
CVRT, 8,
GTVR, 8,
FANT, 8,
SKNT, 8,
AMBT, 8,
MCRT, 8,
DIM0, 8,
DIM1, 8,
PMAX, 8,
PPDT, 8,
PECH, 8,
PMDT, 8,
TSD0, 8,
TSD1, 8,
TSD2, 8,
TSD3, 8,
CPUP, 16,
MCHP, 16,
SYSP, 16,
CPAP, 16,
MCAP, 16,
SYAP, 16,
CFSP, 16,
CPUE, 16,
Offset (0xC6),
Offset (0xC7),
VGAT, 8,
OEM1, 8,
OEM2, 8,
OEM3, 16,
OEM4, 8,
Offset (0xCE),
DUT1, 8,
DUT2, 8,
RPM1, 16,
RPM2, 16,
RPM4, 16,
Offset (0xD7),
DTHL, 8,
DTBP, 8,
AIRP, 8,
WINF, 8,
RINF, 8,
Offset (0xDD),
INF2, 8,
MUTE, 1,
Offset (0xE0),
RPM3, 16,
ECKS, 8,
Offset (0xE4),
, 4,
XTUF, 1,
EP12, 1,
Offset (0xE5),
INF3, 8,
Offset (0xE7),
GFOF, 8,
Offset (0xE9),
KPCR, 1,
Offset (0xEA),
Offset (0xF0),
PL1T, 16,
PL2T, 16,
TAUT, 8,
Offset (0xF8),
FCMD, 8,
FDAT, 8,
FBUF, 8,
FBF1, 8,
FBF2, 8,
FBF3, 8
}

11
src/mainboard/system76/addw2/acpi/gpe.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
// GPP_K6 SCI
Method (_L06, 0, Serialized) {
Debug = Concatenate("GPE _L06: ", ToHexString(\_SB.PCI0.LPCB.EC0.WFNO))
If (\_SB.PCI0.LPCB.EC0.ECOK) {
If (\_SB.PCI0.LPCB.EC0.WFNO == One) {
Notify(\_SB.LID0, 0x80)
}
}
}

50
src/mainboard/system76/addw2/acpi/hid.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
Device (HIDD)
{
Name (_HID, "INT33D5")
Name (HBSY, Zero)
Name (HIDX, Zero)
Name (HRDY, Zero)
Method (HDEM, 0, Serialized)
{
HBSY = Zero
Return (HIDX)
}
Method (HDMM, 0, Serialized)
{
Return (Zero)
}
Method (HDSM, 1, Serialized)
{
HRDY = Arg0
}
Method (HPEM, 1, Serialized)
{
HBSY = One
HIDX = Arg0
Notify (HIDD, 0xC0)
Local0 = Zero
While (((Local0 < 0xFA) && HBSY))
{
Sleep (0x04)
Local0++
}
If ((HBSY == One))
{
HBSY = Zero
HIDX = Zero
Return (One)
}
Else
{
Return (Zero)
}
}
}

23
src/mainboard/system76/addw2/acpi/lid.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
Device (LID0)
{
Name (_HID, EisaId ("PNP0C0D"))
Name (_PRW, Package () { 0x06 /* GPP_K6 */, 3 })
Method (_LID, 0, NotSerialized) {
DEBUG = "LID: _LID"
If (^^PCI0.LPCB.EC0.ECOK) {
Return (^^PCI0.LPCB.EC0.LSTE)
} Else {
Return (One)
}
}
Method (_PSW, 1, NotSerialized) {
DEBUG = Concatenate("LID: _PSW: ", ToHexString(Arg0))
If (^^PCI0.LPCB.EC0.ECOK) {
^^PCI0.LPCB.EC0.LWKE = Arg0
}
}
}

15
src/mainboard/system76/addw2/acpi/mainboard.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
Scope (\_SB) {
#include "ac.asl"
#include "battery.asl"
#include "buttons.asl"
#include "hid.asl"
#include "lid.asl"
#include "s76.asl"
#include "sleep.asl"
}
Scope (_GPE) {
#include "gpe.asl"
}

164
src/mainboard/system76/addw2/acpi/pegp.asl Normal file
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// From https://review.coreboot.org/c/coreboot/+/40625
/* SPDX-License-Identifier: GPL-2.0-only */
Device (PEGP)
{
Name (_ADR, 0x00010000)
OperationRegion (PEGC, PCI_Config, 0x00, 0x0100)
Field (PEGC, AnyAcc, NoLock, Preserve)
{
Offset (0x04), // Device Command; Primary Status
PCMR, 8, // SC, BM, Mem and I/O bitmask
/* Offset (0x4a), // Device Control; Device Status
CEDR, 1, // Correctable Error Detected */
Offset (0x50), // Link Control; Link Status
ASPM, 2, // ASPM Control
, 2,
LNKD, 1, // Link Disable
RTRL, 1, // Retrain Link
, 21,
LNKT, 1, // Link Training
Offset (0x69), // Device Control 2; Device Status 2
, 2,
LREN, 1, // LTR Enable
/* Offset (0x80), // MSI Control
, 16,
MSIE, 1, // MSI enable */
Offset (0xa4), // Power Management
PMST, 2, // Power State
/* Offset (0x328),
, 19,
LNKS, 4, // Link Status? */
}
OperationRegion (PCAP, PCI_Config, 0x40, 0x14)
Field (PCAP, DWordAcc, NoLock, Preserve)
{
Offset (0x10),
LCTL, 16, // Link Control
}
PowerResource (PWRR, 0, 0)
{
Name (_STA, 1)
Method (_ON)
{
Debug = "PEGP.PWRR._ON"
\_SB.PCI0.PEGP._ON ()
PCMR = 0x07 // Bus Master, Memory and I/O space enabled
PMST = 0 // Power state: D0
// MSIE = 1 // Enable MSI interrupts
_STA = 1
}
Method (_OFF)
{
Debug = "PEGP.PWRR._OFF"
\_SB.PCI0.PEGP._OFF ()
_STA = 0
}
}
/* Depend on the CLK to be active. _PR3 is also searched by nouveau to
* detect "Windows 8 compatible Optimus _DSM handler".
*/
Name (_PRE, Package () { \_SB.PCI0.PEGP.PWRR })
Name (_PR0, Package () { \_SB.PCI0.PEGP.PWRR })
Name (_PR3, Package () { \_SB.PCI0.PEGP.PWRR })
Method (_PS0)
{
Debug = "PEGP._PS0"
LNKD = 0
RTRL = 1
Local1 = 0x32
While (Local1)
{
Sleep (2)
If (LNKT == 0)
{
Break
}
Local1--
}
}
Method (_PS3)
{
Debug = "PEGP._PS3"
LNKD = 1
}
Method (_PSC, 0, Serialized)
{
If (LNKD == 1)
{
Debug = "PEGP._PSC 3"
Return (3)
}
Else
{
Debug = "PEGP._PSC 0"
Return (0)
}
}
Method (_ON)
{
Debug = "PEGP._ON"
If (^DEV0.ONOF == 0)
{
^DEV0.ONOF = 1
^DEV0._ON ()
LREN = ^DEV0.LTRE // Restore LTR enable bit
// CEDR = 1
// Restore the Link Control register
LCTL = ((^DEV0.ELCT & 0x43) | (LCTL & 0xFFBC))
//Notify (\_SB.PCI0, 0) // Bus Check
}
}
Method (_OFF)
{
Debug = "PEGP._OFF"
If (^DEV0.ONOF == 1)
{
^DEV0.ONOF = 0
^DEV0.ELCT = LCTL // Save the Link Control register
^DEV0.LTRE = LREN // Save LTR enable bit
^DEV0._OFF ()
//Notify (\_SB.PCI0, 0) // Bus Check
}
}
Method (_STA)
{
If (^DEV0.ONOF)
{
Debug = "PEGP._STA F"
Return (0xF)
}
Else
{
Debug = "PEGP._STA 5"
Return (0x5)
}
}
Device (DEV0)
{
Name(_ADR, 0x00000000)
Name (ONOF, 1)
Name (ELCT, 0)
Name (LTRE, 0)
}
Device (DEV1)
{
Name(_ADR, 0x00000001)
}
}

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src/mainboard/system76/addw2/acpi/s76.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
// Notifications:
// 0x80 - hardware backlight toggle
// 0x81 - backlight toggle
// 0x82 - backlight down
// 0x83 - backlight up
// 0x84 - backlight color change
Device (S76D) {
Name (_HID, "17761776")
Name (_UID, 0)
Method (RSET, 0, Serialized) {
Debug = "S76D: RSET"
SAPL(0)
SKBL(0)
SKBC(0xFFFFFF)
}
Method (INIT, 0, Serialized) {
Debug = "S76D: INIT"
RSET()
If (^^PCI0.LPCB.EC0.ECOK) {
// Set flags to use software control
^^PCI0.LPCB.EC0.ECOS = 2
Return (0)
} Else {
Return (1)
}
}
Method (FINI, 0, Serialized) {
Debug = "S76D: FINI"
RSET()
If (^^PCI0.LPCB.EC0.ECOK) {
// Set flags to use hardware control
^^PCI0.LPCB.EC0.ECOS = 1
Return (0)
} Else {
Return (1)
}
}
// Get Airplane LED
Method (GAPL, 0, Serialized) {
If (^^PCI0.LPCB.EC0.ECOK) {
If (^^PCI0.LPCB.EC0.AIRP & 0x40) {
Return (1)
}
}
Return (0)
}
// Set Airplane LED
Method (SAPL, 1, Serialized) {
If (^^PCI0.LPCB.EC0.ECOK) {
If (Arg0) {
^^PCI0.LPCB.EC0.AIRP |= 0x40
} Else {
^^PCI0.LPCB.EC0.AIRP &= 0xBF
}
}
}
// Set KB LED Brightness
Method (SKBL, 1, Serialized) {
If (^^PCI0.LPCB.EC0.ECOK) {
^^PCI0.LPCB.EC0.FDAT = 6
^^PCI0.LPCB.EC0.FBUF = Arg0
^^PCI0.LPCB.EC0.FBF1 = 0
^^PCI0.LPCB.EC0.FBF2 = Arg0
^^PCI0.LPCB.EC0.FCMD = 0xCA
}
}
// Set Keyboard Color
Method (SKBC, 1, Serialized) {
If (^^PCI0.LPCB.EC0.ECOK) {
^^PCI0.LPCB.EC0.FDAT = 0x3
^^PCI0.LPCB.EC0.FBUF = (Arg0 & 0xFF)
^^PCI0.LPCB.EC0.FBF1 = ((Arg0 >> 16) & 0xFF)
^^PCI0.LPCB.EC0.FBF2 = ((Arg0 >> 8) & 0xFF)
^^PCI0.LPCB.EC0.FCMD = 0xCA
Return (Arg0)
} Else {
Return (0)
}
}
}

11
src/mainboard/system76/addw2/acpi/sleep.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/* Method called from _PTS prior to enter sleep state */
Method (MPTS, 1) {
\_SB.PCI0.LPCB.EC0.PTS (Arg0)
}
/* Method called from _WAK prior to wakeup */
Method (MWAK, 1) {
\_SB.PCI0.LPCB.EC0.WAK (Arg0)
}

8
src/mainboard/system76/addw2/board_info.txt Normal file
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Vendor name: System76
Board name: addw2
Category: laptop
Release year: 2020
ROM package: SOIC-8
ROM protocol: SPI
ROM socketed: n
Flashrom support: y

26
src/mainboard/system76/addw2/bootblock.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h>
#include <delay.h>
#include <gpio.h>
#include "gpio.h"
static void dgpu_power_enable(int onoff) {
if (onoff) {
gpio_set(DGPU_RST_N, 0);
gpio_set(DGPU_PWR_EN, 1);
mdelay(4);
gpio_set(DGPU_RST_N, 1);
} else {
gpio_set(DGPU_RST_N, 0);
mdelay(4);
gpio_set(DGPU_PWR_EN, 0);
}
mdelay(50);
}
void bootblock_mainboard_init(void)
{
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
dgpu_power_enable(1);
}

BIN
src/mainboard/system76/addw2/data.vbt Normal file
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Binary file not shown.

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src/mainboard/system76/addw2/devicetree.cb Normal file
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chip soc/intel/cannonlake
# Lock Down
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
// Touchpad I2C bus
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 80,
.fall_time_ns = 110,
},
}"
# Send an extra VR mailbox command for the PS4 exit issue
register "SendVrMbxCmd" = "2"
# ACPI (soc/intel/cannonlake/acpi.c)
# Enable s0ix
register "s0ix_enable" = "1"
# PM Timer Enabled
register "PmTimerDisabled" = "0"
# Disable DPTF
register "dptf_enable" = "0"
# CPU (soc/intel/cannonlake/cpu.c)
# Power limit
register "power_limits_config" = "{
.tdp_pl1_override = 45,
.tdp_pl2_override = 68,
}"
# Enable "Intel Speed Shift Technology"
register "speed_shift_enable" = "1"
# Enable Enhanced Intel SpeedStep
register "eist_enable" = "1"
# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
register "SaGv" = "SaGv_Enabled"
register "enable_c6dram" = "1"
# FSP Silicon (soc/intel/cannonlake/fsp_params.c)
# Serial I/O
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad I2C bus
[PchSerialIoIndexI2C1] = PchSerialIoPci, // USB-C and Thunderbolt
[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
[PchSerialIoIndexSPI0] = PchSerialIoDisabled,
[PchSerialIoIndexSPI1] = PchSerialIoDisabled,
[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
[PchSerialIoIndexUART0] = PchSerialIoDisabled,
[PchSerialIoIndexUART1] = PchSerialIoDisabled,
[PchSerialIoIndexUART2] = PchSerialIoPci, // Debug console
}"
# SATA
register "SataMode" = "Sata_AHCI"
register "SataSalpSupport" = "0"
register "SataPortsEnable[0]" = "1" # HDD (SATA0B)
register "SataPortsEnable[1]" = "1" # SSD1 (SATA1A)
register "SataPortsEnable[2]" = "0"
register "SataPortsEnable[3]" = "0"
register "SataPortsEnable[4]" = "0"
register "SataPortsEnable[5]" = "0"
register "SataPortsEnable[6]" = "0"
register "SataPortsEnable[7]" = "0"
register "SataPortsDevSlp[0]" = "0"
register "SataPortsDevSlp[1]" = "0"
register "SataPortsDevSlp[2]" = "0"
register "SataPortsDevSlp[3]" = "0"
register "SataPortsDevSlp[4]" = "0"
register "SataPortsDevSlp[5]" = "0"
register "SataPortsDevSlp[6]" = "0"
register "SataPortsDevSlp[7]" = "0"
# Audio
register "PchHdaDspEnable" = "0"
register "PchHdaAudioLinkHda" = "1"
register "PchHdaAudioLinkDmic0" = "1"
register "PchHdaAudioLinkDmic1" = "1"
register "PchHdaAudioLinkSsp0" = "0"
register "PchHdaAudioLinkSsp1" = "0"
register "PchHdaAudioLinkSsp2" = "0"
register "PchHdaAudioLinkSndw1" = "0"
register "PchHdaAudioLinkSndw2" = "0"
register "PchHdaAudioLinkSndw3" = "0"
register "PchHdaAudioLinkSndw4" = "0"
# USB
register "SsicPortEnable" = "0"
# USB2
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C and DisplayPort
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 Gen 2
register "usb2_ports[3]" = "USB2_PORT_EMPTY"
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 Gen 1 audio
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 Gen 1 back
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Per-Key RGB keyboard
register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Camera
register "usb2_ports[9]" = "USB2_PORT_EMPTY"
register "usb2_ports[10]" = "USB2_PORT_EMPTY"
register "usb2_ports[11]" = "USB2_PORT_EMPTY"
register "usb2_ports[12]" = "USB2_PORT_EMPTY"
register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
register "usb2_ports[14]" = "USB2_PORT_EMPTY"
register "usb2_ports[15]" = "USB2_PORT_EMPTY"
# USB3
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C and DisplayPort
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 right
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C (without TBT)
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C (without TBT)
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 1 audio
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 1 back
register "usb3_ports[6]" = "USB3_PORT_EMPTY"
register "usb3_ports[7]" = "USB3_PORT_EMPTY"
register "usb3_ports[8]" = "USB3_PORT_EMPTY"
register "usb3_ports[9]" = "USB3_PORT_EMPTY"
# PCI Express Graphics #0 x16, Clock (NVIDIA GPU)
register "PcieClkSrcUsage[8]" = "0x40"
# PCI Express root port #9 x4, Clock 9 (SSD1)
register "PcieRpEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieClkSrcUsage[9]" = "8"
# PCI Express root port #14 x1, Clock 5 (GLAN)
register "PcieRpEnable[13]" = "1"
register "PcieRpLtrEnable[13]" = "1"
register "PcieClkSrcUsage[5]" = "13"
# PCI Express root port #15 x1, Clock 7 (Card Reader)
register "PcieRpEnable[14]" = "1"
register "PcieRpLtrEnable[14]" = "1"
register "PcieClkSrcUsage[7]" = "14"
# PCI Express root port #16 x1, Clock 6 (WLAN)
register "PcieRpEnable[15]" = "1"
register "PcieRpLtrEnable[15]" = "1"
register "PcieClkSrcUsage[6]" = "15"
# PCI Express root port #17 x4, Clock 0 (Thunderbolt)
register "PcieRpEnable[16]" = "1"
register "PcieRpLtrEnable[16]" = "1"
register "PcieRpHotPlug[16]" = "1"
register "PcieClkSrcUsage[0]" = "16"
# PCI Express root port #21 x4, Clock 10 (SSD2)
register "PcieRpEnable[20]" = "1"
register "PcieRpLtrEnable[20]" = "1"
register "PcieClkSrcUsage[10]" = "20"
# Set all clocks sources to the same clock request
register "PcieClkSrcClkReq[0]" = "0"
register "PcieClkSrcClkReq[1]" = "1"
register "PcieClkSrcClkReq[2]" = "2"
register "PcieClkSrcClkReq[3]" = "3"
register "PcieClkSrcClkReq[4]" = "4"
register "PcieClkSrcClkReq[5]" = "5"
register "PcieClkSrcClkReq[6]" = "6"
register "PcieClkSrcClkReq[7]" = "7"
register "PcieClkSrcClkReq[8]" = "8"
register "PcieClkSrcClkReq[9]" = "9"
register "PcieClkSrcClkReq[10]" = "10"
register "PcieClkSrcClkReq[11]" = "11"
register "PcieClkSrcClkReq[12]" = "12"
register "PcieClkSrcClkReq[13]" = "13"
register "PcieClkSrcClkReq[14]" = "14"
register "PcieClkSrcClkReq[15]" = "15"
# Misc
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
register "Heci3Enabled" = "0"
register "AcousticNoiseMitigation" = "1"
#register "dmipwroptimize" = "1"
#register "satapwroptimize" = "1"
# Power
register "PchPmSlpS3MinAssert" = "3" # 50ms
register "PchPmSlpS4MinAssert" = "1" # 1s
register "PchPmSlpSusMinAssert" = "2" # 500ms
register "PchPmSlpAMinAssert" = "4" # 2s
# Thermal
register "tcc_offset" = "12"
# Serial IRQ Continuous
register "serirq_mode" = "SERIRQ_CONTINUOUS"
# LPC (soc/intel/cannonlake/lpc.c)
# LPC configuration from lspci -s 1f.0 -xxx
# Address 0x84: Decode 0x80 - 0x8F (Port 80)
register "gen1_dec" = "0x000c0081"
# Address 0x88: Decode 0x68 - 0x6F (PMC)
register "gen2_dec" = "0x00040069"
# Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command)
register "gen3_dec" = "0x00fc0E01"
# Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug)
register "gen4_dec" = "0x00fc0F01"
# PMC (soc/intel/cannonlake/pmc.c)
# Enable deep Sx states
register "deep_s3_enable_ac" = "0"
register "deep_s3_enable_dc" = "0"
register "deep_s5_enable_ac" = "0"
register "deep_s5_enable_dc" = "0"
register "deep_sx_config" = "0"
# PM Util (soc/intel/cannonlake/pmutil.c)
# GPE configuration
# Note that GPE events called out in ASL code rely on this
# route. i.e. If this route changes then the affected GPE
# offset bits also need to be changed.
# sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
register "gpe0_dw0" = "PMC_GPP_K"
register "gpe0_dw1" = "PMC_GPP_G"
register "gpe0_dw2" = "PMC_GPP_E"
# Actual device tree
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
device pci 00.0 on end # Host Bridge
device pci 01.0 on end # GPU Port
device pci 02.0 on end # Integrated Graphics Device
device pci 04.0 on end # SA Thermal device
device pci 12.0 on end # Thermal Subsystem
device pci 12.5 off end # UFS SCS
device pci 12.6 off end # GSPI #2
device pci 13.0 off end # Integrated Sensor Hub
device pci 14.0 on end # USB xHCI
device pci 14.1 off end # USB xDCI (OTG)
device pci 14.2 on end # Shared SRAM
#chip drivers/intel/wifi
# register "wake" = "PME_B0_EN_BIT"
device pci 14.3 on end # CNVi wifi
#end
device pci 14.5 off end # SDCard
device pci 15.0 on
chip drivers/i2c/hid
register "generic.hid" = ""PNP0C50""
register "generic.desc" = ""Synaptics Touchpad""
register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_A14_IRQ)"
register "generic.probed" = "1"
register "hid_desc_reg_offset" = "0x20"
device i2c 2c on end
end
end # I2C #0
device pci 15.1 on end # I2C #1
device pci 15.2 off end # I2C #2
device pci 15.3 off end # I2C #3
device pci 16.0 off end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT Redirection
device pci 16.4 off end # Management Engine Interface 3
device pci 16.5 off end # Management Engine Interface 4
device pci 17.0 on end # SATA
device pci 19.0 off end # I2C #4
device pci 19.1 off end # I2C #5
device pci 19.2 on end # UART #2
device pci 1a.0 off end # eMMC
device pci 1b.0 on end # PCI Express Port 17
device pci 1b.1 off end # PCI Express Port 18
device pci 1b.2 off end # PCI Express Port 19
device pci 1b.3 off end # PCI Express Port 20
device pci 1b.4 on end # PCI Express Port 21
device pci 1b.5 off end # PCI Express Port 22
device pci 1b.6 off end # PCI Express Port 23
device pci 1b.7 off end # PCI Express Port 24
device pci 1c.0 off end # PCI Express Port 1
device pci 1c.1 off end # PCI Express Port 2
device pci 1c.2 off end # PCI Express Port 3
device pci 1c.3 off end # PCI Express Port 4
device pci 1c.4 off end # PCI Express Port 5
device pci 1c.5 off end # PCI Express Port 6
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 off end # PCI Express Port 8
device pci 1d.0 on end # PCI Express Port 9
device pci 1d.1 off end # PCI Express Port 10
device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12
device pci 1d.4 off end # PCI Express Port 13
device pci 1d.5 on end # PCI Express Port 14
device pci 1d.6 on end # PCI Express Port 15
device pci 1d.7 on end # PCI Express Port 16
device pci 1e.0 off end # UART #0
device pci 1e.1 off end # UART #1
device pci 1e.2 off end # GSPI #0
device pci 1e.3 off end # GSPI #1
device pci 1f.0 on # LPC Interface
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
end
device pci 1f.1 off end # P2SB
device pci 1f.2 off end # Power Management Controller
device pci 1f.3 on end # Intel HDA
device pci 1f.4 on end # SMBus
device pci 1f.5 on end # PCH SPI
device pci 1f.6 off end # GbE
end
end

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src/mainboard/system76/addw2/dsdt.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
DefinitionBlock(
"dsdt.aml",
"DSDT",
0x02, // DSDT revision: ACPI v2.0 and up
OEM_ID,
ACPI_TABLE_CREATOR,
0x20110725 // OEM revision
)
{
#include <soc/intel/cannonlake/acpi/platform.asl>
#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Device (\_SB.PCI0)
{
#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
#include <soc/intel/cannonlake/acpi/southbridge.asl>
#include "acpi/pegp.asl"
#include "acpi/dgpu.asl"
}
#include <southbridge/intel/common/acpi/sleepstates.asl>
Scope (\_SB.PCI0.LPCB)
{
#include <drivers/pc80/pc/ps2_controller.asl>
#include "acpi/ec.asl"
}
#include "acpi/mainboard.asl"
}

256
src/mainboard/system76/addw2/gpio.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef MAINBOARD_GPIO_H
#define MAINBOARD_GPIO_H
#include <soc/gpe.h>
#include <soc/gpio.h>
#define DGPU_RST_N GPP_F22
#define DGPU_PWR_EN GPP_F23
#ifndef __ACPI__
/* Pad configuration in romstage. */
static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPI(GPP_C20, NONE, DEEP),
PAD_CFG_GPI(GPP_C21, NONE, DEEP),
PAD_CFG_TERM_GPO(GPP_F22, 0, NONE, DEEP), // DGPU_RST#_PCH
PAD_CFG_TERM_GPO(GPP_F23, 0, NONE, DEEP), // DGPU_PWR_EN
};
/* Pad configuration in ramstage. */
static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1),
PAD_CFG_GPI(GPD2, NATIVE, PWROK),
PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
PAD_CFG_GPI(GPD7, NONE, PWROK),
PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
PAD_CFG_NF(GPD9, NONE, PWROK, NF1),
_PAD_CFG_STRUCT(GPD10, 0x04000601, 0x0000),
PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
PAD_CFG_GPI(GPP_A0, NONE, DEEP),
PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),
PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),
PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),
PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
PAD_CFG_GPI(GPP_A7, NONE, DEEP),
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1),
PAD_CFG_GPI(GPP_A11, UP_20K, DEEP),
PAD_CFG_GPI(GPP_A12, NONE, DEEP),
PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
PAD_CFG_GPI_APIC(GPP_A14, NONE, PLTRST, EDGE_SINGLE, INVERT), // TCHPD_INT#
PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1),
PAD_CFG_GPI(GPP_A16, DN_20K, DEEP),
PAD_CFG_GPI(GPP_A17, NONE, DEEP),
PAD_CFG_TERM_GPO(GPP_A18, 1, NONE, DEEP),
PAD_CFG_GPI(GPP_A19, NONE, DEEP),
PAD_CFG_GPI(GPP_A20, NONE, DEEP),
_PAD_CFG_STRUCT(GPP_A21, 0x46080100, 0x0000),
PAD_CFG_TERM_GPO(GPP_A22, 0, NONE, DEEP),
PAD_CFG_GPI(GPP_A23, NONE, DEEP),
_PAD_CFG_STRUCT(GPP_B0, 0x42080100, 0x3000),
PAD_CFG_GPI(GPP_B1, NONE, DEEP),
PAD_CFG_GPI(GPP_B2, NONE, DEEP),
PAD_CFG_TERM_GPO(GPP_B3, 1, NONE, DEEP),
PAD_CFG_GPI(GPP_B4, NONE, DEEP),
PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
PAD_CFG_GPI(GPP_B6, NONE, DEEP),
PAD_CFG_TERM_GPO(GPP_B7, 0, NONE, DEEP),
PAD_CFG_GPI(GPP_B8, NONE, DEEP),
PAD_CFG_GPI(GPP_B9, NONE, DEEP),
PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
PAD_CFG_GPI(GPP_B11, NONE, DEEP),
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
_PAD_CFG_STRUCT(GPP_B13, 0x44000601, 0x0000),
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
PAD_CFG_GPI(GPP_B15, NONE, DEEP),
PAD_CFG_GPI(GPP_B16, NONE, DEEP),
PAD_CFG_GPI(GPP_B17, NONE, DEEP),
PAD_CFG_GPI(GPP_B18, NONE, DEEP),
PAD_CFG_GPI(GPP_B19, NONE, DEEP),
_PAD_CFG_STRUCT(GPP_B20, 0x42840101, 0x0000),
PAD_CFG_GPI(GPP_B21, NONE, DEEP),
PAD_CFG_GPI(GPP_B22, NONE, DEEP),
PAD_CFG_GPI(GPP_B23, NONE, DEEP),
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
PAD_CFG_GPI(GPP_C2, NONE, DEEP),
PAD_CFG_GPI(GPP_C3, NONE, DEEP),
PAD_CFG_GPI(GPP_C4, NONE, DEEP),
PAD_CFG_GPI(GPP_C5, NONE, DEEP),
PAD_CFG_GPI(GPP_C6, NONE, DEEP),
PAD_CFG_GPI(GPP_C7, NONE, DEEP),
PAD_CFG_GPI(GPP_C8, NONE, DEEP),
PAD_CFG_GPI(GPP_C9, NONE, DEEP),
PAD_CFG_GPI(GPP_C10, NONE, DEEP),
PAD_CFG_GPI(GPP_C11, NONE, DEEP), // TBT_DET#
PAD_CFG_GPI(GPP_C12, NONE, DEEP),
PAD_CFG_GPI(GPP_C13, NONE, PLTRST),
PAD_CFG_TERM_GPO(GPP_C14, 1, NONE, DEEP),
PAD_CFG_GPI(GPP_C15, NONE, DEEP),
PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1),
PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1),
PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1),
PAD_CFG_NF(GPP_C19, NONE, PLTRST, NF1),
PAD_CFG_GPI(GPP_C20, NONE, DEEP),
PAD_CFG_GPI(GPP_C21, NONE, DEEP),
PAD_CFG_GPI(GPP_C22, NONE, DEEP),
PAD_CFG_GPI(GPP_C23, NONE, DEEP),
PAD_CFG_GPI(GPP_D0, NONE, DEEP),
PAD_CFG_GPI(GPP_D1, NONE, DEEP),
PAD_CFG_GPI(GPP_D2, NONE, DEEP),
PAD_CFG_GPI(GPP_D3, NONE, DEEP),
PAD_CFG_GPI(GPP_D4, NONE, DEEP),
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3),
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3),
PAD_CFG_GPI(GPP_D7, NONE, DEEP),
PAD_CFG_GPI(GPP_D8, NONE, DEEP),
PAD_CFG_GPI(GPP_D9, NONE, DEEP),
PAD_CFG_GPI(GPP_D10, NONE, DEEP),
PAD_CFG_GPI(GPP_D11, NONE, DEEP),
PAD_CFG_GPI(GPP_D12, NONE, DEEP),
PAD_CFG_GPI(GPP_D13, NONE, DEEP),
PAD_CFG_GPI(GPP_D14, NONE, DEEP),
PAD_CFG_GPI(GPP_D15, NONE, DEEP),
PAD_CFG_GPI(GPP_D16, NONE, DEEP),
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
PAD_CFG_GPI(GPP_D21, NONE, DEEP),
PAD_CFG_GPI(GPP_D22, NONE, DEEP),
PAD_CFG_GPI(GPP_D23, NONE, DEEP),
PAD_CFG_GPI(GPP_E0, NONE, DEEP),
PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1),
PAD_CFG_GPI(GPP_E2, NONE, DEEP),
PAD_CFG_GPI(GPP_E3, NONE, DEEP),
PAD_CFG_GPI(GPP_E4, NONE, DEEP),
PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
PAD_CFG_TERM_GPO(GPP_E6, 1, NONE, DEEP),
PAD_CFG_GPI(GPP_E7, NONE, DEEP),
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
PAD_CFG_GPI(GPP_E9, NONE, DEEP),
PAD_CFG_GPI(GPP_E10, NONE, DEEP),
PAD_CFG_GPI(GPP_E11, NONE, DEEP),
PAD_CFG_GPI(GPP_E12, NONE, DEEP),
PAD_CFG_GPI(GPP_F0, NONE, DEEP),
PAD_CFG_GPI(GPP_F1, NONE, DEEP),
PAD_CFG_GPI(GPP_F2, NONE, DEEP),
PAD_CFG_TERM_GPO(GPP_F3, 0, NONE, DEEP),
PAD_CFG_GPI(GPP_F4, NONE, DEEP),
PAD_CFG_GPI(GPP_F5, NONE, DEEP),
PAD_CFG_GPI(GPP_F6, NONE, DEEP),
PAD_CFG_GPI(GPP_F7, NONE, DEEP),
PAD_CFG_GPI(GPP_F8, NONE, DEEP),
PAD_CFG_TERM_GPO(GPP_F9, 0, NONE, DEEP), // PS8331_SW
PAD_CFG_GPI(GPP_F10, NONE, DEEP),
PAD_CFG_GPI(GPP_F11, NONE, DEEP),
PAD_CFG_GPI(GPP_F12, NONE, DEEP),
PAD_CFG_GPI(GPP_F13, NONE, DEEP),
PAD_CFG_GPI(GPP_F14, NONE, DEEP),
PAD_CFG_GPI(GPP_F15, NONE, DEEP),
PAD_CFG_GPI(GPP_F16, NONE, DEEP),
PAD_CFG_GPI(GPP_F17, NONE, DEEP),
PAD_CFG_GPI(GPP_F18, NONE, DEEP),
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
PAD_CFG_TERM_GPO(GPP_F22, 1, NONE, DEEP), // DGPU_RST#_PCH
PAD_CFG_TERM_GPO(GPP_F23, 1, NONE, DEEP), // DGPU_PWR_EN
PAD_CFG_GPI(GPP_G0, NONE, DEEP),
PAD_CFG_GPI(GPP_G1, NONE, DEEP),
PAD_CFG_GPI(GPP_G2, NONE, DEEP),
PAD_CFG_GPI(GPP_G3, NONE, DEEP),
PAD_CFG_GPI(GPP_G4, NONE, DEEP),
PAD_CFG_GPI(GPP_G5, NONE, DEEP),
PAD_CFG_GPI(GPP_G6, NONE, DEEP),
PAD_CFG_GPI(GPP_G7, NONE, DEEP),
PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1),
PAD_CFG_GPI(GPP_H4, NONE, DEEP),
PAD_CFG_GPI(GPP_H5, NONE, DEEP),
PAD_CFG_TERM_GPO(GPP_H6, 1, NONE, DEEP),
PAD_CFG_TERM_GPO(GPP_H7, 1, NONE, DEEP),
PAD_CFG_GPI(GPP_H8, NONE, DEEP),
_PAD_CFG_STRUCT(GPP_H9, 0x40880100, 0x0000),
PAD_CFG_GPI(GPP_H10, NONE, DEEP),
PAD_CFG_GPI(GPP_H11, NONE, DEEP),
PAD_CFG_GPI(GPP_H12, NONE, DEEP),
PAD_CFG_GPI(GPP_H13, NONE, DEEP), // TBTA_HRESET
PAD_CFG_GPI(GPP_H14, NONE, DEEP),
PAD_CFG_GPI(GPP_H15, NONE, DEEP),
PAD_CFG_TERM_GPO(GPP_H16, 1, NONE, DEEP), // TBT_RTD3_PWR_EN_R
PAD_CFG_TERM_GPO(GPP_H17, 1, NONE, PLTRST), // TBT_FORCE_PWR_R
PAD_CFG_GPI(GPP_H18, NONE, DEEP),
PAD_CFG_TERM_GPO(GPP_H19, 0, NONE, DEEP),
PAD_CFG_TERM_GPO(GPP_H20, 0, NONE, DEEP),
PAD_CFG_GPI(GPP_H21, NONE, DEEP),
PAD_CFG_GPI(GPP_H22, NONE, DEEP),
_PAD_CFG_STRUCT(GPP_H23, 0x82880100, 0x0000),
_PAD_CFG_STRUCT(GPP_I0, 0x46080100, 0x0000),
_PAD_CFG_STRUCT(GPP_I1, 0x46080100, 0x0000),
_PAD_CFG_STRUCT(GPP_I2, 0x46080100, 0x0000),
_PAD_CFG_STRUCT(GPP_I3, 0x46080100, 0x0000),
PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1),
PAD_CFG_TERM_GPO(GPP_I5, 1, UP_20K, PLTRST), // TBT_GPIO_RST#
PAD_CFG_GPI(GPP_I6, NONE, DEEP),
PAD_CFG_GPI(GPP_I7, NONE, DEEP),
PAD_CFG_TERM_GPO(GPP_I8, 1, NONE, DEEP),
PAD_CFG_TERM_GPO(GPP_I9, 1, NONE, DEEP),
PAD_CFG_GPI(GPP_I10, NONE, DEEP),
PAD_CFG_GPI(GPP_I11, NONE, DEEP),
PAD_CFG_TERM_GPO(GPP_I12, 1, NONE, DEEP),
PAD_CFG_GPI(GPP_I13, NONE, DEEP),
PAD_CFG_GPI(GPP_I14, NONE, DEEP),
PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1),
PAD_CFG_TERM_GPO(GPP_J1, 1, NONE, DEEP),
PAD_CFG_GPI(GPP_J2, NONE, DEEP),
PAD_CFG_GPI(GPP_J3, NONE, DEEP),
PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1),
PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1),
PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1),
PAD_CFG_GPI(GPP_J10, NONE, DEEP),
PAD_CFG_GPI(GPP_J11, DN_20K, DEEP),
PAD_CFG_TERM_GPO(GPP_K0, 0, NONE, DEEP),
PAD_CFG_TERM_GPO(GPP_K1, 0, NONE, DEEP),
PAD_CFG_GPI(GPP_K2, NONE, DEEP),
_PAD_CFG_STRUCT(GPP_K3, 0x40880100, 0x0000),
_PAD_CFG_STRUCT(GPP_K4, 0x44000101, 0x0000),
PAD_CFG_GPI(GPP_K5, NONE, DEEP),
_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000),
PAD_CFG_GPI(GPP_K7, NONE, DEEP),
PAD_CFG_TERM_GPO(GPP_K8, 0, NONE, DEEP),
PAD_CFG_GPI(GPP_K9, NONE, DEEP),
PAD_CFG_GPI(GPP_K10, NONE, DEEP),
PAD_CFG_GPI(GPP_K11, NONE, DEEP),
PAD_CFG_TERM_GPO(GPP_K12, 0, NONE, DEEP),
PAD_CFG_GPI(GPP_K13, NONE, DEEP),
PAD_CFG_TERM_GPO(GPP_K14, 0, NONE, DEEP),
_PAD_CFG_STRUCT(GPP_K15, 0x80100100, 0x0000),
PAD_CFG_GPI(GPP_K16, NONE, DEEP),
PAD_CFG_GPI(GPP_K17, NONE, DEEP),
PAD_CFG_TERM_GPO(GPP_K18, 1, NONE, DEEP),
PAD_CFG_GPI(GPP_K19, NONE, DEEP),
PAD_CFG_GPI(GPP_K20, NONE, DEEP),
PAD_CFG_GPI(GPP_K21, NONE, DEEP),
PAD_CFG_TERM_GPO(GPP_K22, 0, NONE, DEEP),
PAD_CFG_GPI(GPP_K23, NONE, DEEP),
};
#endif
#endif

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src/mainboard/system76/addw2/hda_verb.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef HDA_VERB_H
#define HDA_VERB_H
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
/* Realtek, ALC1220 */
0x10ec1220, /* Vendor ID */
0x155865e1, /* Subsystem ID */
12, /* Number of entries */
AZALIA_SUBVENDOR(0, 0x155865e1),
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
AZALIA_PIN_CFG(0, 0x14, 0x0421101f),
AZALIA_PIN_CFG(0, 0x15, 0x40000000),
AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
AZALIA_PIN_CFG(0, 0x18, 0x04a11040),
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d),
AZALIA_PIN_CFG(0, 0x1e, 0x04451150),
/* Intel, KabylakeHDMI */
0x8086280b, /* Vendor ID */
0x80860101, /* Subsystem ID */
4, /* Number of entries */
AZALIA_SUBVENDOR(2, 0x80860101),
AZALIA_PIN_CFG(2, 0x05, 0x18560010),
AZALIA_PIN_CFG(2, 0x06, 0x18560010),
AZALIA_PIN_CFG(2, 0x07, 0x18560010),
/* Nvidia, GPU92HDMI/DP */
0x10de0092, /* Vendor ID */
0x155865e1, /* Subsystem ID */
5, /* Number of entries */
AZALIA_SUBVENDOR(0, 0x155865e1),
AZALIA_PIN_CFG(0, 0x04, 0x185600f0),
AZALIA_PIN_CFG(0, 0x05, 0x185600f0),
AZALIA_PIN_CFG(0, 0x06, 0x185600f0),
AZALIA_PIN_CFG(0, 0x07, 0x185600f0),
};
const u32 pc_beep_verbs[] = {};
AZALIA_ARRAY_SIZES;
#endif

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src/mainboard/system76/addw2/ramstage.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootstate.h>
#include <console/console.h>
#include <device/pci.h>
#include <soc/ramstage.h>
#include "gpio.h"
void mainboard_silicon_init_params(FSP_S_CONFIG *params)
{
/* Configure pads prior to SiliconInit() in case there's any
* dependencies during hardware initialization. */
cnl_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
}
static void dgpu_read_resources(struct device *dev) {
printk(BIOS_INFO, "system76: dgpu_read_resources %s\n", dev_path(dev));
pci_dev_read_resources(dev);
int bar;
// Find all BARs on DGPU, mark them above 4g if prefetchable
for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
printk(BIOS_INFO, " BAR at 0x%02x\n", bar);
struct resource *res;
res = probe_resource(dev, bar);
if (res) {
if (res->flags & IORESOURCE_PREFETCH) {
printk(BIOS_INFO, " marked above 4g\n");
res->flags |= IORESOURCE_ABOVE_4G;
} else {
printk(BIOS_INFO, " not prefetch\n");
}
} else {
printk(BIOS_INFO, " not found\n");
}
}
}
static struct device_operations dgpu_pci_ops_dev = {
.read_resources = dgpu_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
#if CONFIG(HAVE_ACPI_TABLES)
.write_acpi_tables = pci_rom_write_acpi_tables,
.acpi_fill_ssdt = pci_rom_ssdt,
#endif
.init = pci_dev_init,
.ops_pci = &pci_dev_ops_pci,
};
static void dgpu_above_4g(void *unused) {
struct device *pdev;
// Find PEG0
pdev = pcidev_on_root(1, 0);
if (!pdev) {
printk(BIOS_ERR, "system76: failed to find PEG0\n");
return;
}
printk(BIOS_INFO, "system76: PEG0 at %p, %04x:%04x\n", pdev, pdev->vendor, pdev->device);
int fn;
for (fn = 0; fn < 8; fn++) {
struct device *dev;
// Find DGPU functions
dev = pcidev_path_behind(pdev->link_list, PCI_DEVFN(0, fn));
if (dev) {
printk(BIOS_INFO, "system76: DGPU fn %d at %p, %04x:%04x\n", fn, dev, dev->vendor, dev->device);
dev->ops = &dgpu_pci_ops_dev;
} else {
printk(BIOS_ERR, "system76: failed to find DGPU fn %d\n", fn);
}
}
}
BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_ENTRY, dgpu_above_4g, NULL);

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src/mainboard/system76/addw2/romstage.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/cnl_memcfg_init.h>
#include <soc/romstage.h>
static const struct cnl_mb_cfg memcfg = {
/* Parameters required to access SPD for CH0D0/CH0D1/CH1D0/CH1D1. */
.spd[0] = {
.read_type = READ_SMBUS,
.spd_spec = {.spd_smbus_address = 0xa0},
},
.spd[1] = {.read_type = NOT_EXISTING},
.spd[2] = {
.read_type = READ_SMBUS,
.spd_spec = {.spd_smbus_address = 0xa4},
},
.spd[3] = {.read_type = NOT_EXISTING},
/*
* For each channel, there are 3 sets of DQ byte mappings,
* where each set has a package 0 and a package 1 value (package 0
* represents the first 64-bit lpddr4 chip combination, and package 1
* represents the second 64-bit lpddr4 chip combination).
* The first three sets are for CLK, CMD, and CTL.
* The fsp package actually expects 6 sets, but the last 3 sets are
* not used in CNL, so we only define the three sets that are used
* and let the meminit_lpddr4() routine take care of clearing the
* unused fields for the caller.
*/
.dq_map[DDR_CH0] = {
{0x0F, 0xF0}, {0x00, 0xF0}, {0x0F, 0xF0},
//{0x0F, 0x00}, {0xFF, 0x00}, {0xFF, 0x00}
},
.dq_map[DDR_CH1] = {
{0x33, 0xCC}, {0x00, 0xCC}, {0x33, 0xCC},
//{0x33, 0x00}, {0xFF, 0x00}, {0xFF, 0x00}
},
/*
* DQS CPU<>DRAM map Ch0 and Ch1. Each array entry represents a
* mapping of a dq bit on the CPU to the bit it's connected to on
* the memory part. The array index represents the dqs bit number
* on the memory part, and the values in the array represent which
* pin on the CPU that DRAM pin connects to.
*/
.dqs_map[DDR_CH0] = {0, 1, 2, 3, 4, 5, 6, 7},
.dqs_map[DDR_CH1] = {0, 1, 2, 3, 4, 5, 6, 7},
/*
* Rcomp resistor values. These values represent the resistance in
* ohms of the three rcomp resistors attached to the DDR_COMP_0,
* DDR_COMP_1, and DDR_COMP_2 pins on the DRAM.
*/
.rcomp_resistor = { 121, 75, 100 },
/*
* Rcomp target values. These will typically be the following
* values for Cannon Lake : { 80, 40, 40, 40, 30 }
*/
.rcomp_targets = { 50, 25, 20, 20, 26 },
/*
* Indicates whether memory is interleaved.
* Set to 1 for an interleaved design,
* set to 0 for non-interleaved design.
*/
.dq_pins_interleaved = 1,
/*
* VREF_CA configuration.
* Set to 0 VREF_CA goes to both CH_A and CH_B,
* set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B,
* set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B.
*/
.vref_ca_config = 2,
/* Early Command Training */
.ect = 0,
};
void mainboard_memory_init_params(FSPM_UPD *memupd)
{
// Set primary display to internal graphics
memupd->FspmConfig.PrimaryDisplay = 0;
cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
}