Docs: Fix broken header references

MyST Parser automatically generates label "slugs" for headers which
should be used to reference them from links [1]. These labels are in
"slug-case", i.e. the original header text in lower case separated by
dashes, with punctuation removed. This fixes a few "cross-reference
target not found" warnings.

[1] https://myst-parser.readthedocs.io/en/latest/syntax/optional.html#anchor-slug-structure

Change-Id: Ia6970d03b961bde6d7cd0fa3297f8d84b75d3b34
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

Documentation/mainboard/lenovo/Ivy_Bridge_series.md

@@ -82,7 +82,7 @@ It is possible to reduce the Intel ME firmware size to free additional
 space for the `bios` region. This is usually referred to as *cleaning the ME* or
 *stripping the ME*.
 After reducing the Intel ME firmware size you must modify the original IFD,
-[split the resulting coreboot ROM](#splitting-the-coreboot-rom) and then write
+[split the resulting coreboot ROM](#splitting-the-corebootrom) and then write
 each ROM using an [external programmer].
 Have a look at [me_cleaner] for more information.
 

Documentation/northbridge/intel/sandybridge/nri_freq.md

@@ -160,7 +160,7 @@ As you can see, by using DIMMs with different maximum DRAM frequencies, the
 slowest DIMMs' frequency will be selected, to prevent over-clocking it.
 
 The selected frequency gives the PLL multiplier to operate at. In case the PLL
-locks (see Take me to [Hard fuses](#hard_fuses)) the frequency will be used for
+locks (see Take me to [Hard fuses](#hard-fuses)) the frequency will be used for
 all DIMMs. At this point it's not possible to change the multiplier again,
 until the system has been powered off. In case the PLL doesn't lock, the next
 smaller multiplier will be used until a working multiplier will be found.

Documentation/releases/coreboot-4.13-relnotes.md

@@ -214,7 +214,7 @@ Deprecations
 
 In order to minimize the usage of PCI bus mastering, the options we introduced in
 this release will be dropped in a future release again. For more details, please
-see [Preparations to minimize enabling PCI bus mastering](#preparations-to-minimize-enabling-pci-bus-mastering-in-coreboot).
+see [Preparations to minimize enabling PCI bus mastering](#preparations-to-minimize-enabling-pci-bus-mastering).
 
 ### Resource allocator v3
 

Documentation/superio/nuvoton/npcd378.md

@@ -78,7 +78,7 @@ Looks like a WDT.
 ### LDN8
 
 Custom HWM space. It exposes 256 byte of IO config space.
-See [HWM](#HWM) for more details.
+See [HWM](#hwm) for more details.
 
 ## HWM