sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/fsp_baytrail: Rework acpi/cpu.asl

Browse Source 
Use acpigen_write_processor_cnot to implement notifications to the CPU.

Change-Id: I01e4397b9a1c15eff4b856cbc697fa2b4bc9761f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Arthur Heymans
2018-11-28 13:58:57 +01:00
committed by Duncan Laurie
parent c9c5e84d6f
commit cf9fc1ddfe
2 changed files with 15 additions and 44 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
src/soc/intel/fsp_baytrail/acpi.c
View File

@@ -524,6 +524,13 @@ void generate_cpu_entries(struct device *device)
acpigen_pop_len(); acpigen_pop_len();
} }
/* PPKG is usually used for thermal management
of the first and only package. */
acpigen_write_processor_package("PPKG", 0, pattrs->num_cpus);
/* Add a method to notify processor nodes */
acpigen_write_processor_cnot(pattrs->num_cpus);
} }
unsigned long acpi_madt_irq_overrides(unsigned long current) unsigned long acpi_madt_irq_overrides(unsigned long current)

52
src/soc/intel/fsp_baytrail/acpi/cpu.asl
View File

@@ -14,59 +14,23 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
/* These devices are created at runtime */ /* These come from the dynamically created CPU SSDT */
External (\_PR.CP00, DeviceObj) External (\_PR.CNOT, MethodObj)
External (\_PR.CP01, DeviceObj)
External (\_PR.CP02, DeviceObj)
External (\_PR.CP03, DeviceObj)
/* Notify OS to re-read CPU tables, assuming ^2 CPU count */ /* Notify OS to re-read CPU tables */
Method (PNOT) Method (PNOT)
{ {
If (LGreaterEqual (\PCNT, 2)) { \_PR.CNOT (0x81)
Notify (\_PR.CP00, 0x81) // _CST
Notify (\_PR.CP01, 0x81) // _CST
}
If (LGreaterEqual (\PCNT, 4)) {
Notify (\_PR.CP02, 0x81) // _CST
Notify (\_PR.CP03, 0x81) // _CST
}
} }
/* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */ /* Notify OS to re-read CPU _PPC limit */
Method (PPCN) Method (PPCN)
{ {
If (LGreaterEqual (\PCNT, 2)) { \_PR.CNOT (0x80)
Notify (\_PR.CP00, 0x80) // _PPC
Notify (\_PR.CP01, 0x80) // _PPC
}
If (LGreaterEqual (\PCNT, 4)) {
Notify (\_PR.CP02, 0x80) // _PPC
Notify (\_PR.CP03, 0x80) // _PPC
}
} }
/* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */ /* Notify OS to re-read Throttle Limit tables */
Method (TNOT) Method (TNOT)
{ {
If (LGreaterEqual (\PCNT, 2)) { \_PR.CNOT (0x82)
Notify (\_PR.CP00, 0x82) // _TPC
Notify (\_PR.CP01, 0x82) // _TPC
}
If (LGreaterEqual (\PCNT, 4)) {
Notify (\_PR.CP02, 0x82) // _TPC
Notify (\_PR.CP03, 0x82) // _TPC
}
}
/* Return a package containing enabled processor entries */
Method (PPKG)
{
If (LGreaterEqual (\PCNT, 4)) {
Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03})
} ElseIf (LGreaterEqual (\PCNT, 2)) {
Return (Package() {\_PR.CP00, \_PR.CP01})
} Else {
Return (Package() {\_PR.CP00})
}
} }