nb/intel/ironlake/raminit_heci.c: Move to southbridge scope
HECI stuff is in the southbridge, so put the code in there. Rename the file to match the name of the function it provides. Change-Id: I71de1234547dbd46a9b4959c619d2ae194da620a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Angel Pons
Felix Held
@@ -11,7 +11,6 @@ ramstage-y += gma.c
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romstage-y += memmap.c
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romstage-y += raminit.c
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romstage-y += raminit_heci.c
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romstage-y += raminit_tables.c
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romstage-y += early_init.c
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romstage-y += romstage.c
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@@ -106,6 +106,4 @@ u16 get_max_timing(struct raminfo *info, int channel);
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void early_quickpath_init(struct raminfo *info, const u8 x2ca8);
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void late_quickpath_init(struct raminfo *info, const int s3resume);
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void setup_heci_uma(u64 heci_uma_addr, unsigned int heci_uma_size);
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#endif /* RAMINIT_H */
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@@ -1,223 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <device/mmio.h>
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#include <device/pci_def.h>
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#include <device/pci_ops.h>
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#include <northbridge/intel/ironlake/raminit.h>
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#include <southbridge/intel/ibexpeak/me.h>
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#include <types.h>
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#define HECIDEV PCI_DEV(0, 0x16, 0)
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/* FIXME: add timeout. */
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static void wait_heci_ready(void)
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{
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while (!(read32(DEFAULT_HECIBAR + 0xc) & 8)) // = 0x8000000c
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;
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write32((DEFAULT_HECIBAR + 0x4), (read32(DEFAULT_HECIBAR + 0x4) & ~0x10) | 0xc);
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}
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/* FIXME: add timeout. */
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static void wait_heci_cb_avail(int len)
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{
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union {
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struct mei_csr csr;
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u32 raw;
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} csr;
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while (!(read32(DEFAULT_HECIBAR + 0xc) & 8))
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;
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do {
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csr.raw = read32(DEFAULT_HECIBAR + 0x4);
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} while (len > csr.csr.buffer_depth - (csr.csr.buffer_write_ptr -
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csr.csr.buffer_read_ptr));
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}
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static void send_heci_packet(struct mei_header *head, u32 *payload)
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{
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int len = (head->length + 3) / 4;
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int i;
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wait_heci_cb_avail(len + 1);
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/* FIXME: handle leftovers correctly. */
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write32(DEFAULT_HECIBAR + 0, *(u32 *) head);
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for (i = 0; i < len - 1; i++)
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write32(DEFAULT_HECIBAR + 0, payload[i]);
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write32(DEFAULT_HECIBAR + 0, payload[i] & ((1 << (8 * len)) - 1));
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write32(DEFAULT_HECIBAR + 0x4, read32(DEFAULT_HECIBAR + 0x4) | 0x4);
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}
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static void send_heci_message(u8 *msg, int len, u8 hostaddress, u8 clientaddress)
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{
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struct mei_header head;
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int maxlen;
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wait_heci_ready();
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maxlen = (read32(DEFAULT_HECIBAR + 0x4) >> 24) * 4 - 4;
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while (len) {
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int cur = len;
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if (cur > maxlen) {
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cur = maxlen;
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head.is_complete = 0;
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} else
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head.is_complete = 1;
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head.length = cur;
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head.reserved = 0;
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head.client_address = clientaddress;
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head.host_address = hostaddress;
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send_heci_packet(&head, (u32 *) msg);
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len -= cur;
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msg += cur;
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}
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}
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/* FIXME: Add timeout. */
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static int recv_heci_packet(struct mei_header *head, u32 *packet, u32 *packet_size)
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{
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union {
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struct mei_csr csr;
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u32 raw;
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} csr;
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int i = 0;
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write32(DEFAULT_HECIBAR + 0x4, read32(DEFAULT_HECIBAR + 0x4) | 2);
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do {
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csr.raw = read32(DEFAULT_HECIBAR + 0xc);
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} while (csr.csr.buffer_write_ptr == csr.csr.buffer_read_ptr);
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*(u32 *) head = read32(DEFAULT_HECIBAR + 0x8);
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if (!head->length) {
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write32(DEFAULT_HECIBAR + 0x4, read32(DEFAULT_HECIBAR + 0x4) | 2);
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*packet_size = 0;
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return 0;
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}
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if (head->length + 4 > 4 * csr.csr.buffer_depth || head->length > *packet_size) {
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*packet_size = 0;
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return -1;
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}
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do {
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csr.raw = read32(DEFAULT_HECIBAR + 0xc);
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} while (((head->length + 3) >> 2) >
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(csr.csr.buffer_write_ptr - csr.csr.buffer_read_ptr));
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for (i = 0; i < (head->length + 3) >> 2; i++)
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packet[i++] = read32(DEFAULT_HECIBAR + 0x8);
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*packet_size = head->length;
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if (!csr.csr.ready)
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*packet_size = 0;
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write32(DEFAULT_HECIBAR + 0x4, read32(DEFAULT_HECIBAR + 0x4) | 4);
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return 0;
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}
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union uma_reply {
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struct {
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u8 group_id;
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u8 command;
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u8 reserved;
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u8 result;
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u8 field2;
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u8 unk3[0x48 - 4 - 1];
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};
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u32 dwords[0x48 / sizeof(u32)];
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} __packed;
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/* FIXME: Add timeout. */
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static int recv_heci_message(union uma_reply *message, u32 *message_size)
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{
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struct mei_header head;
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int current_position;
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current_position = 0;
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while (1) {
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u32 current_size;
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current_size = *message_size - current_position;
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if (recv_heci_packet
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(&head, &message->dwords[current_position / sizeof(u32)],
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¤t_size) == -1)
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break;
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if (!current_size)
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break;
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current_position += current_size;
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if (head.is_complete) {
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*message_size = current_position;
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return 0;
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}
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if (current_position >= *message_size)
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break;
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}
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*message_size = 0;
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return -1;
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}
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static void send_heci_uma_message(const u64 heci_uma_addr, const unsigned int heci_uma_size)
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{
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union uma_reply reply;
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struct uma_message {
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u8 group_id;
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u8 cmd;
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u8 reserved;
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u8 result;
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u32 c2;
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u64 heci_uma_addr;
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u32 heci_uma_size;
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u16 c3;
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} __packed msg = {
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.group_id = 0,
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.cmd = MKHI_SET_UMA,
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.reserved = 0,
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.result = 0,
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.c2 = 0x82,
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.heci_uma_addr = heci_uma_addr,
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.heci_uma_size = heci_uma_size,
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.c3 = 0,
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};
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u32 reply_size;
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send_heci_message((u8 *) &msg, sizeof(msg), 0, 7);
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reply_size = sizeof(reply);
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if (recv_heci_message(&reply, &reply_size) == -1)
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return;
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if (reply.command != (MKHI_SET_UMA | (1 << 7)))
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die("HECI init failed\n");
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}
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void setup_heci_uma(u64 heci_uma_addr, unsigned int heci_uma_size)
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{
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if (!heci_uma_size && !(pci_read_config32(HECIDEV, 0x40) & 0x20))
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return;
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if (heci_uma_size) {
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dmibar_clrbits32(DMIVC0RCTL, 1 << 7);
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RCBA32(0x14) &= ~0x80;
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dmibar_clrbits32(DMIVC1RCTL, 1 << 7);
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RCBA32(0x20) &= ~0x80;
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dmibar_clrbits32(DMIVCPRCTL, 1 << 7);
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RCBA32(0x30) &= ~0x80;
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dmibar_clrbits32(DMIVCMRCTL, 1 << 7);
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RCBA32(0x40) &= ~0x80;
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RCBA32(0x40) = 0x87000080; // OK
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dmibar_write32(DMIVCMRCTL, 0x87000080); // OK
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while ((RCBA16(0x46) & 2) && dmibar_read16(DMIVCMRSTS) & VCMNP)
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;
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}
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mchbar_write32(0x24, 0x10000 + heci_uma_size);
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send_heci_uma_message(heci_uma_addr, heci_uma_size);
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pci_write_config32(HECIDEV, 0x10, 0x0);
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pci_write_config8(HECIDEV, 0x4, 0x0);
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}
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