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soc/intel/alderlake: Set Base Addresses for TBT DMA remapping engines

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The patch configures 4KB memory region window for each of the TBT DMA
remapping engine. So, the remap engines map their register set to
the respective 4KB window.

TEST=Verified boot on Brya

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I669255065d60d73c4bea0eeb732c4114bcc447c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55015
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sridhar Siricilla 2021-05-28 20:00:02 +05:30 committed by Subrata Banik
parent b67c5edf82
commit d047927168
1 changed files with 19 additions and 0 deletions
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19
src/soc/intel/alderlake/romstage/fsp_params.c
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@ -32,6 +32,10 @@ enum vtd_base_index_type {
VTD_GFX,
VTD_IPU,
VTD_VTVCO,
VTD_TBT0,
VTD_TBT1,
VTD_TBT2,
VTD_TBT3,
};
static uint8_t clk_src_to_fsp(enum pcie_rp_type type, int rp_number)
@ -228,6 +232,21 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
printk(BIOS_ERR, "ERROR: Requested VT-d, but VTVCO_BASE_ADDRESS is 0\n");
}
if (m_cfg->TcssDma0En || m_cfg->TcssDma1En)
m_cfg->VtdItbtEnable = 1;
if (m_cfg->TcssItbtPcie0En)
m_cfg->VtdBaseAddress[VTD_TBT0] = TBT0_BASE_ADDRESS;
if (m_cfg->TcssItbtPcie1En)
m_cfg->VtdBaseAddress[VTD_TBT1] = TBT1_BASE_ADDRESS;
if (m_cfg->TcssItbtPcie2En)
m_cfg->VtdBaseAddress[VTD_TBT2] = TBT2_BASE_ADDRESS;
if (m_cfg->TcssItbtPcie3En)
m_cfg->VtdBaseAddress[VTD_TBT3] = TBT3_BASE_ADDRESS;
/* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */
m_cfg->VmxEnable = CONFIG(ENABLE_VMX);
/* Skip CPU replacement check */