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mb/system76/adl-p: galp6: Fix PCIe port registers

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Correct the PCH PCIe RP indexes, which were copied from darp8.

Fixes using Ethernet and the SD card reader.

Change-Id: If14dea0492f6b7bea62d482ab970fe43e17c107b
Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Tim Crawford
2022-08-02 13:19:41 -06:00
parent 57eae8e37a
commit d2a57693df
1 changed files with 2 additions and 2 deletions
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4
src/mainboard/system76/adl-p/variants/galp6/overridetree.cb
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@@ -151,7 +151,7 @@ chip soc/intel/alderlake
end
device ref pcie_rp9 on
# PCIe RP#9 x1, Clock 5 (CARD)
register "pch_pcie_rp[PCH_RP(6)]" = "{
register "pch_pcie_rp[PCH_RP(9)]" = "{
.clk_src = 5,
.clk_req = 5,
.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
@@ -159,7 +159,7 @@ chip soc/intel/alderlake
end
device ref pcie_rp10 on
# PCIe RP#10 x1, Clock 6 (GLAN)
register "pch_pcie_rp[PCH_RP(8)]" = "{
register "pch_pcie_rp[PCH_RP(10)]" = "{
.clk_src = 6,
.clk_req = 6,
.flags = PCIE_RP_LTR | PCIE_RP_AER,