mb/system76/gaze17: Enable dGPU

Change-Id: I08781b6e91917b8ca92fc216c580befdd75cb994
Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Tim Crawford
2022-07-24 15:33:11 -06:00
parent ef3ef9b9b7
commit d4407b563f
6 changed files with 44 additions and 1 deletions

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@@ -3,6 +3,7 @@ if BOARD_SYSTEM76_GAZE17_3050 || BOARD_SYSTEM76_GAZE17_3060_B
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_32768
select DRIVERS_GFX_NVIDIA
select DRIVERS_I2C_HID
select EC_SYSTEM76_EC
select EC_SYSTEM76_EC_COLOR_KEYBOARD

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@@ -1,5 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <variant/gpio.h>
#define EC_GPE_SCI 0x6E
#define EC_GPE_SWI 0x6B
#include <ec/system76/ec/acpi/ec.asl>
@@ -8,5 +10,8 @@ Scope (\_SB) {
#include "sleep.asl"
Scope (PCI0) {
#include "backlight.asl"
Scope (PEG2) {
#include <drivers/gfx/nvidia/acpi/tigerlake.asl>
}
}
}

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@@ -60,13 +60,19 @@ chip soc/intel/alderlake
device domain 0 on
#From CPU EDS(TODO)
device ref system_agent on end
device ref pcie5 off
device ref pcie5 on
# PCIe PEG2 x8, Clock 3 (DGPU)
register "cpu_pcie_rp[CPU_RP(2)]" = "{
.clk_src = 3,
.clk_req = 3,
.flags = PCIE_RP_LTR,
}"
chip drivers/gfx/nvidia
device pci 00.0 on end # VGA controller
device pci 00.1 on end # Audio device
device pci 00.2 on end # USB xHCI Host controller
device pci 00.3 on end # USB Type-C UCSI controller
end
end
device ref tcss_xhci on
register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"

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@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <drivers/gfx/nvidia/gpu.h>
#include <fsp/util.h>
#include <soc/meminit.h>
#include <soc/romstage.h>
@@ -24,6 +25,18 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
{
const bool half_populated = false;
const struct nvidia_gpu_config config = {
.power_gpio = DGPU_PWR_EN,
.reset_gpio = DGPU_RST_N,
.enable = true,
};
// Enable dGPU power
nvidia_set_power(&config);
// Set primary display to internal graphics
mupd->FspmConfig.PrimaryDisplay = 0;
// Enable audio link
mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1;

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@@ -3,7 +3,16 @@
#ifndef VARIANT_GPIO_H
#define VARIANT_GPIO_H
#include <soc/gpio.h>
#define DGPU_RST_N GPP_B2
#define DGPU_PWR_EN GPP_A14
#define DGPU_GC6 GPP_F13
#define DGPU_SSID 0x866d1558
#ifndef __ACPI__
void variant_configure_early_gpios(void);
void variant_configure_gpios(void);
#endif
#endif

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@@ -3,7 +3,16 @@
#ifndef VARIANT_GPIO_H
#define VARIANT_GPIO_H
#include <soc/gpio.h>
#define DGPU_RST_N GPP_B2
#define DGPU_PWR_EN GPP_A14
#define DGPU_GC6 GPP_F13
#define DGPU_SSID 0x867c1558
#ifndef __ACPI__
void variant_configure_early_gpios(void);
void variant_configure_gpios(void);
#endif
#endif