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AMD Rev F support

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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Yinghai Lu 2006-10-04 20:46:15 +00:00
parent 2e3757d11c
commit d4b278c02c
130 changed files with 11668 additions and 657 deletions
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42
src/arch/i386/Config.lb
View File

@ -1,9 +1,25 @@
uses CONFIG_SMP
uses CONFIG_PRECOMPRESSED_ROM_STREAM
uses CONFIG_USE_INIT
uses HAVE_FAILOVER_BOOT
uses USE_FAILOVER_IMAGE
uses USE_FALLBACK_IMAGE
init init/crt0.S.lb
ldscript init/ldscript.lb
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
ldscript init/ldscript_failover.lb
else
ldscript init/ldscript.lb
end
else
if USE_FALLBACK_IMAGE
ldscript init/ldscript_fallback.lb
else
ldscript init/ldscript.lb
end
end
makerule all
depends "linuxbios.rom"
@ -21,7 +37,7 @@ end
makerule payload
depends "$(PAYLOAD)"
action "cp -f $< $@"
action "cp $< $@"
end
makerule payload.nrv2b
@ -53,9 +69,19 @@ if CONFIG_PRECOMPRESSED_ROM_STREAM
makedefine PAYLOAD-1:=payload
end
makerule linuxbios.rom
depends "linuxbios.strip buildrom $(PAYLOAD-1)"
action "./buildrom $< $@ $(PAYLOAD-1) $(ROM_IMAGE_SIZE) $(ROM_SECTION_SIZE)"
if USE_FAILOVER_IMAGE
makedefine LINUXBIOS_APC:=
makedefine LINUXBIOS_RAM_ROM:=
makerule linuxbios.rom
depends "linuxbios.strip"
action "cp $< $@"
end
else
makerule linuxbios.rom
depends "linuxbios.strip buildrom $(PAYLOAD-1)"
action "./buildrom $< $@ $(PAYLOAD-1) $(ROM_IMAGE_SIZE) $(ROM_SECTION_SIZE)"
end
end
makerule crt0.S
@ -72,11 +98,11 @@ if CONFIG_USE_INIT
action "$(OBJCOPY) --rename-section .text=.init.text --rename-section .data=.init.data --rename-section .rodata=.init.rodata --rename-section .rodata.str1.1=.init.rodata.str1.1 init.pre.o init.o"
end
makerule linuxbios
depends "crt0.o init.o linuxbios_ram.rom ldscript.ld"
makerule linuxbios
depends "crt0.o $(INIT-OBJECTS) $(LINUXBIOS_APC) $(LINUXBIOS_RAM_ROM) ldscript.ld"
action "$(CC) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld crt0.o init.o"
action "$(CROSS_COMPILE)nm -n linuxbios | sort > linuxbios.map"
end
end
end

25
src/arch/i386/boot/acpi.c
View File

@ -203,6 +203,31 @@ void acpi_create_srat(acpi_srat_t *srat)
header->checksum = acpi_checksum((void *)srat, header->length);
}
void acpi_create_slit(acpi_slit_t *slit)
{
acpi_header_t *header=&(slit->header);
unsigned long current=(unsigned long)slit+sizeof(acpi_slit_t);
memset((void *)slit, 0, sizeof(acpi_slit_t));
/* fill out header fields */
memcpy(header->signature, SLIT_NAME, 4);
memcpy(header->oem_id, OEM_ID, 6);
memcpy(header->oem_table_id, SLIT_TABLE, 8);
memcpy(header->asl_compiler_id, ASLC, 4);
header->length = sizeof(acpi_slit_t);
header->revision = 1;
// current = acpi_fill_slit(current);
/* recalculate length */
header->length= current - (unsigned long)slit;
header->checksum = acpi_checksum((void *)slit, header->length);
}
void acpi_create_hpet(acpi_hpet_t *hpet)
{
#define HPET_ADDR 0xfed00000ULL

21
src/arch/i386/include/arch/acpi.h
View File

@ -6,12 +6,9 @@
*
* The ACPI table structs are based on the Linux kernel sources.
*
* ACPI FADT & FACS added by Nick Barker <nick.barker9@btinternet.com>
*/
/* ACPI FADT & FACS added by Nick Barker <nick.barker9@btinternet.com>
* those parts (C) 2004 Nick Barker
*
* ACPI SRAT support added in 2005.9 by yhlu
* Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
*
*/
@ -32,11 +29,13 @@ typedef unsigned long long u64;
#define HPET_NAME "HPET"
#define MADT_NAME "APIC"
#define SRAT_NAME "SRAT"
#define SLIT_NAME "SLIT"
#define RSDT_TABLE "RSDT "
#define HPET_TABLE "AMD64 "
#define MADT_TABLE "MADT "
#define SRAT_TABLE "SRAT "
#define SLIT_TABLE "SLIT "
#define OEM_ID "LXBIOS"
#define ASLC "NONE"
@ -49,7 +48,7 @@ typedef struct acpi_rsdp {
char oem_id[6]; /* OEM ID, "LXBIOS" */
u8 revision; /* 0 for APCI 1.0, 2 for ACPI 2.0 */
u32 rsdt_address; /* physical address of RSDT */
u32 length; /* total length of RSDP (incl. extended part) */
u32 length; /* total length of RSDP (including extended part) */
u64 xsdt_address; /* physical address of XSDT */
u8 ext_checksum; /* chechsum of whole table */
u8 reserved[3];
@ -84,16 +83,15 @@ typedef struct acpi_table_header /* ACPI common table header */
/* RSDT */
typedef struct acpi_rsdt {
struct acpi_table_header header;
u32 entry[5+ACPI_SSDTX_NUM]; /* HPET, FADT, SRAT, MADT(APIC), SSDT, SSDTX */
u32 entry[6+ACPI_SSDTX_NUM]; /* HPET, FADT, SRAT, SLIT, MADT(APIC), SSDT, SSDTX*/
} __attribute__ ((packed)) acpi_rsdt_t;
/* XSDT */
typedef struct acpi_xsdt {
struct acpi_table_header header;
u64 entry[5+ACPI_SSDTX_NUM];
u64 entry[6+ACPI_SSDTX_NUM];
} __attribute__ ((packed)) acpi_xsdt_t;
/* HPET TIMERS */
typedef struct acpi_hpet {
struct acpi_table_header header;
@ -138,6 +136,11 @@ typedef struct acpi_srat_mem {
u32 resv2[2];
} __attribute__ ((packed)) acpi_srat_mem_t;
/* SLIT */
typedef struct acpi_slit {
struct acpi_table_header header;
/* followed by static resource allocation 8+byte[num*num]*/
} __attribute__ ((packed)) acpi_slit_t;
/* MADT */

19
src/arch/i386/include/arch/cpu.h
View File

@ -141,6 +141,25 @@ static inline unsigned long cpu_index(void)
return ci->index;
}
struct cpuinfo_x86 {
uint8_t x86; /* CPU family */
uint8_t x86_vendor; /* CPU vendor */
uint8_t x86_model;
uint8_t x86_mask;
};
static void inline get_fms(struct cpuinfo_x86 *c, uint32_t tfms)
{
c->x86 = (tfms >> 8) & 0xf;
c->x86_model = (tfms >> 4) & 0xf;
c->x86_mask = tfms & 0xf;
if (c->x86 == 0xf)
c->x86 += (tfms >> 20) & 0xff;
if (c->x86 >= 0x6)
c->x86_model += ((tfms >> 16) & 0xF) << 4;
}
#endif
#endif /* ARCH_CPU_H */

152
src/arch/i386/include/arch/romcc_io.h
View File

@ -4,74 +4,35 @@
#include <stdint.h>
static inline uint8_t read8(unsigned long addr)
static inline __attribute__((always_inline)) uint8_t read8(unsigned long addr)
{
return *((volatile uint8_t *)(addr));
}
static inline uint16_t read16(unsigned long addr)
static inline __attribute__((always_inline)) uint16_t read16(unsigned long addr)
{
return *((volatile uint16_t *)(addr));
}
static inline uint32_t read32(unsigned long addr)
static inline __attribute__((always_inline)) uint32_t read32(unsigned long addr)
{
return *((volatile uint32_t *)(addr));
}
static inline void write8(unsigned long addr, uint8_t value)
static inline __attribute__((always_inline)) void write8(unsigned long addr, uint8_t value)
{
*((volatile uint8_t *)(addr)) = value;
}
static inline void write16(unsigned long addr, uint16_t value)
static inline __attribute__((always_inline)) void write16(unsigned long addr, uint16_t value)
{
*((volatile uint16_t *)(addr)) = value;
}
static inline void write32(unsigned long addr, uint32_t value)
static inline __attribute__((always_inline)) void write32(unsigned long addr, uint32_t value)
{
*((volatile uint32_t *)(addr)) = value;
}
#if 0
typedef __builtin_div_t div_t;
typedef __builtin_ldiv_t ldiv_t;
typedef __builtin_udiv_t udiv_t;
typedef __builtin_uldiv_t uldiv_t;
static inline div_t div(int numer, int denom)
{
return __builtin_div(numer, denom);
}
static inline ldiv_t ldiv(long numer, long denom)
{
return __builtin_ldiv(numer, denom);
}
static inline udiv_t udiv(unsigned numer, unsigned denom)
{
return __builtin_udiv(numer, denom);
}
static inline uldiv_t uldiv(unsigned long numer, unsigned long denom)
{
return __builtin_uldiv(numer, denom);
}
inline int log2(int value)
{
/* __builtin_bsr is a exactly equivalent to the x86 machine
* instruction with the exception that it returns -1
* when the value presented to it is zero.
* Otherwise __builtin_bsr returns the zero based index of
* the highest bit set.
*/
return __builtin_bsr(value);
}
#endif
static inline int log2(int value)
{
@ -98,16 +59,16 @@ static inline int log2f(int value)
}
#define PCI_ADDR(BUS, DEV, FN, WHERE) ( \
(((BUS) & 0xFF) << 16) | \
(((DEV) & 0x1f) << 11) | \
(((FN) & 0x07) << 8) | \
((WHERE) & 0xFF))
#define PCI_ADDR(SEGBUS, DEV, FN, WHERE) ( \
(((SEGBUS) & 0xFFF) << 20) | \
(((DEV) & 0x1F) << 15) | \
(((FN) & 0x07) << 12) | \
((WHERE) & 0xFFF))
#define PCI_DEV(BUS, DEV, FN) ( \
(((BUS) & 0xFF) << 16) | \
(((DEV) & 0x1f) << 11) | \
(((FN) & 0x7) << 8))
#define PCI_DEV(SEGBUS, DEV, FN) ( \
(((SEGBUS) & 0xFFF) << 20) | \
(((DEV) & 0x1F) << 15) | \
(((FN) & 0x07) << 12))
#define PCI_ID(VENDOR_ID, DEVICE_ID) \
((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF))
@ -117,58 +78,103 @@ static inline int log2f(int value)
typedef unsigned device_t;
static inline __attribute__((always_inline)) uint8_t pci_read_config8(device_t dev, unsigned where)
static inline __attribute__((always_inline)) uint8_t pci_io_read_config8(device_t dev, unsigned where)
{
unsigned addr;
addr = dev | where;
addr = (dev>>4) | where;
outl(0x80000000 | (addr & ~3), 0xCF8);
return inb(0xCFC + (addr & 3));
}
static inline __attribute__((always_inline)) uint16_t pci_read_config16(device_t dev, unsigned where)
static inline __attribute__((always_inline)) uint8_t pci_read_config8(device_t dev, unsigned where)
{
return pci_io_read_config8(dev, where);
}
static inline __attribute__((always_inline)) uint16_t pci_io_read_config16(device_t dev, unsigned where)
{
unsigned addr;
addr = dev | where;
addr = (dev>>4) | where;
outl(0x80000000 | (addr & ~3), 0xCF8);
return inw(0xCFC + (addr & 2));
}
static inline __attribute__((always_inline)) uint32_t pci_read_config32(device_t dev, unsigned where)
static inline __attribute__((always_inline)) uint16_t pci_read_config16(device_t dev, unsigned where)
{
return pci_io_read_config16(dev, where);
}
static inline __attribute__((always_inline)) uint32_t pci_io_read_config32(device_t dev, unsigned where)
{
unsigned addr;
addr = dev | where;
addr = (dev>>4) | where;
outl(0x80000000 | (addr & ~3), 0xCF8);
return inl(0xCFC);
}
static inline __attribute__((always_inline)) void pci_write_config8(device_t dev, unsigned where, uint8_t value)
static inline __attribute__((always_inline)) uint32_t pci_read_config32(device_t dev, unsigned where)
{
return pci_io_read_config32(dev, where);
}
static inline __attribute__((always_inline)) void pci_io_write_config8(device_t dev, unsigned where, uint8_t value)
{
unsigned addr;
addr = dev | where;
addr = (dev>>4) | where;
outl(0x80000000 | (addr & ~3), 0xCF8);
outb(value, 0xCFC + (addr & 3));
}
static inline __attribute__((always_inline)) void pci_write_config16(device_t dev, unsigned where, uint16_t value)
static inline __attribute__((always_inline)) void pci_write_config8(device_t dev, unsigned where, uint8_t value)
{
unsigned addr;
addr = dev | where;
outl(0x80000000 | (addr & ~3), 0xCF8);
outw(value, 0xCFC + (addr & 2));
pci_io_write_config8(dev, where, value);
}
static inline __attribute__((always_inline)) void pci_write_config32(device_t dev, unsigned where, uint32_t value)
static inline __attribute__((always_inline)) void pci_io_write_config16(device_t dev, unsigned where, uint16_t value)
{
unsigned addr;
addr = (dev>>4) | where;
outl(0x80000000 | (addr & ~3), 0xCF8);
outw(value, 0xCFC + (addr & 2));
}
static inline __attribute__((always_inline)) void pci_write_config16(device_t dev, unsigned where, uint16_t value)
{
pci_io_write_config16(dev, where, value);
}
static inline __attribute__((always_inline)) void pci_io_write_config32(device_t dev, unsigned where, uint32_t value)
{
unsigned addr;
addr = dev | where;
addr = (dev>>4) | where;
outl(0x80000000 | (addr & ~3), 0xCF8);
outl(value, 0xCFC);
}
static inline __attribute__((always_inline)) void pci_write_config32(device_t dev, unsigned where, uint32_t value)
{
pci_io_write_config32(dev, where, value);
}
#define PCI_DEV_INVALID (0xffffffffU)
static device_t pci_io_locate_device(unsigned pci_id, device_t dev)
{
for(; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) {
unsigned int id;
id = pci_io_read_config32(dev, 0);
if (id == pci_id) {
return dev;
}
}
return PCI_DEV_INVALID;
}
static device_t pci_locate_device(unsigned pci_id, device_t dev)
{
for(; dev <= PCI_DEV(CONFIG_MAX_PCI_BUSES, 31, 7); dev += PCI_DEV(0,0,1)) {
for(; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) {
unsigned int id;
id = pci_read_config32(dev, 0);
if (id == pci_id) {
@ -180,11 +186,11 @@ static device_t pci_locate_device(unsigned pci_id, device_t dev)
static device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus)
{
device_t dev, last;
device_t dev, last;
dev = PCI_DEV(bus, 0, 0);
last = PCI_DEV(bus, 31, 7);
for(; dev <=last; dev += PCI_DEV(0,0,1)) {
unsigned int id;
id = pci_read_config32(dev, 0);
@ -195,8 +201,6 @@ static device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus)
return PCI_DEV_INVALID;
}
/* Generic functions for pnp devices */
static inline __attribute__((always_inline)) void pnp_write_config(device_t dev, uint8_t reg, uint8_t value)
{

5
src/arch/i386/init/ldscript.lb
View File

@ -36,16 +36,13 @@ INPUT(linuxbios_ram.rom)
SECTIONS
{
. = _ROMBASE;
.ram . : {
_ram = . ;
linuxbios_ram.rom(*)
_eram = . ;
}
_x = .;
. = (_x < (_ROMBASE - 0x10000 + ROM_IMAGE_SIZE)) ? (_ROMBASE - 0x10000 + ROM_IMAGE_SIZE) : _x;
/* This section might be better named .setup */
.rom . : {
_rom = .;

13
src/arch/i386/init/ldscript_apc.lb Normal file
View File

@ -0,0 +1,13 @@
INPUT(linuxbios_apc.rom)
SECTIONS
{
.apcrom . : {
_apcrom = .;
linuxbios_apc.rom(*)
_eapcrom = .;
}
_iseg_apc = DCACHE_RAM_BASE;
_eiseg_apc = _iseg_apc + SIZEOF(.apcrom);
_liseg_apc = _apcrom;
_eliseg_apc = _eapcrom;
}

56
src/arch/i386/init/ldscript_failover.lb Normal file
View File

@ -0,0 +1,56 @@
/*
* Memory map:
*
* _RAMBASE
* : data segment
* : bss segment
* : heap
* : stack
* _ROMBASE
* : linuxbios text
* : readonly text
*/
/*
* Bootstrap code for the STPC Consumer
* Copyright (c) 1999 by Net Insight AB. All Rights Reserved.
*
*/
/*
* Written by Johan Rydberg, based on work by Daniel Kahlin.
* Rewritten by Eric Biederman
*/
/*
* We use ELF as output format. So that we can
* debug the code in some form.
*/
OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
OUTPUT_ARCH(i386)
/*
ENTRY(_start)
*/
TARGET(binary)
SECTIONS
{
. = _ROMBASE;
/* This section might be better named .setup */
.rom . : {
_rom = .;
*(.rom.text);
*(.rom.data);
*(.rom.data.*);
. = ALIGN(16);
_erom = .;
}
_lrom = LOADADDR(.rom);
_elrom = LOADADDR(.rom) + SIZEOF(.rom);
/DISCARD/ : {
*(.comment)
*(.note)
}
}

71
src/arch/i386/init/ldscript_fallback.lb Normal file
View File

@ -0,0 +1,71 @@
/*
* Memory map:
*
* _RAMBASE
* : data segment
* : bss segment
* : heap
* : stack
* _ROMBASE
* : linuxbios text
* : readonly text
*/
/*
* Bootstrap code for the STPC Consumer
* Copyright (c) 1999 by Net Insight AB. All Rights Reserved.
*
*/
/*
* Written by Johan Rydberg, based on work by Daniel Kahlin.
* Rewritten by Eric Biederman
*/
/*
* We use ELF as output format. So that we can
* debug the code in some form.
*/
OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
OUTPUT_ARCH(i386)
/*
ENTRY(_start)
*/
TARGET(binary)
INPUT(linuxbios_ram.rom)
SECTIONS
{
. = _ROMBASE;
.ram . : {
_ram = . ;
linuxbios_ram.rom(*)
_eram = . ;
}
/* cut _start into last 64k*/
_x = .;
. = (_x < (_ROMBASE - 0x10000 + ROM_IMAGE_SIZE)) ? (_ROMBASE - 0x10000 + ROM_IMAGE_SIZE) : _x;
/* This section might be better named .setup */
.rom . : {
_rom = .;
*(.rom.text);
*(.rom.data);
*(.rom.data.*);
. = ALIGN(16);
_erom = .;
}
_lrom = LOADADDR(.rom);
_elrom = LOADADDR(.rom) + SIZEOF(.rom);
_iseg = _RAMBASE;
_eiseg = _iseg + SIZEOF(.ram);
_liseg = _ram;
_eliseg = _eram;
/DISCARD/ : {
*(.comment)
*(.note)
}
}

7
src/arch/i386/lib/cpu.c
View File

@ -222,6 +222,8 @@ void cpu_initialize(void)
*/
struct device *cpu;
struct cpu_info *info;
struct cpuinfo_x86 c;
info = cpu_info();
printk_notice("Initializing CPU #%d\n", info->index);
@ -245,6 +247,11 @@ void cpu_initialize(void)
identify_cpu(cpu);
printk_debug("CPU: vendor %s device %x\n",
cpu_vendor_name(cpu->vendor), cpu->device);
get_fms(&c, cpu->device);
printk_debug("CPU: family %02x, model %02x, stepping %02x\n", c.x86, c.x86_model, c.x86_mask);
/* Lookup the cpu's operations */
set_cpu_ops(cpu);

36
src/arch/i386/lib/pci_ops_conf1.c
View File

@ -10,40 +10,40 @@
#define CONFIG_CMD(bus,devfn, where) (0x80000000 | (bus << 16) | (devfn << 8) | (where & ~3))
static uint8_t pci_conf1_read_config8(struct bus *pbus, unsigned char bus, int devfn, int where)
static uint8_t pci_conf1_read_config8(struct bus *pbus, int bus, int devfn, int where)
{
outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
return inb(0xCFC + (where & 3));
outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
return inb(0xCFC + (where & 3));
}
static uint16_t pci_conf1_read_config16(struct bus *pbus, unsigned char bus, int devfn, int where)
static uint16_t pci_conf1_read_config16(struct bus *pbus, int bus, int devfn, int where)
{
outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
return inw(0xCFC + (where & 2));
outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
return inw(0xCFC + (where & 2));
}
static uint32_t pci_conf1_read_config32(struct bus *pbus, unsigned char bus, int devfn, int where)
static uint32_t pci_conf1_read_config32(struct bus *pbus, int bus, int devfn, int where)
{
outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
return inl(0xCFC);
outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
return inl(0xCFC);
}
static void pci_conf1_write_config8(struct bus *pbus, unsigned char bus, int devfn, int where, uint8_t value)
static void pci_conf1_write_config8(struct bus *pbus, int bus, int devfn, int where, uint8_t value)
{
outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
outb(value, 0xCFC + (where & 3));
outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
outb(value, 0xCFC + (where & 3));
}
static void pci_conf1_write_config16(struct bus *pbus, unsigned char bus, int devfn, int where, uint16_t value)
static void pci_conf1_write_config16(struct bus *pbus, int bus, int devfn, int where, uint16_t value)
{
outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
outw(value, 0xCFC + (where & 2));
outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
outw(value, 0xCFC + (where & 2));
}
static void pci_conf1_write_config32(struct bus *pbus, unsigned char bus, int devfn, int where, uint32_t value)
static void pci_conf1_write_config32(struct bus *pbus, int bus, int devfn, int where, uint32_t value)
{
outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
outl(value, 0xCFC);
outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
outl(value, 0xCFC);
}
#undef CONFIG_CMD

12
src/arch/i386/lib/pci_ops_conf2.c
View File

@ -12,7 +12,7 @@
#define FUNC(devfn) (((devfn & 7) << 1) | 0xf0)
#define SET(bus,devfn) outb(FUNC(devfn), 0xCF8); outb(bus, 0xCFA);
static uint8_t pci_conf2_read_config8(struct bus *pbus, unsigned char bus, int devfn, int where)
static uint8_t pci_conf2_read_config8(struct bus *pbus, int bus, int devfn, int where)
{
uint8_t value;
SET(bus, devfn);
@ -21,7 +21,7 @@ static uint8_t pci_conf2_read_config8(struct bus *pbus, unsigned char bus, int d
return value;
}
static uint16_t pci_conf2_read_config16(struct bus *pbus, unsigned char bus, int devfn, int where)
static uint16_t pci_conf2_read_config16(struct bus *pbus, int bus, int devfn, int where)
{
uint16_t value;
SET(bus, devfn);
@ -30,7 +30,7 @@ static uint16_t pci_conf2_read_config16(struct bus *pbus, unsigned char bus, int
return value;
}
static uint32_t pci_conf2_read_config32(struct bus *pbus, unsigned char bus, int devfn, int where)
static uint32_t pci_conf2_read_config32(struct bus *pbus, int bus, int devfn, int where)
{
uint32_t value;
SET(bus, devfn);
@ -39,21 +39,21 @@ static uint32_t pci_conf2_read_config32(struct bus *pbus, unsigned char bus, int
return value;
}
static void pci_conf2_write_config8(struct bus *pbus, unsigned char bus, int devfn, int where, uint8_t value)
static void pci_conf2_write_config8(struct bus *pbus, int bus, int devfn, int where, uint8_t value)
{
SET(bus, devfn);
outb(value, IOADDR(devfn, where));
outb(0, 0xCF8);
}
static void pci_conf2_write_config16(struct bus *pbus, unsigned char bus, int devfn, int where, uint16_t value)
static void pci_conf2_write_config16(struct bus *pbus, int bus, int devfn, int where, uint16_t value)
{
SET(bus, devfn);
outw(value, IOADDR(devfn, where));
outb(0, 0xCF8);
}
static void pci_conf2_write_config32(struct bus *pbus, unsigned char bus, int devfn, int where, uint32_t value)
static void pci_conf2_write_config32(struct bus *pbus, int bus, int devfn, int where, uint32_t value)
{
SET(bus, devfn);
outl(value, IOADDR(devfn, where));

68
src/config/Config.lb
View File

@ -1,6 +1,7 @@
## This is Architecture independant part of the makefile
uses HAVE_OPTION_TABLE
uses CONFIG_AP_CODE_IN_CAR
makedefine CPP:= $(CC) -x assembler-with-cpp -DASSEMBLY -E
makedefine LIBGCC_FILE_NAME := $(shell $(CC) -print-libgcc-file-name)
@ -31,6 +32,12 @@ makerule linuxbios.strip
action "$(OBJCOPY) -O binary linuxbios linuxbios.strip"
end
makerule linuxbios.a
depends "$(OBJECTS)"
action "rm -f linuxbios.a"
action "ar cr linuxbios.a $(OBJECTS)"
end
makerule linuxbios_ram.o
depends "$(DRIVER) linuxbios.a $(LIBGCC_FILE_NAME)"
action "$(CC) -nostdlib -r -o $@ c_start.o $(DRIVER) linuxbios.a $(LIBGCC_FILE_NAME)"
@ -63,16 +70,59 @@ makerule linuxbios_ram.rom
action "cp $(LINUXBIOS_RAM-1) linuxbios_ram.rom"
end
makerule linuxbios
depends "crt0.o $(INIT-OBJECTS) linuxbios_ram.rom ldscript.ld"
action "$(CC) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld crt0.o $(INIT-OBJECTS)"
action "$(CROSS_COMPILE)nm -n linuxbios | sort > linuxbios.map"
makedefine LINUXBIOS_APC:=
if CONFIG_AP_CODE_IN_CAR
#for ap code in cache
makerule linuxbios_apc.a
depends "apc_auto.o"
action "rm -f linuxbios_apc.a"
action "ar cr linuxbios_apc.a apc_auto.o"
end
makerule linuxbios_apc.o
depends "linuxbios_apc.a c_start.o $(LIBGCC_FILE_NAME)"
action "$(CC) -nostdlib -r -o $@ c_start.o linuxbios_apc.a $(LIBGCC_FILE_NAME)"
end
makerule linuxbios_apc
depends "linuxbios_apc.o $(TOP)/src/config/linuxbios_apc.ld ldoptions"
action "$(CC) -nostdlib -nostartfiles -static -o $@ -T $(TOP)/src/config/linuxbios_apc.ld linuxbios_apc.o"
action "$(CROSS_COMPILE)nm -n linuxbios_apc | sort > linuxbios_apc.map"
end
##
## By default compress the part of linuxbios that runs from cache as ram
##
makedefine LINUXBIOS_APC-$(CONFIG_COMPRESS):=linuxbios_apc.nrv2b
makedefine LINUXBIOS_APC-$(CONFIG_UNCOMPRESSED):=linuxbios_apc.bin
makerule linuxbios_apc.bin
depends "linuxbios_apc"
action "$(OBJCOPY) -O binary $< $@"
end
makerule linuxbios_apc.nrv2b
depends "linuxbios_apc.bin nrv2b"
action "./nrv2b e $< $@"
end
makerule linuxbios_apc.rom
depends "$(LINUXBIOS_APC-1)"
action "cp $(LINUXBIOS_APC-1) linuxbios_apc.rom"
end
makedefine LINUXBIOS_APC:=linuxbios_apc.rom
end
makerule linuxbios.a
depends "$(OBJECTS)"
action "rm -f linuxbios.a"
action "ar cr linuxbios.a $(OBJECTS)"
makedefine LINUXBIOS_RAM_ROM:=linuxbios_ram.rom
makerule linuxbios
depends "crt0.o $(INIT-OBJECTS) $(LINUXBIOS_APC) $(LINUXBIOS_RAM_ROM) ldscript.ld"
action "$(CC) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld crt0.o $(INIT-OBJECTS)"
action "$(CROSS_COMPILE)nm -n linuxbios | sort > linuxbios.map"
end
#makerule crt0.S
@ -159,7 +209,7 @@ makerule clean
action "rm -f ldscript.ld"
action "rm -f a.out *.s *.l *.o *.E *.inc"
action "rm -f TAGS tags romcc*"
action "rm -f docipl buildrom* chips.c *chip.c linuxbios_ram* linuxbios_pay*"
action "rm -f docipl buildrom* chips.c *chip.c linuxbios_apc* linuxbios_ram* linuxbios_pay*"
action "rm -f build_opt_tbl* nrv2b* option_table.c crt0.S"
end

86
src/config/Options.lb
View File

@ -178,18 +178,36 @@ define HAVE_FALLBACK_BOOT
export always
comment "Set if fallback booting required"
end
define HAVE_FAILOVER_BOOT
format "%d"
default 0
export always
comment "Set if failover booting required"
end
define USE_FALLBACK_IMAGE
format "%d"
default 0
export used
comment "Set to build a fallback image"
end
define USE_FAILOVER_IMAGE
format "%d"
default 0
export used
comment "Set to build a failover image"
end
define FALLBACK_SIZE
default 65536
format "0x%x"
export used
comment "Default fallback image size"
end
define FAILOVER_SIZE
default 0
format "0x%x"
export used
comment "Default failover image size"
end
define ROM_SIZE
default none
format "0x%x"
@ -274,9 +292,9 @@ define USE_DCACHE_RAM
comment "Use data cache as temporary RAM if possible"
end
define DCACHE_RAM_BASE
default none
default 0xc0000
format "0x%x"
export used
export always
comment "Base address of data cache when using it for temporary RAM"
end
define DCACHE_RAM_SIZE
@ -291,6 +309,21 @@ define DCACHE_RAM_GLOBAL_VAR_SIZE
export always
comment "Size of region that for global variable of cache as ram stage"
end
define CONFIG_AP_CODE_IN_CAR
default 0
export always
comment "will copy linuxbios_apc to AP cache ane execute in AP"
end
define MEM_TRAIN_SEQ
default 0
export always
comment "0: three for in bsp, 1: on every core0, 2: one for on bsp"
end
define WAIT_BEFORE_CPUS_INIT
default 0
export always
comment "execute cpus_ready_for_init if it is set to 1"
end
define XIP_ROM_BASE
default 0
format "0x%x"
@ -853,7 +886,7 @@ end
define HT_CHAIN_UNITID_BASE
default 1
export always
comment "first hypertransport device's unitid base. if southbridge ht chain only has one ht device, it could be 0"
comment "this will be first hypertransport device's unitid base, if sb ht chain only has one ht device, it could be 0"
end
define HT_CHAIN_END_UNITID_BASE
@ -868,30 +901,67 @@ define SB_HT_CHAIN_UNITID_OFFSET_ONLY
comment "this will decided if only offset SB hypertransport chain"
end
define K8_SB_HT_CHAIN_ON_BUS0
define SB_HT_CHAIN_ON_BUS0
default 0
export always
comment "this will make SB hypertransport chain sit on bus 0, if it is 2 will put other chain on 0x40, 0x80, 0xc0"
comment "this will make SB hypertransport chain sit on bus 0, if it is 1, will put sb ht chain on bus 0, if it is 2 will put other chain on 0x40, 0x80, 0xc0"
end
define K8_HW_MEM_HOLE_SIZEK
define HW_MEM_HOLE_SIZEK
default 0
export always
comment "Opteron E0 later memory hole size in K, 0 mean disable"
end
define K8_HW_MEM_HOLE_SIZE_AUTO_INC
define HW_MEM_HOLE_SIZE_AUTO_INC
default 0
export always
comment "Opteron E0 later memory hole size auto increase to avoid hole startk equal to basek"
end
define K8_HT_FREQ_1G_SUPPORT
default 0
default 0
export always
comment "Optern E0 later could support 1G HT, but still depends MB design"
end
define K8_REV_F_SUPPORT
default 0
export always
comment "Opteron Rev F (DDR2) support"
end
define CBB
default 0
export always
comment "Opteron cpu bus num base"
end
define CDB
default 0x18
export always
comment "Opteron cpu device num base"
end
define DIMM_SUPPORT
default 0x0108
format "0x%x"
export always
comment "DIMM support: bit 0 - sdram, bit 1: ddr1, bit 2: ddr2, bit 3: ddr3, bit 4: fbdimm, bit 8: reg"
end
define CPU_SOCKET_TYPE
default 0x10
export always
comment "cpu socket type, 0x10 mean Socket F, 0x11 mean socket M2, 0x20, Soxket G, and 0x21 mean socket M3"
end
define CPU_ADDR_BITS
default 36
export always
comment "CPU hardware address lines num, for AMD K8 could be 40, and GH could be 48"
end
define CONFIG_PCI_ROM_RUN
default 0
export always

2
src/config/linuxbios_ram.ld
View File

@ -109,7 +109,7 @@ SECTIONS
_ram_seg = _text;
_eram_seg = _eheap;
_bogus = ASSERT( ((_eram_seg>>10)<CONFIG_LB_MEM_TOPK) , "please increase CONFIG_LB_MEM_TOPK");
_bogus = ASSERT( ( (_eram_seg>>10) < (CONFIG_LB_MEM_TOPK)) , "please increase CONFIG_LB_MEM_TOPK");
_bogus = ASSERT( !((CONFIG_CONSOLE_VGA || CONFIG_PCI_ROM_RUN) && ((_ram_seg<0xa0000) && (_eram_seg>0xa0000))) , "please increase CONFIG_LB_MEM_TOPK and if still fail, try to set _RAMBASE more than 1M");

47
src/cpu/amd/car/cache_as_ram.inc
View File

@ -17,7 +17,7 @@
cache_as_ram_setup:
/* hope we can skip the double set for normal part */
#if USE_FALLBACK_IMAGE == 1
#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE==1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE==1))
/* check if cpu_init_detected */
movl $MTRRdefType_MSR, %ecx
rdmsr
@ -56,16 +56,32 @@ clear_fixed_var_mtrr_out:
wrmsr
movl $0x269, %ecx
wrmsr
#else
#endif
#if CacheSize == 0x8000
#if CacheSize == 0xc000
/* enable caching for 16K using fixed mtrr */
movl $0x268, %ecx /* fix4k_c4000*/
movl $0x06060606, %edx /* WB IO type */
xorl %eax, %eax
wrmsr
/* enable caching for 32K using fixed mtrr */
movl $0x269, %ecx /* fix4k_c8000*/
movl $0x06060606, %eax /* WB IO type */
movl %eax, %edx
wrmsr
#endif
#if CacheSize == 0x8000
/* enable caching for 32K using fixed mtrr */
movl $0x269, %ecx /* fix4k_c8000*/
movl $0x06060606, %eax /* WB IO type */
movl %eax, %edx
wrmsr
#else
#endif
#if CacheSize < 0x8000
/* enable caching for 16K/8K/4K using fixed mtrr */
movl $0x269, %ecx /* fix4k_cc000*/
#if CacheSize == 0x4000
@ -79,8 +95,6 @@ clear_fixed_var_mtrr_out:
#endif
xorl %eax, %eax
wrmsr
#endif
#endif
/* enable memory access for first MBs using top_mem */
@ -88,9 +102,10 @@ clear_fixed_var_mtrr_out:
xorl %edx, %edx
movl $(((CONFIG_LB_MEM_TOPK << 10) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax
wrmsr
#endif /* USE_FALLBACK_IMAGE == 1*/
#endif /* USE_FAILOVER_IMAGE == 1*/
#if USE_FALLBACK_IMAGE == 0
#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 0)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE==0))
/* disable cache */
movl %cr0, %eax
orl $(0x1<<30),%eax
@ -108,12 +123,12 @@ clear_fixed_var_mtrr_out:
wrmsr
movl $0x203, %ecx
movl $0x0000000f, %edx /* AMD 40 bit */
movl $((1<<(CPU_ADDR_BITS-32))-1), %edx /* AMD 40 bit */
movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax
wrmsr
#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */
#if USE_FALLBACK_IMAGE == 1
#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE==1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE==1))
/* Set the default memory type and enable fixed and variable MTRRs */
movl $MTRRdefType_MSR, %ecx
xorl %edx, %edx
@ -133,23 +148,25 @@ clear_fixed_var_mtrr_out:
andl $0x9fffffff,%eax
movl %eax, %cr0
#if USE_FALLBACK_IMAGE == 1
#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE==1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE==1))
/* Read the range with lodsl*/
cld
movl $CacheBase, %esi
movl $(CacheSize>>2), %ecx
rep lodsl
rep
lodsl
/* Clear the range */
movl $CacheBase, %edi
movl $(CacheSize>>2), %ecx
xorl %eax, %eax
rep stosl
rep
stosl
#endif /*USE_FALLBACK_IMAGE == 1*/
#endif /*USE_FAILOVER_IMAGE == 1*/
/* set up the stack pointer */
movl $(CacheBase+CacheSize - 4 - GlobalVarSize), %eax
movl $(CacheBase+CacheSize - GlobalVarSize), %eax
movl %eax, %esp
/* Restore the BIST result */

60
src/cpu/amd/car/copy_and_run.c
View File

@ -2,7 +2,6 @@
moved from nrv2v.c and some lines from crt0.S
2006/05/02 - stepan: move nrv2b to an extra file.
*/
static inline void print_debug_cp_run(const char *strval, uint32_t val)
{
#if CONFIG_USE_INIT
@ -46,8 +45,13 @@ static void copy_and_run(void)
print_debug_cp_run("src=",(uint32_t)src);
print_debug_cp_run("dst=",(uint32_t)dst);
olen = unrv2b(src, dst);
// dump_mem(src, src+0x100);
olen = unrv2b(src, dst, &ilen);
print_debug_cp_run("linxbios_ram.nrv2b length = ", ilen);
#endif
// dump_mem(dst, dst+0x100);
print_debug_cp_run("linxbios_ram.bin length = ", olen);
@ -61,3 +65,55 @@ static void copy_and_run(void)
);
}
#if CONFIG_AP_CODE_IN_CAR == 1
static void copy_and_run_ap_code_in_car(unsigned ret_addr)
{
uint8_t *src, *dst;
unsigned long ilen, olen;
// print_debug("Copying LinuxBIOS AP code to CAR.\r\n");
#if !CONFIG_COMPRESS
__asm__ volatile (
"leal _liseg_apc, %0\n\t"
"leal _iseg_apc, %1\n\t"
"leal _eiseg_apc, %2\n\t"
"subl %1, %2\n\t"
: "=a" (src), "=b" (dst), "=c" (olen)
);
memcpy(dst, src, olen);
#else
__asm__ volatile (
"leal _liseg_apc, %0\n\t"
"leal _iseg_apc, %1\n\t"
: "=a" (src) , "=b" (dst)
);
// print_debug_cp_run("src=",(uint32_t)src);
// print_debug_cp_run("dst=",(uint32_t)dst);
// dump_mem(src, src+0x100);
olen = unrv2b(src, dst, &ilen);
// print_debug_cp_run("linxbios_apc.nrv2b length = ", ilen);
#endif
// dump_mem(dst, dst+0x100);
// print_debug_cp_run("linxbios_apc.bin length = ", olen);
// print_debug("Jumping to LinuxBIOS AP code in CAR.\r\n");
__asm__ volatile (
"movl %0, %%ebp\n\t" /* cpu_reset for hardwaremain dummy */
"cli\n\t"
"leal _iseg_apc, %%edi\n\t"
"jmp *%%edi\n\t"
:: "a"(ret_addr)
);
}
#endif

34
src/cpu/amd/car/post_cache_as_ram.c
View File

@ -18,12 +18,13 @@ static void inline __attribute__((always_inline)) memcopy(void *dest, const voi
{
__asm__ volatile(
"cld\n\t"
"rep movsl\n\t"
"rep; movsl\n\t"
: /* No outputs */
: "S" (src), "D" (dest), "c" ((bytes)>>2)
);
}
static void post_cache_as_ram(void)
{
@ -49,24 +50,34 @@ static void post_cache_as_ram(void)
#error "You need to set CONFIG_LB_MEM_TOPK greater than 1024"
#endif
set_init_ram_access();
set_init_ram_access(); /* So we can access RAM from [1M, CONFIG_LB_MEM_TOPK) */
// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x8000, DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x7c00);
print_debug("Copying data from cache to ram -- switching to use ram as stack... ");
/* from here don't store more data in CAR */
#if 0
__asm__ volatile (
"pushl %eax\n\t"
);
memcopy((CONFIG_LB_MEM_TOPK<<10)-DCACHE_RAM_SIZE, DCACHE_RAM_BASE, DCACHE_RAM_SIZE); //inline
#endif
memcopy((void *)((CONFIG_LB_MEM_TOPK<<10)-DCACHE_RAM_SIZE), (void *)DCACHE_RAM_BASE, DCACHE_RAM_SIZE); //inline
// dump_mem((CONFIG_LB_MEM_TOPK<<10) - 0x8000, (CONFIG_LB_MEM_TOPK<<10) - 0x7c00);
__asm__ volatile (
/* set new esp */ /* before _RAMBASE */
"subl %0, %%ebp\n\t"
"subl %0, %%esp\n\t"
::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- (CONFIG_LB_MEM_TOPK<<10) )
); // We need to push %eax to the stack (CAR) before copy stack and pop it later after copy stack and change esp
#if 0
__asm__ volatile (
"popl %eax\n\t"
);
#endif
/* We can put data to stack again */
/* only global variable sysinfo in cache need to be offset */
@ -77,14 +88,27 @@ static void post_cache_as_ram(void)
disable_cache_as_ram_bsp();
print_debug("Clearing initial memory region: ");
clear_init_ram(); //except the range from [(CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_SIZE, (CONFIG_LB_MEM_TOPK<<10)), that is used as stack in ram
clear_init_ram(); //except the range from [(CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_SIZE, (CONFIG_LB_MEM_TOPK<<10))
print_debug("Done\r\n");
// dump_mem((CONFIG_LB_MEM_TOPK<<10) - 0x8000, (CONFIG_LB_MEM_TOPK<<10) - 0x7c00);
#ifndef MEM_TRAIN_SEQ
#define MEM_TRAIN_SEQ 0
#endif
set_sysinfo_in_ram(1); // So other core0 could start to train mem
#if MEM_TRAIN_SEQ == 1
// struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE);
// wait for ap memory to trained
// wait_all_core0_mem_trained(sysinfox); // moved to lapic_init_cpus.c
#endif
/*copy and execute linuxbios_ram */
copy_and_run();
/* We will not return */
print_debug("should not be here -\r\n");
print_debug("should not be here -\r\n");
}

10
src/cpu/amd/dualcore/amd_sibling.c
View File

@ -11,6 +11,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/amd/model_fxx_msr.h>
#include <cpu/amd/model_fxx_rev.h>
#include <cpu/amd/amdk8_sysconf.h>
static int first_time = 1;
static int disable_siblings = !CONFIG_LOGICAL_CPUS;
@ -168,6 +169,15 @@ void amd_sibling_init(device_t cpu)
/* Build the cpu device path */
cpu_path.type = DEVICE_PATH_APIC;
cpu_path.u.apic.apic_id = cpu->path.u.apic.apic_id + i * (nb_cfg_54?1:8);
if(id.nodeid == 0) {
// need some special processing, because may the bsp is not lifted, but the core1 is lifted
//defined in northbridge.c
if(sysconf.enabled_apic_ext_id && (!sysconf.lift_bsp_apicid)) {
cpu->path.u.apic.apic_id += sysconf.apicid_offset;
}
}
/* See if I can find the cpu */
new = find_dev_path(cpu->bus, &cpu_path);

2
src/cpu/amd/dualcore/dualcore.c
View File

@ -19,7 +19,9 @@ static inline unsigned get_core_num_in_bsp(unsigned nodeid)
#if SET_NB_CFG_54 == 1
static inline uint8_t set_apicid_cpuid_lo(void)
{
#if K8_REV_F_SUPPORT == 0
if(is_cpu_pre_e0()) return 0; // pre_e0 can not be set
#endif
// set the NB_CFG[54]=1; why the OS will be happy with that ???
msr_t msr;

10
src/cpu/amd/dualcore/dualcore_id.c
View File

@ -20,6 +20,8 @@ static inline unsigned get_initial_apicid(void)
}
//called by amd_siblings too
#define CORE_ID_BIT 1
#define NODE_ID_BIT 3
struct node_core_id get_node_core_id(unsigned nb_cfg_54)
{
struct node_core_id id;
@ -27,15 +29,15 @@ struct node_core_id get_node_core_id(unsigned nb_cfg_54)
if( nb_cfg_54) {
// when NB_CFG[54] is set, nodeid = ebx[27:25], coreid = ebx[24]
id.coreid = (cpuid_ebx(1) >> 24) & 0xf;
id.nodeid = (id.coreid>>1);
id.coreid &= 1;
id.nodeid = (id.coreid>>CORE_ID_BIT);
id.coreid &= ((1<<CORE_ID_BIT)-1);
}
else
{
// when NB_CFG[54] is clear, nodeid = ebx[26:24], coreid = ebx[27]
id.nodeid = (cpuid_ebx(1) >> 24) & 0xf;
id.coreid = (id.nodeid>>3);
id.nodeid &= 7;
id.coreid = (id.nodeid>>NODE_ID_BIT);
id.nodeid &= ((1<<NODE_ID_BIT)-1);
}
return id;
}

3
src/cpu/amd/model_fxx/Config.lb
View File

@ -1,7 +1,10 @@
uses HAVE_INIT_TIMER
uses HAVE_MOVNTI
uses CPU_ADDR_BITS
default HAVE_INIT_TIMER=1
default HAVE_MOVNTI=1
default CPU_ADDR_BITS=40
dir /cpu/x86/tsc
dir /cpu/x86/fpu
dir /cpu/x86/mmx

78
src/cpu/amd/model_fxx/fidvid.c
View File

@ -4,6 +4,12 @@
#define K8_SET_FIDVID_STORE_AP_APICID_AT_FIRST 1
#ifndef SB_VFSMAF
#define SB_VFSMAF 1
#endif
#define FX_SUPPORT 1
static inline void print_debug_fv(const char *str, unsigned val)
{
#if K8_SET_FIDVID_DEBUG == 1
@ -59,7 +65,7 @@ static void enable_fid_change(void)
dword |= (1<<14);// disable the DRAM interface at first, it will be enabled by raminit again
pci_write_config32(PCI_DEV(0, 0x18+i, 2), 0x94, dword);
dword = 0x23070000; //enable FID/VID change
dword = 0x23070700; //enable FID/VID change
// dword = 0x00070000; //enable FID/VID change
pci_write_config32(PCI_DEV(0, 0x18+i, 3), 0x80, dword);
@ -122,13 +128,27 @@ static unsigned set_fidvid(unsigned apicid, unsigned fidvid, int showmessage)
if((vid_cur==vid) && (fid_cur==fid)) return fidvid;
vid_max = (msr.hi>>(48-32)) & 0x3f;
fid_max = (msr.lo>>16) & 0x3f;
fid_max = ((msr.lo>>16) & 0x3f); //max fid
#if FX_SUPPORT
if(fid_max>=((25-4)*2)) { // FX max fid is 5G
fid_max = ((msr.lo>>8) & 0x3f) + 5*2; // max FID is min fid + 1G
if(fid_max >= ((25-4)*2)) {
fid_max = (10-4)*2; // hard set to 2G
}
}
#endif
//set vid to max
msr.hi = 1;
msr.lo = (vid_max<<8) | (fid_cur);
#if SB_VFSMAF == 1
msr.lo |= (1<<16); // init changes
#endif
wrmsr(0xc0010041, msr);
#if SB_VFSMAF == 0
ldtstop_sb();
#endif
for(loop=0;loop<100000;loop++){
msr = rdmsr(0xc0010042);
@ -159,8 +179,13 @@ static unsigned set_fidvid(unsigned apicid, unsigned fidvid, int showmessage)
//set target fid
msr.hi = (100000/5);
msr.lo = (vid_cur<<8) | fid_cur;
#if SB_VFSMAF == 1
msr.lo |= (1<<16); // init changes
#endif
wrmsr(0xc0010041, msr);
#if SB_VFSMAF == 0
ldtstop_sb();
#endif
#if K8_SET_FIDVID_DEBUG == 1
@ -186,8 +211,13 @@ static unsigned set_fidvid(unsigned apicid, unsigned fidvid, int showmessage)
//set vid to final
msr.hi = 1;
msr.lo = (vid<<8) | (fid_cur);
#if SB_VFSMAF == 1
msr.lo |= (1<<16); // init changes
#endif
wrmsr(0xc0010041, msr);
#if SB_VFSMAF == 0
ldtstop_sb();
#endif
for(loop=0;loop<100000;loop++){
msr = rdmsr(0xc0010042);
@ -215,10 +245,21 @@ static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid)
msr_t msr;
uint32_t vid_cur;
uint32_t fid_cur;
uint32_t fid_max;
int loop;
msr = rdmsr(0xc0010042);
send = ((msr.lo>>16) & 0x3f) << 8; //max fid
fid_max = ((msr.lo>>16) & 0x3f); //max fid
#if FX_SUPPORT
if(fid_max>=((25-4)*2)) { // FX max fid is 5G
fid_max = ((msr.lo>>8) & 0x3f) + 5*2; // max FID is min fid + 1G
if(fid_max >= ((25-4)*2)) {
fid_max = (10-4)*2; // hard set to 2G
}
}
#endif
send = fid_max<<8;
send |= ((msr.hi>>(48-32)) & 0x3f) << 16; //max vid
send |= (apicid<<24); // ap apicid
@ -342,6 +383,14 @@ static void init_fidvid_bsp(unsigned bsp_apicid)
msr_t msr;
msr = rdmsr(0xc0010042);
fid_max = ((msr.lo>>16) & 0x3f); //max fid
#if FX_SUPPORT == 1
if(fid_max>=((25-4)*2)) { // FX max fid is 5G
fid_max = ((msr.lo>>8) & 0x3f) + 5*2; // max FID is min fid + 1G
if(fid_max >= ((25-4)*2)) {
fid_max = (10-4)*2; // hard set to 2G
}
}
#endif
vid_max = ((msr.hi>>(48-32)) & 0x3f); //max vid
fv.common_fidvid = (fid_max<<8)|(vid_max<<16);
@ -366,6 +415,29 @@ static void init_fidvid_bsp(unsigned bsp_apicid)
#endif
#if 0
unsigned fid, vid;
// Can we use max only? So we can only set fid in one around, otherwise we need to set that to max after raminit
// set fid vid to DQS training required
fid = (fv.common_fidvid >> 8) & 0x3f;
vid = (fv.common_fidvid >> 16) & 0x3f;
if(fid>(10-4)*2) {
fid = (10-4)*2; //x10
}
if(vid>=0x1f) {
vid+= 4; //unit is 12.5mV
} else {
vid+= 2; //unit is 25mV
}
fv.common_fidvid = (fid<<8) | (vid<<16);
print_debug_fv("common_fidvid=", fv.common_fidvid);
#endif
// set BSP fid and vid
print_debug_fv("bsp apicid=", bsp_apicid);
fv.common_fidvid = set_fidvid(bsp_apicid, fv.common_fidvid, 1);

107
src/cpu/amd/model_fxx/init_cpus.c
View File

@ -1,6 +1,12 @@
//it takes the ENABLE_APIC_EXT_ID and APIC_ID_OFFSET and LIFT_BSP_APIC_ID
#ifndef K8_SET_FIDVID
#define K8_SET_FIDVID 0
#if K8_REV_F_SUPPORT == 0
#define K8_SET_FIDVID 0
#else
// for rev F, need to set FID to max
#define K8_SET_FIDVID 1
#endif
#endif
#ifndef K8_SET_FIDVID_CORE0_ONLY
@ -8,6 +14,43 @@
#define K8_SET_FIDVID_CORE0_ONLY 1
#endif
static inline void print_initcpu8 (const char *strval, unsigned val)
{
#if CONFIG_USE_INIT
printk_debug("%s%02x\r\n", strval, val);
#else
print_debug(strval); print_debug_hex8(val); print_debug("\r\n");
#endif
}
static inline void print_initcpu8_nocr (const char *strval, unsigned val)
{
#if CONFIG_USE_INIT
printk_debug("%s%02x", strval, val);
#else
print_debug(strval); print_debug_hex8(val);
#endif
}
static inline void print_initcpu16 (const char *strval, unsigned val)
{
#if CONFIG_USE_INIT
printk_debug("%s%04x\r\n", strval, val);
#else
print_debug(strval); print_debug_hex16(val); print_debug("\r\n");
#endif
}
static inline void print_initcpu(const char *strval, unsigned val)
{
#if CONFIG_USE_INIT
printk_debug("%s%08x\r\n", strval, val);
#else
print_debug(strval); print_debug_hex32(val); print_debug("\r\n");
#endif
}
typedef void (*process_ap_t)(unsigned apicid, void *gp);
//core_range = 0 : all cores
@ -44,7 +87,11 @@ static void for_each_ap(unsigned bsp_apicid, unsigned core_range, process_ap_t p
j = ((pci_read_config32(PCI_DEV(0, 0x18+i, 3), 0xe8) >> 12) & 3);
if(nb_cfg_54) {
if(j == 0 ){ // if it is single core, we need to increase siblings for apic calculation
e0_later_single_core = is_e0_later_in_bsp(i); // single core
#if K8_REV_F_SUPPORT == 0
e0_later_single_core = is_e0_later_in_bsp(i); // single core
#else
e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3
#endif
}
if(e0_later_single_core) {
j=1;
@ -57,14 +104,17 @@ static void for_each_ap(unsigned bsp_apicid, unsigned core_range, process_ap_t p
if(core_range == 2) {
jstart = 1;
}
else {
jstart = 0;
}
if(e0_later_single_core || disable_siblings || (core_range==1)) {
jend = 0;
} else {
jend = siblings;
}
}
for(j=jstart; j<=jend; j++) {
ap_apicid = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:8);
@ -141,10 +191,10 @@ static void wait_cpu_state(unsigned apicid, unsigned state)
if((readback & 0xff) == state) break; //target cpu is in stage started
}
}
static void wait_ap_started(unsigned ap_apicid, void *gp )
{
wait_cpu_state(ap_apicid, 0x33); // started
print_initcpu8_nocr(" ", ap_apicid);
}
static void wait_all_aps_started(unsigned bsp_apicid)
@ -152,9 +202,11 @@ static void wait_all_aps_started(unsigned bsp_apicid)
for_each_ap(bsp_apicid, 0 , wait_ap_started, (void *)0);
}
static void wait_all_other_cores_started(unsigned bsp_apicid)
static void wait_all_other_cores_started(unsigned bsp_apicid) // all aps other than core0
{
print_debug("started ap apicid: ");
for_each_ap(bsp_apicid, 2 , wait_ap_started, (void *)0);
print_debug("\r\n");
}
static void allow_all_aps_stop(unsigned bsp_apicid)
@ -162,8 +214,23 @@ static void allow_all_aps_stop(unsigned bsp_apicid)
lapic_write(LAPIC_MSG_REG, (bsp_apicid<<24) | 0x44); // allow aps to stop
}
static void STOP_CAR_AND_CPU(void)
{
disable_cache_as_ram(); // inline
stop_this_cpu(); // inline, it will stop all cores except node0/core0 the bsp ....
}
#if RAMINIT_SYSINFO == 1
#if MEM_TRAIN_SEQ != 1
static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall) {}
#else
static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall);
#endif
#endif
#if RAMINIT_SYSINFO == 1
static unsigned init_cpus(unsigned cpu_init_detectedx ,struct sys_info *sysinfo)
#else
static unsigned init_cpus(unsigned cpu_init_detectedx)
@ -251,14 +318,16 @@ static unsigned init_cpus(unsigned cpu_init_detectedx)
init_fidvid_ap(bsp_apicid, apicid);
#endif
// We need to stop the CACHE as RAM for this CPU, really?
wait_cpu_state(bsp_apicid, 0x44);
lapic_write(LAPIC_MSG_REG, (apicid<<24) | 0x44); // bsp can not check it before stop_this_cpu
// We need to stop the CACHE as RAM for this CPU, really?
wait_cpu_state(bsp_apicid, 0x44);
lapic_write(LAPIC_MSG_REG, (apicid<<24) | 0x44); // bsp can not check it before stop_this_cpu
set_init_ram_access();
#if RAMINIT_SYSINFO == 1
train_ram_on_node(id.nodeid, id.coreid, sysinfo, STOP_CAR_AND_CPU);
#endif
set_init_ram_access();
disable_cache_as_ram(); // inline
stop_this_cpu(); // inline, it will stop all cores except node0/core0 the bsp ....
}
STOP_CAR_AND_CPU();
}
return bsp_apicid;
}
@ -281,9 +350,13 @@ static void wait_all_core0_started(void)
unsigned i;
unsigned nodes = get_nodes();
for(i=1;i<nodes;i++) { // skip bsp, because it is running on bsp
while(!is_core0_started(i)) {}
}
print_debug("core0 started: ");
for(i=1;i<nodes;i++) { // skip bsp, because it is running on bsp
while(!is_core0_started(i)) {}
print_initcpu8_nocr(" ", i);
}
print_debug("\r\n");
}
#endif

154
src/cpu/amd/model_fxx/model_fxx_init.c
View File

@ -13,6 +13,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <string.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/pae.h>
#include <pc80/mc146818rtc.h>
#include <cpu/x86/lapic.h>
@ -29,6 +30,17 @@
#include <cpu/amd/model_fxx_msr.h>
void cpus_ready_for_init(void)
{
#if MEM_TRAIN_SEQ == 1
struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE);
// wait for ap memory to trained
wait_all_core0_mem_trained(sysinfox);
#endif
}
#if K8_REV_F_SUPPORT == 0
int is_e0_later_in_bsp(int nodeid)
{
uint32_t val;
@ -53,6 +65,18 @@ int is_e0_later_in_bsp(int nodeid)
return e0_later;
}
#endif
#if K8_REV_F_SUPPORT == 1
int is_cpu_f0_in_bsp(int nodeid)
{
uint32_t dword;
device_t dev;
dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid, 3));
dword = pci_read_config32(dev, 0xfc);
return (dword & 0xfff00) == 0x40f00;
}
#endif
#define MCI_STATUS 0x401
@ -265,16 +289,20 @@ static void init_ecc_memory(unsigned node_id)
startk = (pci_read_config32(f1_dev, 0x40 + (node_id*8)) & 0xffff0000) >> 2;
endk = ((pci_read_config32(f1_dev, 0x44 + (node_id*8)) & 0xffff0000) >> 2) + 0x4000;
#if K8_HW_MEM_HOLE_SIZEK != 0
#if HW_MEM_HOLE_SIZEK != 0
#if K8_REV_F_SUPPORT == 0
if (!is_cpu_pre_e0())
{
#endif
uint32_t val;
val = pci_read_config32(f1_dev, 0xf0);
if(val & 1) {
hole_startk = ((val & (0xff<<24)) >> 10);
}
#if K8_REV_F_SUPPORT == 0
}
#endif
#endif
@ -294,7 +322,7 @@ static void init_ecc_memory(unsigned node_id)
disable_lapic();
/* Walk through 2M chunks and zero them */
#if K8_HW_MEM_HOLE_SIZEK != 0
#if HW_MEM_HOLE_SIZEK != 0
/* here hole_startk can not be equal to begink, never. Also hole_startk is in 2M boundary, 64M? */
if ( (hole_startk != 0) && ((begink < hole_startk) && (endk>(4*1024*1024)))) {
for(basek = begink; basek < hole_startk;
@ -336,9 +364,11 @@ static void init_ecc_memory(unsigned node_id)
printk_debug(" done\n");
}
static inline void k8_errata(void)
{
msr_t msr;
#if K8_REV_F_SUPPORT == 0
if (is_cpu_pre_c0()) {
/* Erratum 63... */
msr = rdmsr(HWCR_MSR);
@ -406,8 +436,11 @@ static inline void k8_errata(void)
msr.hi |=1;
wrmsr_amd(CPU_ID_HYPER_EXT_FEATURES, msr);
}
#endif
#if K8_REV_F_SUPPORT == 0
if (!is_cpu_pre_e0())
#endif
{
/* Erratum 110 ... */
msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
@ -420,8 +453,95 @@ static inline void k8_errata(void)
msr.lo |= 1 << 6;
wrmsr(HWCR_MSR, msr);
#if K8_REV_F_SUPPORT == 1
/* Erratum 131... */
msr = rdmsr(NB_CFG_MSR);
msr.lo |= 1 << 20;
wrmsr(NB_CFG_MSR, msr);
#endif
}
#if K8_REV_F_SUPPORT == 1
static void amd_set_name_string_f(device_t dev)
{
unsigned socket;
unsigned cmpCap;
unsigned pwrLmt;
unsigned brandId;
unsigned brandTableIndex;
unsigned nN;
unsigned unknown = 1;
uint8_t str[48];
uint32_t *p;
msr_t msr;
unsigned i;
brandId = cpuid_ebx(0x80000001) & 0xffff;
printk_debug("brandId=%04x\n", brandId);
pwrLmt = ((brandId>>14) & 1) | ((brandId>>5) & 0x0e);
brandTableIndex = (brandId>>9) & 0x1f;
nN = (brandId & 0x3f) | ((brandId>>(15-6)) &(1<<6));
socket = (dev->device >> 4) & 0x3;
cmpCap = cpuid_ecx(0x80000008) & 0xff;
if((brandTableIndex == 0) && (pwrLmt == 0)) {
memset(str, 0, 48);
sprintf(str, "AMD Engineering Sample");
unknown = 0;
} else {
memset(str, 0, 48);
sprintf(str, "AMD Processor model unknown");
#if CPU_SOCKET_TYPE == 0x10
if(socket == 0x01) { // socket F
if ((cmpCap == 1) && ((brandTableIndex==0) ||(brandTableIndex ==1) ||(brandTableIndex == 4)) ) {
uint8_t pc[2];
unknown = 0;
switch (pwrLmt) {
case 2: pc[0]= 'E'; pc[1] = 'E'; break;
case 6: pc[0]= 'H'; pc[1] = 'E'; break;
case 0xa: pc[0]= ' '; pc[1] = ' '; break;
case 0xc: pc[0]= 'S'; pc[1] = 'E'; break;
default: unknown = 1;
}
if(!unknown) {
memset(str, 0, 48);
sprintf(str, "Dual-Core AMD Opteron(tm) Processor %1d2%2d %c%c", brandTableIndex<<1, (nN-1)&0x3f, pc[0], pc[1]);
}
}
}
#else
#if CPU_SOCKET_TYPE == 0x11
if(socket == 0x00) { // socket AM2
if(cmpCap == 0) {
sprintf(str, "Athlon 64");
} else {
sprintf(str, "Athlon 64 Dual Core");
}
}
#endif
#endif
}
p = str;
for(i=0;i<6;i++) {
msr.lo = *p; p++; msr.hi = *p; p++;
wrmsr(0xc0010030+i, msr);
}
}
#endif
extern void model_fxx_update_microcode(unsigned cpu_deviceid);
int init_processor_name(void);
@ -435,6 +555,16 @@ void model_fxx_init(device_t dev)
unsigned siblings;
#endif
#if K8_REV_F_SUPPORT == 1
struct cpuinfo_x86 c;
get_fms(&c, dev->device);
if((c.x86_model & 0xf0) == 0x40) {
amd_set_name_string_f(dev);
}
#endif
/* Turn on caching if we haven't already */
x86_enable_cache();
amd_setup_mtrrs();
@ -504,6 +634,7 @@ static struct device_operations cpu_dev_ops = {
.init = model_fxx_init,
};
static struct cpu_device_id cpu_table[] = {
#if K8_REV_F_SUPPORT == 0
{ X86_VENDOR_AMD, 0xf50 }, /* B3 */
{ X86_VENDOR_AMD, 0xf51 }, /* SH7-B3 */
{ X86_VENDOR_AMD, 0xf58 }, /* SH7-C0 */
@ -540,6 +671,25 @@ static struct cpu_device_id cpu_table[] = {
{ X86_VENDOR_AMD, 0x20fc2 },
{ X86_VENDOR_AMD, 0x20f12 }, /* JH-E6 */
{ X86_VENDOR_AMD, 0x20f32 },
#endif
#if K8_REV_F_SUPPORT == 1
//AMD_F0_SUPPORT
{ X86_VENDOR_AMD, 0x40f50 }, /* SH-F0 Socket F (1207): Opteron */
{ X86_VENDOR_AMD, 0x40f70 }, /* AM2: Athlon64/Athlon64 FX */
{ X86_VENDOR_AMD, 0x40f40 }, /* S1g1: Mobile Athlon64 */
{ X86_VENDOR_AMD, 0x40f11 }, /* JH-F1 Socket F (1207): Opteron Dual Core */
{ X86_VENDOR_AMD, 0x40f31 }, /* AM2: Athlon64 x2/Athlon64 FX Dual Core */
{ X86_VENDOR_AMD, 0x40f01 }, /* S1g1: Mobile Athlon64 */
{ X86_VENDOR_AMD, 0x40f12 }, /* JH-F2 Socket F (1207): Opteron Dual Core */
{ X86_VENDOR_AMD, 0x40f32 }, /* AM2 : Opteron Dual Core/Athlon64 x2/ Athlon64 FX Dual Core */
{ X86_VENDOR_AMD, 0x40fb2 }, /* BH-F2 Socket AM2:Athlon64 x2/ Mobile Athlon64 x2 */
{ X86_VENDOR_AMD, 0x40f82 }, /* S1g1:Turion64 x2 */
{ X86_VENDOR_AMD, 0x40ff2 }, /* DH-F2 Socket AM2: Athlon64 */
{ X86_VENDOR_AMD, 0x40fc2 }, /* S1g1:Turion64 */
{ X86_VENDOR_AMD, 0x40f13 }, /* JH-F3 Socket F (1207): Opteron Dual Core */
{ X86_VENDOR_AMD, 0x40f33 }, /* AM2 : Opteron Dual Core/Athlon64 x2/ Athlon64 FX Dual Core */
#endif
{ 0, 0 },
};

19
src/cpu/amd/model_fxx/model_fxx_update_microcode.c
View File

@ -1,5 +1,5 @@
/* Copyright 2005 AMD
* 2005.08 yhlu add microcode support
* 2005.08 yhlu add microcode support
*/
/*============================================================================
Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
@ -52,10 +52,15 @@ $1.0$
static uint8_t microcode_updates[] __attribute__ ((aligned(16))) = {
#include "microcode_rev_c.h"
#include "microcode_rev_d.h"
#include "microcode_rev_e.h"
#if K8_REV_F_SUPPORT == 0
#include "microcode_rev_c.h"
#include "microcode_rev_d.h"
#include "microcode_rev_e.h"
#endif
#if K8_REV_F_SUPPORT == 1
// #include "microcode_rev_f.h"
#endif
/* Dummy terminator */
0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0,
@ -65,6 +70,7 @@ static uint8_t microcode_updates[] __attribute__ ((aligned(16))) = {
static unsigned get_equivalent_processor_rev_id(unsigned orig_id) {
static unsigned id_mapping_table[] = {
#if K8_REV_F_SUPPORT == 0
0x0f48, 0x0048,
0x0f58, 0x0048,
@ -85,6 +91,11 @@ static unsigned get_equivalent_processor_rev_id(unsigned orig_id) {
0x20f12, 0x0210,
0x20f32, 0x0210,
0x20fb1, 0x0210,
#endif
#if K8_REV_F_SUPPORT == 1
#endif
};

4
src/cpu/amd/model_gx2/vsmsetup.c
View File

@ -254,6 +254,7 @@ void do_vsmbios(void)
unsigned char *buf;
unsigned int size = SMM_SIZE*1024;
int i;
unsigned long ilen, olen;
printk_err("do_vsmbios\n");
/* clear vsm bios data area */
@ -273,7 +274,8 @@ void do_vsmbios(void)
rom = ((unsigned long) 0) - (ROM_SIZE + 64*1024);
buf = (unsigned char *) 0x60000;
unrv2b((uint8_t *)rom, buf);
olen = unrv2b((uint8_t *)rom, buf, &ilen);
printk_debug("buf ilen %d olen%d\n", ilen, olen);
printk_debug("buf %p *buf %d buf[256k] %d\n",
buf, buf[0], buf[SMM_SIZE*1024]);
printk_debug("buf[0x20] signature is %x:%x:%x:%x\n",

4
src/cpu/amd/model_lx/vsmsetup.c
View File

@ -295,6 +295,7 @@ void do_vsmbios(void)
unsigned char *buf;
unsigned int size = SMM_SIZE*1024;
int i;
unsigned long ilen, olen;
printk_err("do_vsmbios\n");
/* clear vsm bios data area */
@ -316,7 +317,8 @@ void do_vsmbios(void)
rom = 0xfffc8000;
buf = (unsigned char *) VSA2_BUFFER;
unrv2b((uint8_t *)rom, buf);
olen = unrv2b((uint8_t *)rom, buf, &ilen);
printk_debug("buf ilen %d olen%d\n", ilen, olen);
printk_debug("buf %p *buf %d buf[256k] %d\n",
buf, buf[0], buf[SMM_SIZE*1024]);
printk_debug("buf[0x20] signature is %x:%x:%x:%x\n",

1
src/cpu/amd/mtrr/amd_earlymtrr.c
View File

@ -15,7 +15,6 @@ static void do_amd_early_mtrr_init(const unsigned long *mtrr_msrs)
*/
msr_t msr;
const unsigned long *msr_addr;
unsigned long cr0;
#if 0
/* Enable the access to AMD RdDram and WrDram extension bits */
msr = rdmsr(SYSCFG_MSR);

4
src/cpu/amd/mtrr/amd_mtrr.c
View File

@ -149,7 +149,7 @@ void amd_setup_mtrrs(void)
msr.lo = state.mmio_basek << 10;
wrmsr(TOP_MEM, msr);
if(state.tomk>(4*1024*1024)) {
if(state.tomk > (4*1024*1024)) {
/* Setup TOP_MEM2 */
msr.hi = state.tomk >> 22;
msr.lo = state.tomk << 10;
@ -180,7 +180,7 @@ void amd_setup_mtrrs(void)
/* FIXME we should probably query the cpu for this
* but so far this is all any recent AMD cpu has supported.
*/
address_bits = 40;
address_bits = CPU_ADDR_BITS; //K8 could be 40, and GH could be 48
/* Now that I have mapped what is memory and what is not
* Setup the mtrrs so we can cache the memory.

19
src/cpu/amd/socket_AM2/Config.lb Normal file
View File

@ -0,0 +1,19 @@
uses CONFIG_CHIP_NAME
uses K8_REV_F_SUPPORT
uses K8_HT_FREQ_1G_SUPPORT
uses DIMM_SUPPORT
uses CPU_SOCKET_TYPE
if CONFIG_CHIP_NAME
config chip.h
end
default K8_REV_F_SUPPORT=1
#Opteron K8 1G HT Support
default K8_HT_FREQ_1G_SUPPORT=1
default DIMM_SUPPORT=0x0004 #DDR2 unbuffered
default CPU_SOCKET_TYPE=0x11
object socket_AM2.o
dir /cpu/amd/model_fxx

4
src/cpu/amd/socket_AM2/chip.h Normal file
View File

@ -0,0 +1,4 @@
extern struct chip_operations cpu_amd_socket_AM2_ops;
struct cpu_amd_socket_AM2_config {
};

6
src/cpu/amd/socket_AM2/socket_AM2.c Normal file
View File

@ -0,0 +1,6 @@
#include <device/device.h>
#include "chip.h"
struct chip_operations cpu_amd_socket_AM2_ops = {
CHIP_NAME("socket AM2")
};

19
src/cpu/amd/socket_F/Config.lb Normal file
View File

@ -0,0 +1,19 @@
uses CONFIG_CHIP_NAME
uses K8_REV_F_SUPPORT
uses K8_HT_FREQ_1G_SUPPORT
uses DIMM_SUPPORT
uses CPU_SOCKET_TYPE
if CONFIG_CHIP_NAME
config chip.h
end
default K8_REV_F_SUPPORT=1
#Opteron K8 1G HT Support
default K8_HT_FREQ_1G_SUPPORT=1
default DIMM_SUPPORT=0x0104 #DDR2 and REG
default CPU_SOCKET_TYPE=0x10
object socket_F.o
dir /cpu/amd/model_fxx

4
src/cpu/amd/socket_F/chip.h Normal file
View File

@ -0,0 +1,4 @@
extern struct chip_operations cpu_amd_socket_F_ops;
struct cpu_amd_socket_F_config {
};

6
src/cpu/amd/socket_F/socket_F.c Normal file
View File

@ -0,0 +1,6 @@
#include <device/device.h>
#include "chip.h"
struct chip_operations cpu_amd_socket_F_ops = {
CHIP_NAME("socket F")
};

2
src/cpu/x86/car/copy_and_run.c
View File

@ -44,7 +44,7 @@ static void copy_and_run(unsigned cpu_reset)
// dump_mem(src, src+0x100);
olen=unrv2b(src, dst);
olen = unrv2b(src, dst, &ilen);
#endif
// dump_mem(dst, dst+0x100);

2
src/cpu/x86/lapic/lapic.c
View File

@ -55,7 +55,7 @@ void setup_lapic(void)
LAPIC_DELIVERY_MODE_NMI)
);
printk_debug(" apic_id: %d ", lapicid());
printk_debug(" apic_id: 0x%02x ", lapicid());
#else /* !NEED_LLAPIC */
/* Only Pentium Pro and later have those MSR stuff */

11
src/cpu/x86/lapic/lapic_cpu_init.c
View File

@ -322,7 +322,7 @@ static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu)
if (!start_cpu(cpu)) {
/* Record the error in cpu? */
printk_err("CPU %u would not start!\n",
printk_err("CPU 0x%02x would not start!\n",
cpu->path.u.apic.apic_id);
}
#if SERIAL_CPU_INIT == 1
@ -354,7 +354,7 @@ static void wait_other_cpus_stop(struct bus *cpu_bus)
continue;
}
if (!cpu->initialized) {
printk_err("CPU %u did not initialize!\n",
printk_err("CPU 0x%02x did not initialize!\n",
cpu->path.u.apic.apic_id);
#warning "FIXME do I need a mainboard_cpu_fixup function?"
}
@ -366,6 +366,10 @@ static void wait_other_cpus_stop(struct bus *cpu_bus)
#define initialize_other_cpus(root) do {} while(0)
#endif /* CONFIG_SMP */
#if WAIT_BEFORE_CPUS_INIT==0
#define cpus_ready_for_init() do {} while(0)
#endif
void initialize_cpus(struct bus *cpu_bus)
{
struct device_path cpu_path;
@ -394,6 +398,8 @@ void initialize_cpus(struct bus *cpu_bus)
copy_secondary_start_to_1m_below(); // why here? In case some day we can start core1 in amd_sibling_init
#endif
cpus_ready_for_init();
#if CONFIG_SMP == 1
#if SERIAL_CPU_INIT == 0
/* start all aps at first, so we can init ECC all together */
@ -407,7 +413,6 @@ void initialize_cpus(struct bus *cpu_bus)
#if CONFIG_SMP == 1
#if SERIAL_CPU_INIT == 1
/* start all aps */
start_other_cpus(cpu_bus, info->cpu);
#endif

22
src/cpu/x86/mtrr/earlymtrr.c
View File

@ -47,10 +47,29 @@ static void set_var_mtrr(
basem.hi = 0;
wrmsr(MTRRphysBase_MSR(reg), basem);
maskm.lo = ~(size - 1) | 0x800;
maskm.hi = 0x0f;
maskm.hi = (1<<(CPU_ADDR_BITS-32))-1;
wrmsr(MTRRphysMask_MSR(reg), maskm);
}
static void set_var_mtrr_x(
unsigned reg, uint32_t base_lo, uint32_t base_hi, uint32_t size_lo, uint32_t size_hi, unsigned type)
{
/* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
msr_t basem, maskm;
basem.lo = (base_lo & 0xfffff000) | type;
basem.hi = base_hi & ((1<<(CPU_ADDR_BITS-32))-1);
wrmsr(MTRRphysBase_MSR(reg), basem);
maskm.hi = (1<<(CPU_ADDR_BITS-32))-1;
if(size_lo) {
maskm.lo = ~(size_lo - 1) | 0x800;
} else {
maskm.lo = 0x800;
maskm.hi &= ~(size_hi - 1);
}
wrmsr(MTRRphysMask_MSR(reg), maskm);
}
static void cache_lbmem(int type)
{
/* Enable caching for 0 - 1MB using variable mtrr */
@ -70,7 +89,6 @@ static void do_early_mtrr_init(const unsigned long *mtrr_msrs)
*/
msr_t msr;
const unsigned long *msr_addr;
unsigned long cr0;
/* Inialize all of the relevant msrs to 0 */
msr.lo = 0;

42
src/cpu/x86/mtrr/mtrr.c
View File

@ -70,6 +70,25 @@ static void set_var_mtrr(
msr_t base, mask;
unsigned address_mask_high;
if (reg >= 8)
return;
// it is recommended that we disable and enable cache when we
// do this.
if (sizek == 0) {
disable_cache();
msr_t zero;
zero.lo = zero.hi = 0;
/* The invalid bit is kept in the mask, so we simply clear the
relevant mask register to disable a range. */
wrmsr (MTRRphysMask_MSR(reg), zero);
enable_cache();
return;
}
address_mask_high = ((1u << (address_bits - 32u)) - 1u);
base.hi = basek >> 22;
@ -86,25 +105,16 @@ static void set_var_mtrr(
mask.lo = 0;
}
if (reg >= 8)
return;
// it is recommended that we disable and enable cache when we
// do this.
disable_cache();
if (sizek == 0) {
msr_t zero;
zero.lo = zero.hi = 0;
/* The invalid bit is kept in the mask, so we simply clear the
relevant mask register to disable a range. */
wrmsr (MTRRphysMask_MSR(reg), zero);
} else {
/* Bit 32-35 of MTRRphysMask should be set to 1 */
base.lo |= type;
mask.lo |= 0x800;
wrmsr (MTRRphysBase_MSR(reg), base);
wrmsr (MTRRphysMask_MSR(reg), mask);
}
/* Bit 32-35 of MTRRphysMask should be set to 1 */
base.lo |= type;
mask.lo |= 0x800;
wrmsr (MTRRphysBase_MSR(reg), base);
wrmsr (MTRRphysMask_MSR(reg), mask);
enable_cache();
}

2
src/devices/device_util.c
View File

@ -430,7 +430,7 @@ void report_resource_stored(device_t dev, struct resource *resource, const char
end = resource_end(resource);
buf[0] = '\0';
if (resource->flags & IORESOURCE_PCI_BRIDGE) {
sprintf(buf, "bus %d ", dev->link[0].secondary);
sprintf(buf, "bus %02x ", dev->link[0].secondary);
}
printk_debug(
"%s %02x <- [0x%010Lx - 0x%010Lx] %s%s%s\n",

18
src/devices/hypertransport.c
View File

@ -3,7 +3,6 @@
*/
#include <bitops.h>
#include <console/console.h>
#include <device/device.h>
@ -78,9 +77,11 @@ static unsigned ht_read_freq_cap(device_t dev, unsigned pos)
/* AMD K8 Unsupported 1Ghz? */
if ((dev->vendor == PCI_VENDOR_ID_AMD) && (dev->device == 0x1100)) {
#if K8_HT_FREQ_1G_SUPPORT == 1
#if K8_REV_F_SUPPORT == 0
if (is_cpu_pre_e0()) { // only e0 later suupport 1GHz HT
freq_cap &= ~(1 << HT_FREQ_1000Mhz);
}
#endif
#else
freq_cap &= ~(1 << HT_FREQ_1000Mhz);
#endif
@ -450,8 +451,8 @@ unsigned int hypertransport_scan_chain(struct bus *bus,
}
flags &= ~0x1f; /* mask out base Unit ID */
flags |= next_unitid & 0x1f;
pci_write_config16(dev, pos + PCI_CAP_FLAGS, flags);
flags |= next_unitid & 0x1f;
pci_write_config16(dev, pos + PCI_CAP_FLAGS, flags);
/* Update the Unitd id in the device structure */
static_count = 1;
@ -490,7 +491,6 @@ unsigned int hypertransport_scan_chain(struct bus *bus,
dev->vendor, dev->device,
(dev->enabled? "enabled": "disabled"), next_unitid);
} while((last_unitid != next_unitid) && (next_unitid <= (max_devfn >> 3)));
end_of_chain:
#if OPT_HT_LINK == 1
@ -560,9 +560,17 @@ unsigned int hypertransport_scan_chain(struct bus *bus,
*
* @return The maximum bus number found, after scanning all subordinate busses
*/
unsigned int hypertransport_scan_chain_x(struct bus *bus,
unsigned min_devfn, unsigned max_devfn, unsigned int max)
{
unsigned ht_unitid_base[4];
unsigned offset_unitid = 1;
return hypertransport_scan_chain(bus, min_devfn, max_devfn, max, ht_unitid_base, offset_unitid);
}
unsigned int ht_scan_bridge(struct device *dev, unsigned int max)
{
return do_pci_scan_bridge(dev, max, hypertransport_scan_chain);
return do_pci_scan_bridge(dev, max, hypertransport_scan_chain_x);
}

3
src/include/cpu/amd/microcode.h
View File

@ -2,4 +2,5 @@
#define CPU_AMD_MICORCODE_H
void amd_update_microcode(void *microcode_updates, unsigned processor_rev_id);
#endif /* CPU_AMD_MICROCODE_H */
#endif /* CPU_AMD_MICROCODE_H */

42
src/include/cpu/amd/model_fxx_rev.h
View File

@ -1,5 +1,6 @@
#include <arch/cpu.h>
#if K8_REV_F_SUPPORT == 0
static inline int is_cpu_rev_a0(void)
{
return (cpuid_eax(1) & 0xfffef) == 0x0f00;
@ -74,5 +75,46 @@ static int is_e0_later_in_bsp(int nodeid)
int is_e0_later_in_bsp(int nodeid); //defined model_fxx_init.c
#endif
#endif
#if K8_REV_F_SUPPORT == 1
//AMD_F0_SUPPORT
static inline int is_cpu_pre_f0(void)
{
return (cpuid_eax(1) & 0xfff0f) < 0x40f00;
}
static inline int is_cpu_f0(void)
{
return (cpuid_eax(1) & 0xfff00) == 0x40f00;
}
static inline int is_cpu_pre_f2(void)
{
return (cpuid_eax(1) & 0xfff0f) < 0x40f02;
}
#ifdef __ROMCC__
//AMD_F0_SUPPORT
static int is_cpu_f0_in_bsp(int nodeid)
{
uint32_t dword;
device_t dev;
dev = PCI_DEV(0, 0x18+nodeid, 3);
dword = pci_read_config32(dev, 0xfc);
return (dword & 0xfff00) == 0x40f00;
}
static int is_cpu_pre_f2_in_bsp(int nodeid)
{
uint32_t dword;
device_t dev;
dev = PCI_DEV(0, 0x18+nodeid, 3);
dword = pci_read_config32(dev, 0xfc);
return (dword & 0xfff0f) < 0x40f02;
}
#else
int is_cpu_f0_in_bsp(int nodeid); // defined in model_fxx_init.c
#endif
#endif

2
src/include/cpu/x86/mem.h
View File

@ -6,7 +6,7 @@ static inline void clear_memory(void *addr, unsigned long size)
{
asm volatile(
"cld \n\t"
"rep stosl\n\t"
"rep; stosl\n\t"
: /* No outputs */
: "a" (0), "D" (addr), "c" (size>>2)
);

6
src/include/device/device.h
View File

@ -48,14 +48,14 @@ struct bus {
device_t children; /* devices behind this bridge */
unsigned bridge_ctrl; /* Bridge control register */
unsigned char link; /* The index of this link */
unsigned char secondary; /* secondary bus number */
unsigned char subordinate; /* max subordinate bus number */
uint16_t secondary; /* secondary bus number */
uint16_t subordinate; /* max subordinate bus number */
unsigned char cap; /* PCi capability offset */
unsigned reset_needed : 1;
unsigned disable_relaxed_ordering : 1;
};
#define MAX_RESOURCES 12
#define MAX_RESOURCES 12
#define MAX_LINKS 8
/*
* There is one device structure for each slot-number/function-number

5
src/include/device/hypertransport_def.h
View File

@ -11,6 +11,11 @@
#define HT_FREQ_1200Mhz 7
#define HT_FREQ_1400Mhz 8
#define HT_FREQ_1600Mhz 9
#define HT_FREQ_1800Mhz 10
#define HT_FREQ_2000Mhz 11
#define HT_FREQ_2200Mhz 12
#define HT_FREQ_2400Mhz 13
#define HT_FREQ_2600Mhz 14
#define HT_FREQ_VENDOR 15 /* AMD defines this to be 100Mhz */
#endif /* DEVICE_HYPERTRANSPORT_DEF_H */

12
src/include/device/pci.h
View File

@ -29,12 +29,12 @@ struct pci_operations {
/* Common pci bus operations */
struct pci_bus_operations {
uint8_t (*read8) (struct bus *pbus, unsigned char bus, int devfn, int where);
uint16_t (*read16) (struct bus *pbus, unsigned char bus, int devfn, int where);
uint32_t (*read32) (struct bus *pbus, unsigned char bus, int devfn, int where);
void (*write8) (struct bus *pbus, unsigned char bus, int devfn, int where, uint8_t val);
void (*write16) (struct bus *pbus, unsigned char bus, int devfn, int where, uint16_t val);
void (*write32) (struct bus *pbus, unsigned char bus, int devfn, int where, uint32_t val);
uint8_t (*read8) (struct bus *pbus, int bus, int devfn, int where);
uint16_t (*read16) (struct bus *pbus, int bus, int devfn, int where);
uint32_t (*read32) (struct bus *pbus, int bus, int devfn, int where);
void (*write8) (struct bus *pbus, int bus, int devfn, int where, uint8_t val);
void (*write16) (struct bus *pbus, int bus, int devfn, int where, uint16_t val);
void (*write32) (struct bus *pbus, int bus, int devfn, int where, uint32_t val);
};
struct pci_driver {

1
src/include/device/pci_def.h
View File

@ -201,6 +201,7 @@
#define PCI_HT_CAP_SLAVE_FREQ1 0x011 /* Slave frequency to */
#define PCI_HT_CAP_SLAVE_FREQ_CAP0 0x0e /* Frequency capability from */
#define PCI_HT_CAP_SLAVE_FREQ_CAP1 0x12 /* Frequency capability to */
#define PCI_HT_CAP_SLAVE_LINK_ENUM 0x14 /* Link Enumeration Scratchpad */
/* Power Management Registers */

12
src/lib/nrv2b.c
View File

@ -28,18 +28,13 @@
#if ENDIAN == 0 && BITSIZE == 32
#define GETBIT(bb, src, ilen) GETBIT_LE32(bb, src, ilen)
#endif
static unsigned long unrv2b(uint8_t * src, uint8_t * dst)
static unsigned long unrv2b(uint8_t * src, uint8_t * dst, unsigned long *ilen_p)
{
unsigned long ilen = 0, olen = 0, last_m_off = 1;
uint32_t bb = 0;
unsigned bc = 0;
const uint8_t *m_pos;
// unsigned long file_len = *(unsigned long *) src;
// we only have printk_debug in copy_and_run.c if CONFIG_USE_INIT is
// not set, so comment it out.
// printk_debug("compressed file len is supposed to be %d bytes\n", file_len);
// skip length
src += 4;
/* FIXME: check olen with the length stored in first 4 bytes */
@ -81,9 +76,8 @@ static unsigned long unrv2b(uint8_t * src, uint8_t * dst)
} while (--m_len > 0);
}
// we only have printk_debug in copy_and_run.c if CONFIG_USE_INIT is
// not set, so comment it out.
//printk_debug("computed len is %d, file len is %d\n", olen, file_len);
*ilen_p = ilen;
return olen;
}

4
src/mainboard/Iwill/DK8HTX/auto.c
View File

@ -11,7 +11,6 @@
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
@ -23,7 +22,6 @@
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#include "cpu/amd/dualcore/dualcore.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@ -126,8 +124,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "sdram/generic_sdram.c"
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#define FIRST_CPU 1
#define SECOND_CPU 1

4
src/mainboard/Iwill/DK8S2/auto.c
View File

@ -11,7 +11,6 @@
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
@ -23,7 +22,6 @@
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#include "cpu/amd/dualcore/dualcore.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@ -126,8 +124,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "sdram/generic_sdram.c"
#include "northbridge/amd/amdk8/resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#define FIRST_CPU 1
#define SECOND_CPU 1

4
src/mainboard/Iwill/DK8X/auto.c
View File

@ -11,7 +11,6 @@
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
@ -24,7 +23,6 @@
#include "superio/NSC/pc87360/pc87360_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#include "cpu/amd/dualcore/dualcore.c"
#define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
@ -128,8 +126,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "sdram/generic_sdram.c"
#include "northbridge/amd/amdk8/resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#define FIRST_CPU 1
#define SECOND_CPU 1

2
src/mainboard/agami/aruma/Options.lb
View File

@ -138,7 +138,7 @@ default LIFT_BSP_APIC_ID=0
default USE_DCACHE_RAM=1
default DCACHE_RAM_BASE=0xcc000
default DCACHE_RAM_SIZE=0x4000
default CONFIG_USE_INIT=1
default CONFIG_USE_INIT=0
##
## Build code to setup a generic IOAPIC

4
src/mainboard/amd/serenade/auto.c
View File

@ -13,7 +13,6 @@
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
@ -25,7 +24,6 @@
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#include "cpu/amd/dualcore/dualcore.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@ -128,8 +126,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "sdram/generic_sdram.c"
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#define FIRST_CPU 1
#define SECOND_CPU 1

406
src/mainboard/amd/serengeti_cheetah/Config.lb Normal file
View File

@ -0,0 +1,406 @@
##
## Compute the location and size of where this firmware image
## (linuxBIOS plus bootloader) will live in the boot rom chip.
##
if USE_FAILOVER_IMAGE
default ROM_SECTION_SIZE = FAILOVER_SIZE
default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
else
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
else
default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
default ROM_SECTION_OFFSET = 0
end
end
##
## Compute the start location and size size of
## The linuxBIOS bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
## Compute where this copy of linuxBIOS will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
##
## Compute a range of ROM that can cached to speed up linuxBIOS,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
##
default XIP_ROM_SIZE=65536
if USE_FAILOVER_IMAGE
default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
else
if USE_FALLBACK_IMAGE
default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
else
default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
end
end
arch i386 end
##
## Build the objects we have code for in this directory.
##
driver mainboard.o
#dir /drivers/si/3114
#needed by irq_tables and mptable and acpi_tables
object get_bus_conf.o
if HAVE_MP_TABLE
object mptable.o
end
if HAVE_PIRQ_TABLE
object irq_tables.o
end
#if HAVE_ACPI_TABLES
# object acpi_tables.o
# object fadt.o
# if SB_HT_CHAIN_ON_BUS0
# object dsdt_bus0.o
# else
# object dsdt.o
# end
# object ssdt.o
# if ACPI_SSDTX_NUM
# if SB_HT_CHAIN_ON_BUS0
# object ssdt2_bus0.o
# else
# object ssdt2.o
# end
# end
#end
if HAVE_ACPI_TABLES
object acpi_tables.o
object fadt.o
makerule dsdt.c
depends "$(MAINBOARD)/dx/dsdt_lb.dsl"
action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/dsdt_lb.dsl"
action "mv dsdt_lb.hex dsdt.c"
end
object ./dsdt.o
#./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
if ACPI_SSDTX_NUM
makerule ssdt2.c
depends "$(MAINBOARD)/dx/pci2.asl"
action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci2.asl"
action "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex"
action "mv pci2.hex ssdt2.c"
end
object ./ssdt2.o
end
end
if USE_DCACHE_RAM
if CONFIG_USE_INIT
# compile cache_as_ram.c to auto.o
makerule ./cache_as_ram_auto.o
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
end
else
#compile cache_as_ram.c to auto.inc
makerule ./cache_as_ram_auto.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
action "perl -e 's/.rodata/.rom.data/g' -pi $@"
action "perl -e 's/.text/.section .rom.text/g' -pi $@"
end
end
end
if USE_FAILOVER_IMAGE
else
if CONFIG_AP_CODE_IN_CAR
makerule ./apc_auto.o
depends "$(MAINBOARD)/apc_auto.c option_table.h"
action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
end
ldscript /arch/i386/init/ldscript_apc.lb
end
end
##
## Build our 16 bit and 32 bit linuxBIOS entry code
##
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
ldscript /cpu/x86/16bit/entry16.lds
end
else
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
ldscript /cpu/x86/16bit/entry16.lds
end
end
mainboardinit cpu/x86/32bit/entry32.inc
if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
end
##
## Build our reset vector (This is where linuxBIOS is entered)
##
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
mainboardinit cpu/x86/32bit/reset32.inc
ldscript /cpu/x86/32bit/reset32.lds
end
else
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
mainboardinit cpu/x86/32bit/reset32.inc
ldscript /cpu/x86/32bit/reset32.lds
end
end
##
## Include an id string (For safe flashing)
##
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
if USE_DCACHE_RAM
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
end
###
### This is the early phase of linuxBIOS startup
### Things are delicate and we test to see if we should
### failover to another image.
###
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover_failover.lds
end
end
else
if USE_FALLBACK_IMAGE
if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds
end
end
end
###
### O.k. We aren't just an intermediary anymore!
###
##
## Setup RAM
##
if USE_DCACHE_RAM
if CONFIG_USE_INIT
initobject cache_as_ram_auto.o
else
mainboardinit ./cache_as_ram_auto.inc
end
end
##
## Include the secondary Configuration files
##
if CONFIG_CHIP_NAME
config chip.h
end
# sample config for amd/serengeti_cheetah
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
chip cpu/amd/socket_F
device apic 0 on end
end
end
device pci_domain 0 on
chip northbridge/amd/amdk8
device pci 18.0 on # northbridge
# devices on link 0, link 0 == LDT 0
chip southbridge/amd/amd8132
# the on/off keyword is mandatory
device pci 0.0 on end
device pci 0.1 on end
device pci 1.0 on end
device pci 1.1 on end
end
chip southbridge/amd/amd8111
# this "device pci 0.0" is the parent the next one
# PCI bridge
device pci 0.0 on
device pci 0.0 on end
device pci 0.1 on end
device pci 0.2 off end
device pci 1.0 off end
end
device pci 1.0 on
chip superio/winbond/w83627hf
device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.2 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 off # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 2e.6 off # CIR
io 0x60 = 0x100
end
device pnp 2e.7 off # GAME_MIDI_GIPO1
io 0x60 = 0x220
io 0x62 = 0x300
irq 0x70 = 9
end
device pnp 2e.8 off end # GPIO2
device pnp 2e.9 off end # GPIO3
device pnp 2e.a off end # ACPI
device pnp 2e.b on # HW Monitor
io 0x60 = 0x290
irq 0x70 = 5
end
end
end
device pci 1.1 on end
device pci 1.2 on end
device pci 1.3 on
chip drivers/i2c/i2cmux # pca9556 smbus mux
device i2c 18 on #0 pca9516 1
chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end
end
chip drivers/generic/generic #dimm 0-0-1
device i2c 51 on end
end
chip drivers/generic/generic #dimm 0-1-0
device i2c 52 on end
end
chip drivers/generic/generic #dimm 0-1-1
device i2c 53 on end
end
end
device i2c 18 on #1 pca9516 2
chip drivers/generic/generic #dimm 1-0-0
device i2c 50 on end
end
chip drivers/generic/generic #dimm 1-0-1
device i2c 51 on end
end
chip drivers/generic/generic #dimm 1-1-0
device i2c 52 on end
end
chip drivers/generic/generic #dimm 1-1-1
device i2c 53 on end
end
chip drivers/generic/generic #dimm 1-2-0
device i2c 54 on end
end
chip drivers/generic/generic #dimm 1-2-1
device i2c 55 on end
end
chip drivers/generic/generic #dimm 1-3-0
device i2c 56 on end
end
chip drivers/generic/generic #dimm 1-3-1
device i2c 57 on end
end
end
end
end # acpi
device pci 1.5 off end
device pci 1.6 off end
register "ide0_enable" = "1"
register "ide1_enable" = "1"
end
end # device pci 18.0
device pci 18.0 on end
device pci 18.0 on end
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
end
chip northbridge/amd/amdk8
device pci 19.0 on # northbridge
chip southbridge/amd/amd8151
# the on/off keyword is mandatory
device pci 0.0 on end
device pci 1.0 on end
end
end # device pci 19.0
device pci 19.0 on end
device pci 19.0 on end
device pci 19.1 on end
device pci 19.2 on end
device pci 19.3 on end
end
end #pci_domain
# chip drivers/generic/debug
# device pnp 0.0 off end # chip name
# device pnp 0.1 on end # pci_regs_all
# device pnp 0.2 off end # mem
# device pnp 0.3 off end # cpuid
# device pnp 0.4 off end # smbus_regs_all
# device pnp 0.5 off end # dual core msr
# device pnp 0.6 off end # cache size
# device pnp 0.7 off end # tsc
# end
end

329
src/mainboard/amd/serengeti_cheetah/Options.lb Normal file
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uses HAVE_MP_TABLE
uses HAVE_PIRQ_TABLE
uses HAVE_ACPI_TABLES
uses ACPI_SSDTX_NUM
uses USE_FALLBACK_IMAGE
uses USE_FAILOVER_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_FAILOVER_BOOT
uses HAVE_HARD_RESET
uses IRQ_SLOT_COUNT
uses HAVE_OPTION_TABLE
uses CONFIG_MAX_CPUS
uses CONFIG_MAX_PHYSICAL_CPUS
uses CONFIG_LOGICAL_CPUS
uses CONFIG_IOAPIC
uses CONFIG_SMP
uses FALLBACK_SIZE
uses FAILOVER_SIZE
uses ROM_SIZE
uses ROM_SECTION_SIZE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
uses CONFIG_ROM_STREAM
uses CONFIG_ROM_STREAM_START
uses CONFIG_COMPRESSED_ROM_STREAM
uses PAYLOAD_SIZE
uses _ROMBASE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses STACK_SIZE
uses HEAP_SIZE
uses USE_OPTION_TABLE
uses LB_CKS_RANGE_START
uses LB_CKS_RANGE_END
uses LB_CKS_LOC
uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses LINUXBIOS_EXTRA_VERSION
uses _RAMBASE
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
uses CONFIG_GDB_STUB
uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
uses HW_MEM_HOLE_SIZE_AUTO_INC
uses K8_HT_FREQ_1G_SUPPORT
uses HT_CHAIN_UNITID_BASE
uses HT_CHAIN_END_UNITID_BASE
uses SB_HT_CHAIN_ON_BUS0
uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
uses DCACHE_RAM_GLOBAL_VAR_SIZE
uses CONFIG_USE_INIT
uses SERIAL_CPU_INIT
uses ENABLE_APIC_EXT_ID
uses APIC_ID_OFFSET
uses LIFT_BSP_APIC_ID
uses CONFIG_PCI_64BIT_PREF_MEM
uses CONFIG_LB_MEM_TOPK
uses CONFIG_AP_CODE_IN_CAR
uses MEM_TRAIN_SEQ
uses WAIT_BEFORE_CPUS_INIT
###
### Build options
###
##
## ROM_SIZE is the size of boot ROM that this board will use.
##
default ROM_SIZE=524288
##
## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
##
#default FALLBACK_SIZE=131072
#default FALLBACK_SIZE=0x40000
#FALLBACK: 256K-4K
default FALLBACK_SIZE=0x3f000
#FAILOVER: 4K
default FAILOVER_SIZE=0x01000
#more 1M for pgtbl
default CONFIG_LB_MEM_TOPK=2048
##
## Build code for the fallback boot
##
default HAVE_FALLBACK_BOOT=1
default HAVE_FAILOVER_BOOT=1
##
## Build code to reset the motherboard from linuxBIOS
##
default HAVE_HARD_RESET=1
##
## Build code to export a programmable irq routing table
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=11
##
## Build code to export an x86 MP table
## Useful for specifying IRQ routing values
##
default HAVE_MP_TABLE=1
## ACPI tables will be included
default HAVE_ACPI_TABLES=1
## extra SSDT num
default ACPI_SSDTX_NUM=1
##
## Build code to export a CMOS option table
##
default HAVE_OPTION_TABLE=1
##
## Move the default LinuxBIOS cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default LB_CKS_LOC=123
##
## Build code for SMP support
## Only worry about 2 micro processors
##
default CONFIG_SMP=1
default CONFIG_MAX_CPUS=8
default CONFIG_MAX_PHYSICAL_CPUS=4
default CONFIG_LOGICAL_CPUS=1
default SERIAL_CPU_INIT=0
default ENABLE_APIC_EXT_ID=0
default APIC_ID_OFFSET=0x8
default LIFT_BSP_APIC_ID=1
#CHIP_NAME ?
default CONFIG_CHIP_NAME=1
#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
#2G
#default HW_MEM_HOLE_SIZEK=0x200000
#1G
default HW_MEM_HOLE_SIZEK=0x100000
#512M
#default HW_MEM_HOLE_SIZEK=0x80000
#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
#default HW_MEM_HOLE_SIZE_AUTO_INC=1
#Opteron K8 1G HT Support
default K8_HT_FREQ_1G_SUPPORT=1
#VGA Console
default CONFIG_CONSOLE_VGA=1
default CONFIG_PCI_ROM_RUN=1
#HT Unit ID offset, default is 1, the typical one
default HT_CHAIN_UNITID_BASE=0xa
#real SB Unit ID, default is 0x20, mean dont touch it at last
default HT_CHAIN_END_UNITID_BASE=0x6
#make the SB HT chain on bus 0, default is not (0)
default SB_HT_CHAIN_ON_BUS0=2
#only offset for SB chain?, default is yes(1)
#default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
#allow capable device use that above 4G
#default CONFIG_PCI_64BIT_PREF_MEM=1
##
## enable CACHE_AS_RAM specifics
##
default USE_DCACHE_RAM=1
default DCACHE_RAM_BASE=0xc8000
default DCACHE_RAM_SIZE=0x08000
default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
default CONFIG_USE_INIT=0
default CONFIG_AP_CODE_IN_CAR=1
default MEM_TRAIN_SEQ=1
default WAIT_BEFORE_CPUS_INIT=1
##
## Build code to setup a generic IOAPIC
##
default CONFIG_IOAPIC=1
##
## Clean up the motherboard id strings
##
default MAINBOARD_PART_NUMBER="serengeti_cheetah"
default MAINBOARD_VENDOR="AMD"
default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
###
### LinuxBIOS layout values
###
## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
default ROM_IMAGE_SIZE = 65536
##
## Use a small 8K stack
##
default STACK_SIZE=0x2000
##
## Use a small 32K heap
##
default HEAP_SIZE=0x8000
##
## Only use the option table in a normal image
##
default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
##
## LinuxBIOS C code runs at this location in RAM
##
default _RAMBASE=0x00100000
##
## Load the payload from the ROM
##
default CONFIG_ROM_STREAM = 1
#default CONFIG_COMPRESSED_ROM_STREAM = 1
###
### Defaults of options that you may want to override in the target config file
###
##
## The default compiler
##
default CC="$(CROSS_COMPILE)gcc-3.4.5 -m32"
default HOSTCC="gcc-3.4.5"
##
## Disable the gdb stub by default
##
default CONFIG_GDB_STUB=0
##
## The Serial Console
##
# To Enable the Serial Console
default CONFIG_CONSOLE_SERIAL8250=1
## Select the serial console baud rate
default TTYS0_BAUD=115200
#default TTYS0_BAUD=57600
#default TTYS0_BAUD=38400
#default TTYS0_BAUD=19200
#default TTYS0_BAUD=9600
#default TTYS0_BAUD=4800
#default TTYS0_BAUD=2400
#default TTYS0_BAUD=1200
# Select the serial console base port
default TTYS0_BASE=0x3f8
# Select the serial protocol
# This defaults to 8 data bits, 1 stop bit, and no parity
default TTYS0_LCS=0x3
##
### Select the linuxBIOS loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
## CRIT 3 critical conditions
## ERR 4 error conditions
## WARNING 5 warning conditions
## NOTICE 6 normal but significant condition
## INFO 7 informational
## DEBUG 8 debug-level messages
## SPEW 9 Way too many details
## Request this level of debugging output
default DEFAULT_CONSOLE_LOGLEVEL=8
## At a maximum only compile in this level of debugging
default MAXIMUM_CONSOLE_LOGLEVEL=8
##
## Select power on after power fail setting
default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
### End Options.lb
end

25
src/mainboard/amd/serengeti_cheetah/a Normal file
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@ -0,0 +1,25 @@
echo "Creating for ACPI hex for bus 1 Conf"
cd dx
iasl -tc dsdt_lb.dsl
rm DSDT.aml
mv dsdt_lb.hex ../dsdt.c
iasl -tc pci2.asl
rm SSDT2.aml
perl -e 's/AmlCode/AmlCode_ssdt2/g' -pi pci2.hex
mv pci2.hex ../ssdt2.c
cd ..
echo "Creating for ACPI hex for bus 0 Conf"
cd dx_bus0
iasl -tc dsdt_lb.dsl
rm DSDT.aml
mv dsdt_lb.hex ../dsdt_bus0.c
iasl -tc pci2.asl
rm SSDT2.aml
perl -e 's/AmlCode/AmlCode_ssdt2/g' -pi pci2.hex
mv pci2.hex ../ssdt2_bus0.c
cd ..
echo "Creating ssdt"
iasl -tc ssdt_lb_x.dsl
rm SSDT.aml
perl -e 's/AmlCode/AmlCode_ssdt/g' -pi ssdt_lb_x.hex
mv ssdt_lb_x.hex ssdt.c

268
src/mainboard/amd/serengeti_cheetah/acpi_tables.c Normal file
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/*
* Island Aruma ACPI support
* written by Stefan Reinauer <stepan@openbios.org>
* (C) 2005 Stefan Reinauer
*
*
* Copyright 2005 AMD
* 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB
*/
#include <console/console.h>
#include <string.h>
#include <arch/acpi.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <cpu/amd/amdk8_sysconf.h>
#include "mb_sysconf.h"
#define DUMP_ACPI_TABLES 0
#if DUMP_ACPI_TABLES == 1
static void dump_mem(unsigned start, unsigned end)
{
unsigned i;
print_debug("dump_mem:");
for(i=start;i<end;i++) {
if((i & 0xf)==0) {
printk_debug("\n%08x:", i);
}
printk_debug(" %02x", (unsigned char)*((unsigned char *)i));
}
print_debug("\n");
}
#endif
extern unsigned char AmlCode[];
extern unsigned char AmlCode_ssdt[];
#if ACPI_SSDTX_NUM >= 1
extern unsigned char AmlCode_ssdt2[];
//extern unsigned char AmlCode_ssdt3[];
//extern unsigned char AmlCode_ssdt4[];
//extern unsigned char AmlCode_ssdt5[];
//extern unsigned char AmlCode_ssdt6[];
//extern unsigned char AmlCode_ssdt7[];
//extern unsigned char AmlCode_ssdt8[];
#endif
#define IO_APIC_ADDR 0xfec00000UL
unsigned long acpi_fill_madt(unsigned long current)
{
unsigned int gsi_base=0x18;
struct mb_sysconf_t *m;
m = sysconf.mb;
/* create all subtables for processors */
current = acpi_create_madt_lapics(current);
/* Write 8111 IOAPIC */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8111,
IO_APIC_ADDR, 0);
/* Write all 8131 IOAPICs */
{
device_t dev;
struct resource *res;
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN((sysconf.hcdn[0]&0xff), 1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_1,
res->base, gsi_base );
gsi_base+=7;
}
}
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN((sysconf.hcdn[0] & 0xff)+1, 1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_2,
res->base, gsi_base );
gsi_base+=7;
}
}
}
current += acpi_create_madt_irqoverride( (acpi_madt_irqoverride_t *)
current, 0, 0, 2, 5 );
/* 0: mean bus 0--->ISA */
/* 0: PIC 0 */
/* 2: APIC 2 */
/* 5 mean: 0101 --> Edige-triggered, Active high*/
/* create all subtables for processors */
current = acpi_create_madt_lapic_nmis(current, 5, 1);
/* 1: LINT1 connect to NMI */
return current;
}
extern void get_bus_conf(void);
extern void update_ssdt(void *ssdt);
unsigned long write_acpi_tables(unsigned long start)
{
unsigned long current;
acpi_rsdp_t *rsdp;
acpi_rsdt_t *rsdt;
acpi_hpet_t *hpet;
acpi_madt_t *madt;
acpi_srat_t *srat;
acpi_slit_t *slit;
acpi_fadt_t *fadt;
acpi_facs_t *facs;
acpi_header_t *dsdt;
acpi_header_t *ssdt;
acpi_header_t *ssdtx;
unsigned char *AmlCode_ssdtx[HC_POSSIBLE_NUM];
int i;
get_bus_conf(); //it will get sblk, pci1234, hcdn, and sbdn
/* Align ACPI tables to 16byte */
start = ( start + 0x0f ) & -0x10;
current = start;
printk_info("ACPI: Writing ACPI tables at %lx...\n", start);
/* We need at least an RSDP and an RSDT Table */
rsdp = (acpi_rsdp_t *) current;
current += sizeof(acpi_rsdp_t);
rsdt = (acpi_rsdt_t *) current;
current += sizeof(acpi_rsdt_t);
/* clear all table memory */
memset((void *)start, 0, current - start);
acpi_write_rsdp(rsdp, rsdt);
acpi_write_rsdt(rsdt);
/*
* We explicitly add these tables later on:
*/
printk_debug("ACPI: * HPET\n");
hpet = (acpi_hpet_t *) current;
current += sizeof(acpi_hpet_t);
acpi_create_hpet(hpet);
acpi_add_table(rsdt,hpet);
/* If we want to use HPET Timers Linux wants an MADT */
printk_debug("ACPI: * MADT\n");
madt = (acpi_madt_t *) current;
acpi_create_madt(madt);
current+=madt->header.length;
acpi_add_table(rsdt,madt);
/* SRAT */
printk_debug("ACPI: * SRAT\n");
srat = (acpi_srat_t *) current;
acpi_create_srat(srat);
current+=srat->header.length;
acpi_add_table(rsdt,srat);
/* SLIT */
printk_debug("ACPI: * SLIT\n");
slit = (acpi_slit_t *) current;
acpi_create_slit(slit);
current+=slit->header.length;
acpi_add_table(rsdt,slit);
/* SSDT */
printk_debug("ACPI: * SSDT\n");
ssdt = (acpi_header_t *)current;
current += ((acpi_header_t *)AmlCode_ssdt)->length;
memcpy((void *)ssdt, (void *)AmlCode_ssdt, ((acpi_header_t *)AmlCode_ssdt)->length);
//Here you need to set value in pci1234, sblk and sbdn in get_bus_conf.c
update_ssdt((void*)ssdt);
/* recalculate checksum */
ssdt->checksum = 0;
ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
acpi_add_table(rsdt,ssdt);
#if ACPI_SSDTX_NUM >= 1
// we need to make ssdt2 match to PCI2 in pci2.asl,... pci1234[1]
AmlCode_ssdtx[1] = AmlCode_ssdt2;
// AmlCode_ssdtx[2] = AmlCode_ssdt3;
// AmlCode_ssdtx[3] = AmlCode_ssdt4;
// AmlCode_ssdtx[4] = AmlCode_ssdt5;
// AmlCode_ssdtx[5] = AmlCode_ssdt6;
// AmlCode_ssdtx[6] = AmlCode_ssdt7;
// AmlCode_ssdtx[7] = AmlCode_ssdt8;
//same htio, but different possition? We may have to copy, change HCIN, and recalculate the checknum and add_table
for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink
if((sysconf.pci1234[i] & 1) != 1 ) continue;
printk_debug("ACPI: * SSDT for PCI%d\n", i+1); //pci0 and pci1 are in dsdt
ssdtx = (acpi_header_t *)current;
current += ((acpi_header_t *)AmlCode_ssdtx[i])->length;
memcpy((void *)ssdtx, (void *)AmlCode_ssdtx[i], ((acpi_header_t *)AmlCode_ssdtx[i])->length);
acpi_add_table(rsdt,ssdtx);
}
#endif
/* FACS */
printk_debug("ACPI: * FACS\n");
facs = (acpi_facs_t *) current;
current += sizeof(acpi_facs_t);
acpi_create_facs(facs);
/* DSDT */
printk_debug("ACPI: * DSDT\n");
dsdt = (acpi_header_t *)current;
current += ((acpi_header_t *)AmlCode)->length;
memcpy((void *)dsdt,(void *)AmlCode, \
((acpi_header_t *)AmlCode)->length);
printk_debug("ACPI: * DSDT @ %08x Length %x\n",dsdt,dsdt->length);
/* FDAT */
printk_debug("ACPI: * FADT\n");
fadt = (acpi_fadt_t *) current;
current += sizeof(acpi_fadt_t);
acpi_create_fadt(fadt,facs,dsdt);
acpi_add_table(rsdt,fadt);
#if DUMP_ACPI_TABLES == 1
printk_debug("rsdp\n");
dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
printk_debug("rsdt\n");
dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
printk_debug("madt\n");
dump_mem(madt, ((void *)madt) + madt->header.length);
printk_debug("srat\n");
dump_mem(srat, ((void *)srat) + srat->header.length);
printk_debug("slit\n");
dump_mem(slit, ((void *)slit) + slit->header.length);
printk_debug("ssdt\n");
dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
printk_debug("fadt\n");
dump_mem(fadt, ((void *)fadt) + fadt->header.length);
#endif
printk_info("ACPI: done.\n");
return current;
}

108
src/mainboard/amd/serengeti_cheetah/apc_auto.c Normal file
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#define ASSEMBLY 1
#define __ROMCC__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1
//used by raminit
#define QRANK_DIMM_SUPPORT 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#include <stdint.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#if 0
static void post_code(uint8_t value) {
#if 1
int i;
for(i=0;i<0x80000;i++) {
outb(value, 0x80);
}
#endif
}
#endif
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
//#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
#include "northbridge/amd/amdk8/amdk8_f.h"
#include "cpu/x86/mtrr.h"
#include "cpu/amd/mtrr.h"
#include "cpu/x86/tsc.h"
#include "northbridge/amd/amdk8/amdk8_f_pci.c"
#include "northbridge/amd/amdk8/raminit_f_dqs.c"
#include "cpu/amd/dualcore/dualcore.c"
void hardwaremain(int ret_addr)
{
struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
struct node_core_id id;
id = get_node_core_id_x();
print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n");
train_ram(id.nodeid, sysinfo, sysinfox);
/*
go back, but can not use stack any more, because we only keep ret_addr and can not restore esp, and ebp
*/
__asm__ volatile (
"movl %0, %%edi\n\t"
"jmp *%%edi\n\t"
:: "a"(ret_addr)
);
}
struct eregs {
uint32_t eax, ecx, edx, ebx, esp, ebp, esi, edi;
uint32_t vector;
uint32_t error_code;
uint32_t eip;
uint32_t cs;
uint32_t eflags;
};
void x86_exception(struct eregs *info)
{
do {
hlt();
} while(1);
}

5
src/mainboard/amd/serengeti_cheetah/c Normal file
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rm dsdt.c
rm ssdt2.c
rm dsdt_bus0.c
rm ssdt2_bus0.c
rm ssdt.c

395
src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c Normal file
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#define ASSEMBLY 1
#define __ROMCC__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1
//used by raminit
#define QRANK_DIMM_SUPPORT 1
//used by incoherent_ht
//#define K8_SCAN_PCI_BUS 1
//#define K8_ALLOCATE_IO_RANGE 1
//used by init_cpus and fidvid
#define K8_SET_FIDVID 1
//if we want to wait for core1 done before DQS training, set it to 0
#define K8_SET_FIDVID_CORE0_ONLY 1
//0: three for in bsp, only this one support F0_F1 workaround
//1: on every core0
//2: one for on bsp
//#define MEM_TRAIN_SEQ 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#include <stdint.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#if 0
static void post_code(uint8_t value) {
#if 1
int i;
for(i=0;i<0x80000;i++) {
outb(value, 0x80);
}
#endif
}
#endif
#if USE_FAILOVER_IMAGE==0
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include <cpu/amd/model_fxx_rev.h>
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "cpu/x86/bist.h"
#if USE_FAILOVER_IMAGE==0
#include "lib/delay.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
static void memreset_setup(void)
{
//GPIO on amd8111 to enable MEMRST ????
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
#define SMBUS_HUB 0x18
int ret,i;
unsigned device=(ctrl->channel0[0])>>8;
/* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
i=2;
do {
ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
} while ((ret!=0) && (i-->0));
smbus_write_byte(SMBUS_HUB, 0x03, 0);
}
#if 0
static inline void change_i2c_mux(unsigned device)
{
#define SMBUS_HUB 0x18
int ret, i;
print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n");
i=2;
do {
ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\r\n");
} while ((ret!=0) && (i-->0));
ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\r\n");
}
#endif
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
#include "northbridge/amd/amdk8/amdk8_f.h"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "sdram/generic_sdram.c"
/* tyan does not want the default */
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#define RC0 ((1<<0)<<8)
#define RC1 ((1<<1)<<8)
#define RC2 ((1<<2)<<8)
#define RC3 ((1<<3)<<8)
#define DIMM0 0x50
#define DIMM1 0x51
#define DIMM2 0x52
#define DIMM3 0x53
#define DIMM4 0x54
#define DIMM5 0x55
#define DIMM6 0x56
#define DIMM7 0x57
#include "cpu/amd/car/copy_and_run.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
#include "cpu/amd/model_fxx/fidvid.c"
#endif
#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
{
unsigned last_boot_normal_x = last_boot_normal();
/* Is this a cpu only reset? or Is this a secondary cpu? */
if ((cpu_init_detectedx) || (!boot_cpu())) {
if (last_boot_normal_x) {
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* Setup the rom access for 4M */
amd8111_enable_rom();
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal_x) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
__asm__ volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
);
fallback_image:
#if HAVE_FAILOVER_BOOT==1
__asm__ volatile ("jmp __fallback_image"
: /* outputs */
: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
)
#endif
;
}
#endif
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
#if HAVE_FAILOVER_BOOT==1
#if USE_FAILOVER_IMAGE==1
failover_process(bist, cpu_init_detectedx);
#else
real_main(bist, cpu_init_detectedx);
#endif
#else
#if USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx);
#endif
real_main(bist, cpu_init_detectedx);
#endif
}
#if USE_FAILOVER_IMAGE==0
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
//first node
RC0|DIMM0, RC0|DIMM2, 0, 0,
RC0|DIMM1, RC0|DIMM3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
//second node
RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,
RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 2
// third node
RC2|DIMM0, RC2|DIMM2, 0, 0,
RC2|DIMM1, RC2|DIMM3, 0, 0,
// four node
RC3|DIMM0, RC3|DIMM2, RC3|DIMM4, RC3|DIMM6,
RC3|DIMM1, RC3|DIMM3, RC3|DIMM5, RC3|DIMM7,
#endif
};
struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
int needs_reset; int i;
unsigned bsp_apicid = 0;
if (bist == 0) {
//It's the time to set ctrl in sysinfo now;
fill_mem_ctrl(CONFIG_MAX_PHYSICAL_CPUS, sysinfo->ctrl, spd_addr);
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
}
// post_code(0x32);
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE);
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(","); print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
setup_serengeti_cheetah_resource_map();
#if 0
dump_pci_device(PCI_DEV(0, 0x18, 0));
dump_pci_device(PCI_DEV(0, 0x19, 0));
#endif
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
#if MEM_TRAIN_SEQ == 1
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
#endif
setup_coherent_ht_domain(); // routing table and start other core0
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS==1
// It is said that we should start core1 after all core0 launched
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
* So here need to make sure last core0 is started, esp for two way system,
* (there may be apic id conflicts in that case)
*/
start_other_cores();
wait_all_other_cores_started(bsp_apicid);
#endif
/* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if 0
//it your CPU min fid is 1G, you can change HT to 1G and FID to max one time.
needs_reset = optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo);
#endif
#if K8_SET_FIDVID == 1
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
}
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
init_fidvid_bsp(bsp_apicid);
// show final fid and vid
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
}
#endif
#if 1
needs_reset = optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo);
// fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) {
print_info("ht reset -\r\n");
soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
}
#endif
allow_all_aps_stop(bsp_apicid);
#if 0
//It's the time to set ctrl in sysinfo now;
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
#endif
enable_smbus();
#if 0
for(i=0;i<4;i++) {
activate_spd_rom(&cpu[i]);
dump_smbus_registers();
}
#endif
#if 0
for(i=1;i<256;i<<=1) {
change_i2c_mux(i);
dump_smbus_registers();
}
#endif
memreset_setup();
//do we need apci timer, tsc...., only debug need it for better output
/* all ap stopped? */
// init_timer(); // Need to use TMICT to synconize FID/VID
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
#if 0
print_pci_devices();
#endif
#if 0
// dump_pci_devices();
dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98);
dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98);
#endif
post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
}
#endif

6
src/mainboard/amd/serengeti_cheetah/chip.h Normal file
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extern struct chip_operations mainboard_amd_serengeti_cheetah_ops;
struct mainboard_amd_serengeti_cheetah_config {
// int fixup_scsi;
// int fixup_vga;
};

98
src/mainboard/amd/serengeti_cheetah/cmos.layout Normal file
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entries
#start-bit length config config-ID name
#0 8 r 0 seconds
#8 8 r 0 alarm_seconds
#16 8 r 0 minutes
#24 8 r 0 alarm_minutes
#32 8 r 0 hours
#40 8 r 0 alarm_hours
#48 8 r 0 day_of_week
#56 8 r 0 day_of_month
#64 8 r 0 month
#72 8 r 0 year
#80 4 r 0 rate_select
#84 3 r 0 REF_Clock
#87 1 r 0 UIP
#88 1 r 0 auto_switch_DST
#89 1 r 0 24_hour_mode
#90 1 r 0 binary_values_enable
#91 1 r 0 square-wave_out_enable
#92 1 r 0 update_finished_enable
#93 1 r 0 alarm_interrupt_enable
#94 1 r 0 periodic_interrupt_enable
#95 1 r 0 disable_clock_updates
#96 288 r 0 temporary_filler
0 384 r 0 reserved_memory
384 1 e 4 boot_option
385 1 e 4 last_boot
386 1 e 1 ECC_memory
388 4 r 0 reboot_bits
392 3 e 5 baud_rate
395 1 e 1 hw_scrubber
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
399 1 e 2 dual_core
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
416 4 e 7 boot_first
420 4 e 7 boot_second
424 4 e 7 boot_third
428 4 h 0 boot_index
432 8 h 0 boot_countdown
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
728 256 h 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
5 0 115200
5 1 57600
5 2 38400
5 3 19200
5 4 9600
5 5 4800
5 6 2400
5 7 1200
6 6 Notice
6 7 Info
6 8 Debug
6 9 Spew
7 0 Network
7 1 HDD
7 2 Floppy
7 8 Fallback_Network
7 9 Fallback_HDD
7 10 Fallback_Floppy
#7 3 ROM
8 0 400Mhz
8 1 333Mhz
8 2 266Mhz
8 3 200Mhz
9 0 off
9 1 87.5%
9 2 75.0%
9 3 62.5%
9 4 50.0%
9 5 37.5%
9 6 25.0%
9 7 12.5%
checksums
checksum 392 983 984

172
src/mainboard/amd/serengeti_cheetah/dx/amd8111.asl Normal file
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/*
* Copyright 2005 AMD
*/
//AMD8111
Name (APIC, Package (0x04)
{
Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10},// 0x0004ffff : assusme 8131 is present
Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11},
Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12},
Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13}
})
Name (PICM, Package (0x04)
{
Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00},
Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00},
Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00},
Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00}
})
Name (DNCG, Ones)
Method (_PRT, 0, NotSerialized)
{
If (LEqual (^DNCG, Ones)) {
Store (DADD(\_SB.PCI0.SBDN, 0x0001ffff), Local0)
// Update the Device Number according to SBDN
Store(Local0, Index (DeRefOf (Index (PICM, 0)), 0))
Store(Local0, Index (DeRefOf (Index (PICM, 1)), 0))
Store(Local0, Index (DeRefOf (Index (PICM, 2)), 0))
Store(Local0, Index (DeRefOf (Index (PICM, 3)), 0))
Store(Local0, Index (DeRefOf (Index (APIC, 0)), 0))
Store(Local0, Index (DeRefOf (Index (APIC, 1)), 0))
Store(Local0, Index (DeRefOf (Index (APIC, 2)), 0))
Store(Local0, Index (DeRefOf (Index (APIC, 3)), 0))
Store (0x00, ^DNCG)
}
If (LNot (PICF)) {
Return (PICM)
}
Else {
Return (APIC)
}
}
Device (SBC3)
{
/* acpi smbus it should be 0x00040003 if 8131 present */
Method (_ADR, 0, NotSerialized)
{
Return (DADD(\_SB.PCI0.SBDN, 0x00010003))
}
OperationRegion (PIRQ, PCI_Config, 0x56, 0x02)
Field (PIRQ, ByteAcc, Lock, Preserve)
{
PIBA, 8,
PIDC, 8
}
/*
OperationRegion (TS3_, PCI_Config, 0xC4, 0x02)
Field (TS3_, DWordAcc, NoLock, Preserve)
{
PTS3, 16
}
*/
}
Device (HPET)
{
Name (HPT, 0x00)
Name (_HID, EisaId ("PNP0103"))
Name (_UID, 0x00)
Method (_STA, 0, NotSerialized)
{
Return (0x0F)
}
Method (_CRS, 0, NotSerialized)
{
Name (BUF0, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0xFED00000, 0x00000400)
})
Return (BUF0)
}
}
Include ("amd8111_pic.asl")
Include ("amd8111_isa.asl")
Device (TP2P)
{
/* 8111 P2P and it should 0x00030000 when 8131 present*/
Method (_ADR, 0, NotSerialized)
{
Return (DADD(\_SB.PCI0.SBDN, 0x00000000))
}
Method (_PRW, 0, NotSerialized)
{
If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x08, 0x03 }) }
Else { Return (Package (0x02) { 0x08, 0x01 }) }
}
Device (USB0)
{
Name (_ADR, 0x00000000)
Method (_PRW, 0, NotSerialized)
{
If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x0F, 0x03 }) }
Else { Return (Package (0x02) { 0x0F, 0x01 }) }
}
}
Device (USB1)
{
Name (_ADR, 0x00000001)
Method (_PRW, 0, NotSerialized)
{
If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x0F, 0x03 }) }
Else { Return (Package (0x02) { 0x0F, 0x01 }) }
}
}
Name (APIC, Package (0x0C)
{
Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, //USB
Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 },
Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },
Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 },
Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10 }, //Slot 4
Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11 },
Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12 },
Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13 },
Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x11 }, //Slot 3
Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x12 },
Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x13 },
Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x10 }
})
Name (PICM, Package (0x0C)
{
Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //USB
Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //Slot 4
Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, //Slot 3
Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }
})
Method (_PRT, 0, NotSerialized)
{
If (LNot (PICF)) { Return (PICM) }
Else { Return (APIC) }
}
}

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/*
* Copyright 2005 AMD
*/
//AMD8111 isa
Device (ISA)
{
/* lpc 0x00040000 */
Method (_ADR, 0, NotSerialized)
{
Return (DADD(\_SB.PCI0.SBDN, 0x00010000))
}
OperationRegion (PIRY, PCI_Config, 0x51, 0x02) // LPC Decode Registers
Field (PIRY, ByteAcc, NoLock, Preserve)
{
Z000, 2, // Parallel Port Range
, 1,
ECP, 1, // ECP Enable
FDC1, 1, // Floppy Drive Controller 1
FDC2, 1, // Floppy Drive Controller 2
Offset (0x01),
Z001, 3, // Serial Port A Range
SAEN, 1, // Serial Post A Enabled
Z002, 3, // Serial Port B Range
SBEN, 1 // Serial Post B Enabled
}
Device (PIC)
{
Name (_HID, EisaId ("PNP0000"))
Name (_CRS, ResourceTemplate ()
{
IO (Decode16, 0x0020, 0x0020, 0x01, 0x02)
IO (Decode16, 0x00A0, 0x00A0, 0x01, 0x02)
IRQ (Edge, ActiveHigh, Exclusive) {2}
})
}
Device (DMA1)
{
Name (_HID, EisaId ("PNP0200"))
Name (_CRS, ResourceTemplate ()
{
IO (Decode16, 0x0000, 0x0000, 0x01, 0x10)
IO (Decode16, 0x0080, 0x0080, 0x01, 0x10)
IO (Decode16, 0x00C0, 0x00C0, 0x01, 0x20)
DMA (Compatibility, NotBusMaster, Transfer16) {4}
})
}
Device (TMR)
{
Name (_HID, EisaId ("PNP0100"))
Name (_CRS, ResourceTemplate ()
{
IO (Decode16, 0x0040, 0x0040, 0x01, 0x04)
IRQ (Edge, ActiveHigh, Exclusive) {0}
})
}
Device (RTC)
{
Name (_HID, EisaId ("PNP0B00"))
Name (_CRS, ResourceTemplate ()
{
IO (Decode16, 0x0070, 0x0070, 0x01, 0x06)
IRQ (Edge, ActiveHigh, Exclusive) {8}
})
}
Device (SPKR)
{
Name (_HID, EisaId ("PNP0800"))
Name (_CRS, ResourceTemplate ()
{
IO (Decode16, 0x0061, 0x0061, 0x01, 0x01)
})
}
Device (COPR)
{
Name (_HID, EisaId ("PNP0C04"))
Name (_CRS, ResourceTemplate ()
{
IO (Decode16, 0x00F0, 0x00F0, 0x01, 0x10)
IRQ (Edge, ActiveHigh, Exclusive) {13}
})
}
Device (SYSR)
{
Name (_HID, EisaId ("PNP0C02"))
Name (_UID, 0x00)
Name (SYR1, ResourceTemplate ()
{
IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02) //wrh092302 - added to report Thor NVRAM
IO (Decode16, 0x1100, 0x117F, 0x01, 0x80) //wrh092302 - added to report Thor NVRAM
IO (Decode16, 0x1180, 0x11FF, 0x01, 0x80)
IO (Decode16, 0x0010, 0x0010, 0x01, 0x10)
IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E)
IO (Decode16, 0x0044, 0x0044, 0x01, 0x1C)
IO (Decode16, 0x0062, 0x0062, 0x01, 0x02)
IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B)
IO (Decode16, 0x0076, 0x0076, 0x01, 0x0A)
IO (Decode16, 0x0090, 0x0090, 0x01, 0x10)
IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E)
IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10)
IO (Decode16, 0x0B78, 0x0B78, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error
IO (Decode16, 0x0190, 0x0190, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error
})
Method (_CRS, 0, NotSerialized)
{
Return (SYR1)
}
}
Device (MEM)
{
Name (_HID, EisaId ("PNP0C02"))
Name (_UID, 0x01)
Method (_CRS, 0, NotSerialized)
{
Name (BUF0, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0x000E0000, 0x00020000) // BIOS E4000-FFFFF
Memory32Fixed (ReadWrite, 0x000C0000, 0x00000000) // video BIOS c0000-c8404
Memory32Fixed (ReadWrite, 0xFEC00000, 0x00001000) // I/O APIC
Memory32Fixed (ReadWrite, 0xFFC00000, 0x00380000) // LPC forwarded, 4 MB w/ROM
Memory32Fixed (ReadWrite, 0xFEE00000, 0x00001000) // Local APIC
Memory32Fixed (ReadWrite, 0xFFF80000, 0x00080000) // Overlay BIOS
Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS
Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS
})
// Read the Video Memory length
CreateDWordField (BUF0, 0x14, CLEN)
CreateDWordField (BUF0, 0x10, CBAS)
ShiftLeft (VGA1, 0x09, Local0)
Store (Local0, CLEN)
Return (BUF0)
}
}
Device (PS2M)
{
Name (_HID, EisaId ("PNP0F13"))
Name (_CRS, ResourceTemplate ()
{
IRQNoFlags () {12}
})
Method (_STA, 0, NotSerialized)
{
And (FLG0, 0x04, Local0)
If (LEqual (Local0, 0x04)) { Return (0x0F) }
Else { Return (0x00) }
}
}
Device (PS2K)
{
Name (_HID, EisaId ("PNP0303"))
Name (_CRS, ResourceTemplate ()
{
IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
IRQNoFlags () {1}
})
}
Include ("superio.asl")
}

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/*
* Copyright 2005 AMD
*/
//AMD8111 pic LNKA B C D
Device (LNKA)
{
Name (_HID, EisaId ("PNP0C0F"))
Name (_UID, 0x01)
Method (_STA, 0, NotSerialized)
{
And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local0)
If (LEqual (Local0, 0x00)) { Return (0x09) } //Disabled
Else { Return (0x0B) } //Enabled
}
Method (_PRS, 0, NotSerialized)
{
Name (BUFA, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared) {3,5,10,11}
})
Return (BUFA)
}
Method (_DIS, 0, NotSerialized)
{
Store (0x01, Local3)
And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local1)
Store (Local1, Local2)
If (LGreater (Local1, 0x07))
{
Subtract (Local1, 0x08, Local1)
}
ShiftLeft (Local3, Local1, Local3)
Not (Local3, Local3)
And (\_SB.PCI0.SBC3.PIBA, 0xF0, \_SB.PCI0.SBC3.PIBA)
}
Method (_CRS, 0, NotSerialized)
{
Name (BUFA, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared) {}
})
CreateByteField (BUFA, 0x01, IRA1)
CreateByteField (BUFA, 0x02, IRA2)
Store (0x00, Local3)
Store (0x00, Local4)
And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local1)
If (LNot (LEqual (Local1, 0x00)))
{ // Routing enable
If (LGreater (Local1, 0x07))
{
Subtract (Local1, 0x08, Local2)
ShiftLeft (One, Local2, Local4)
}
Else
{
If (LGreater (Local1, 0x00))
{
ShiftLeft (One, Local1, Local3)
}
}
Store (Local3, IRA1)
Store (Local4, IRA2)
}
Return (BUFA)
}
Method (_SRS, 1, NotSerialized)
{
CreateByteField (Arg0, 0x01, IRA1)
CreateByteField (Arg0, 0x02, IRA2)
ShiftLeft (IRA2, 0x08, Local0)
Or (Local0, IRA1, Local0)
Store (0x00, Local1)
ShiftRight (Local0, 0x01, Local0)
While (LGreater (Local0, 0x00))
{
Increment (Local1)
ShiftRight (Local0, 0x01, Local0)
}
And (\_SB.PCI0.SBC3.PIBA, 0xF0, \_SB.PCI0.SBC3.PIBA)
Or (\_SB.PCI0.SBC3.PIBA, Local1, \_SB.PCI0.SBC3.PIBA)
}
}
Device (LNKB)
{
Name (_HID, EisaId ("PNP0C0F"))
Name (_UID, 0x02)
Method (_STA, 0, NotSerialized)
{
And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local0)
If (LEqual (Local0, 0x00)) { Return (0x09) }
Else { Return (0x0B) }
}
Method (_PRS, 0, NotSerialized)
{
Name (BUFB, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared) {3,5,10,11}
})
Return (BUFB)
}
Method (_DIS, 0, NotSerialized)
{
Store (0x01, Local3)
And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local1)
ShiftRight (Local1, 0x04, Local1)
Store (Local1, Local2)
If (LGreater (Local1, 0x07))
{
Subtract (Local1, 0x08, Local1)
}
ShiftLeft (Local3, Local1, Local3)
Not (Local3, Local3)
And (\_SB.PCI0.SBC3.PIBA, 0x0F, \_SB.PCI0.SBC3.PIBA)
}
Method (_CRS, 0, NotSerialized)
{
Name (BUFB, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared) {}
})
CreateByteField (BUFB, 0x01, IRB1)
CreateByteField (BUFB, 0x02, IRB2)
Store (0x00, Local3)
Store (0x00, Local4)
And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local1)
ShiftRight (Local1, 0x04, Local1)
If (LNot (LEqual (Local1, 0x00)))
{
If (LGreater (Local1, 0x07))
{
Subtract (Local1, 0x08, Local2)
ShiftLeft (One, Local2, Local4)
}
Else
{
If (LGreater (Local1, 0x00))
{
ShiftLeft (One, Local1, Local3)
}
}
Store (Local3, IRB1)
Store (Local4, IRB2)
}
Return (BUFB)
}
Method (_SRS, 1, NotSerialized)
{
CreateByteField (Arg0, 0x01, IRB1)
CreateByteField (Arg0, 0x02, IRB2)
ShiftLeft (IRB2, 0x08, Local0)
Or (Local0, IRB1, Local0)
Store (0x00, Local1)
ShiftRight (Local0, 0x01, Local0)
While (LGreater (Local0, 0x00))
{
Increment (Local1)
ShiftRight (Local0, 0x01, Local0)
}
And (\_SB.PCI0.SBC3.PIBA, 0x0F, \_SB.PCI0.SBC3.PIBA)
ShiftLeft (Local1, 0x04, Local1)
Or (\_SB.PCI0.SBC3.PIBA, Local1, \_SB.PCI0.SBC3.PIBA)
}
}
Device (LNKC)
{
Name (_HID, EisaId ("PNP0C0F"))
Name (_UID, 0x03)
Method (_STA, 0, NotSerialized)
{
And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local0)
If (LEqual (Local0, 0x00)) { Return (0x09) }
Else { Return (0x0B) }
}
Method (_PRS, 0, NotSerialized)
{
Name (BUFA, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared) {3,5,10,11}
})
Return (BUFA)
}
Method (_DIS, 0, NotSerialized)
{
Store (0x01, Local3)
And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local1)
Store (Local1, Local2)
If (LGreater (Local1, 0x07))
{
Subtract (Local1, 0x08, Local1)
}
ShiftLeft (Local3, Local1, Local3)
Not (Local3, Local3)
And (\_SB.PCI0.SBC3.PIDC, 0xF0, \_SB.PCI0.SBC3.PIDC)
}
Method (_CRS, 0, NotSerialized)
{
Name (BUFA, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared) {}
})
CreateByteField (BUFA, 0x01, IRA1)
CreateByteField (BUFA, 0x02, IRA2)
Store (0x00, Local3)
Store (0x00, Local4)
And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local1)
If (LNot (LEqual (Local1, 0x00)))
{
If (LGreater (Local1, 0x07))
{
Subtract (Local1, 0x08, Local2)
ShiftLeft (One, Local2, Local4)
}
Else
{
If (LGreater (Local1, 0x00))
{
ShiftLeft (One, Local1, Local3)
}
}
Store (Local3, IRA1)
Store (Local4, IRA2)
}
Return (BUFA)
}
Method (_SRS, 1, NotSerialized)
{
CreateByteField (Arg0, 0x01, IRA1)
CreateByteField (Arg0, 0x02, IRA2)
ShiftLeft (IRA2, 0x08, Local0)
Or (Local0, IRA1, Local0)
Store (0x00, Local1)
ShiftRight (Local0, 0x01, Local0)
While (LGreater (Local0, 0x00))
{
Increment (Local1)
ShiftRight (Local0, 0x01, Local0)
}
And (\_SB.PCI0.SBC3.PIDC, 0xF0, \_SB.PCI0.SBC3.PIDC)
Or (\_SB.PCI0.SBC3.PIDC, Local1, \_SB.PCI0.SBC3.PIDC)
}
}
Device (LNKD)
{
Name (_HID, EisaId ("PNP0C0F"))
Name (_UID, 0x04)
Method (_STA, 0, NotSerialized)
{
And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local0)
If (LEqual (Local0, 0x00)) { Return (0x09) }
Else { Return (0x0B) }
}
Method (_PRS, 0, NotSerialized)
{
Name (BUFB, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared) {3,5,10,11}
})
Return (BUFB)
}
Method (_DIS, 0, NotSerialized)
{
Store (0x01, Local3)
And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local1)
ShiftRight (Local1, 0x04, Local1)
Store (Local1, Local2)
If (LGreater (Local1, 0x07))
{
Subtract (Local1, 0x08, Local1)
}
ShiftLeft (Local3, Local1, Local3)
Not (Local3, Local3)
And (\_SB.PCI0.SBC3.PIDC, 0x0F, \_SB.PCI0.SBC3.PIDC)
}
Method (_CRS, 0, NotSerialized)
{
Name (BUFB, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared) {}
})
CreateByteField (BUFB, 0x01, IRB1)
CreateByteField (BUFB, 0x02, IRB2)
Store (0x00, Local3)
Store (0x00, Local4)
And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local1)
ShiftRight (Local1, 0x04, Local1)
If (LNot (LEqual (Local1, 0x00)))
{
If (LGreater (Local1, 0x07))
{
Subtract (Local1, 0x08, Local2)
ShiftLeft (One, Local2, Local4)
}
Else
{
If (LGreater (Local1, 0x00))
{
ShiftLeft (One, Local1, Local3)
}
}
Store (Local3, IRB1)
Store (Local4, IRB2)
}
Return (BUFB)
}
Method (_SRS, 1, NotSerialized)
{
CreateByteField (Arg0, 0x01, IRB1)
CreateByteField (Arg0, 0x02, IRB2)
ShiftLeft (IRB2, 0x08, Local0)
Or (Local0, IRB1, Local0)
Store (0x00, Local1)
ShiftRight (Local0, 0x01, Local0)
While (LGreater (Local0, 0x00))
{
Increment (Local1)
ShiftRight (Local0, 0x01, Local0)
}
And (\_SB.PCI0.SBC3.PIDC, 0x0F, \_SB.PCI0.SBC3.PIDC)
ShiftLeft (Local1, 0x04, Local1)
Or (\_SB.PCI0.SBC3.PIDC, Local1, \_SB.PCI0.SBC3.PIDC)
}
}

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/*
* Copyright 2005 AMD
*/
Device (PG0A)
{
/* 8132 pcix bridge*/
Method (_ADR, 0, NotSerialized)
{
Return (DADD(GHCD(HCIN, 0), 0x00000000))
}
Method (_PRW, 0, NotSerialized)
{
If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) }
Else { Return (Package (0x02) { 0x29, 0x01 }) }
}
Name (APIC, Package (0x14)
{
// Slot A - PIRQ BCDA
Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x19 }, //Slot 2
Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1A },
Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x1B },
Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x18 },
//Cypress Slot A - PIRQ BCDA
Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x19 }, //?
Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x1A },
Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x1B },
Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x18 },
//Cypress Slot B - PIRQ CDAB
Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x1A }, //?
Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x1B },
Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x18 },
Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x19 },
//Cypress Slot C - PIRQ DABC
Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x1B }, //?
Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x18 },
Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x19 },
Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x1A },
//Cypress Slot D - PIRQ ABCD
Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x18 }, //?
Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x19 },
Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x1A },
Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x1B }
})
Name (PICM, Package (0x14)
{
Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//Slot 2
Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },
Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },
Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },
Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },
Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },
Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },
Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },
Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 },
Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 },
Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 },
Package (0x04) { 0x0006FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },
Package (0x04) { 0x0006FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
Package (0x04) { 0x0006FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
Package (0x04) { 0x0006FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
})
Method (_PRT, 0, NotSerialized)
{
If (LNot (PICF)) { Return (PICM) }
Else { Return (APIC) }
}
}
Device (PG0B)
{
/* 8132 pcix bridge 2 */
Method (_ADR, 0, NotSerialized)
{
Return (DADD(GHCD(HCIN, 0), 0x00010000))
}
Method (_PRW, 0, NotSerialized)
{
If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) }
Else { Return (Package (0x02) { 0x22, 0x01 }) }
}
Name (APIC, Package (0x04)
{
// Slot A - PIRQ ABCD
Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x1F },// Slot 1
Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x20 },
Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x21 },
Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x22 }
})
Name (PICM, Package (0x04)
{
Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1
Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
})
Method (_PRT, 0, NotSerialized)
{
If (LNot (PICF)) { Return (PICM) }
Else { Return (APIC) }
}
}

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// AMD8151
Device (AGPB)
{
Method (_ADR, 0, NotSerialized)
{
Return (DADD(GHCD(HCIN, 0), 0x00010000))
}
Name (APIC, Package (0x04)
{
Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 },
Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 },
Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },
Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 }
})
Name (PICM, Package (0x04)
{
Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },
Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
})
Method (_PRT, 0, NotSerialized)
{
If (LNot (PICF)) { Return (PICM) }
Else { Return (APIC) }
}
}

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/*
* Copyright 2005 AMD
*/
//AMD k8 util for BUSB and res range
Scope (\_SB)
{
Name (OSTB, Ones)
Method (OSTP, 0, NotSerialized)
{
If (LEqual (^OSTB, Ones))
{
Store (0x00, ^OSTB)
}
Return (^OSTB)
}
Method (SEQL, 2, Serialized)
{
Store (SizeOf (Arg0), Local0)
Store (SizeOf (Arg1), Local1)
If (LNot (LEqual (Local0, Local1))) { Return (Zero) }
Name (BUF0, Buffer (Local0) {})
Store (Arg0, BUF0)
Name (BUF1, Buffer (Local0) {})
Store (Arg1, BUF1)
Store (Zero, Local2)
While (LLess (Local2, Local0))
{
Store (DerefOf (Index (BUF0, Local2)), Local3)
Store (DerefOf (Index (BUF1, Local2)), Local4)
If (LNot (LEqual (Local3, Local4))) { Return (Zero) }
Increment (Local2)
}
Return (One)
}
Method (DADD, 2, NotSerialized)
{
Store( Arg1, Local0)
Store( Arg0, Local1)
Add( ShiftLeft(Local1,16), Local0, Local0)
Return (Local0)
}
Method (GHCE, 1, NotSerialized) // check if the HC enabled
{
Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1)
if(LEqual ( And(Local1, 0x01), 0x01)) { Return (0x0F) }
Else { Return (0x00) }
}
Method (GHCN, 1, NotSerialized) // get the node num for the HC
{
Store (0x00, Local0)
Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1)
Store (ShiftRight( And (Local1, 0xf0), 0x04), Local0)
Return (Local0)
}
Method (GHCL, 1, NotSerialized) // get the link num on node for the HC
{
Store (0x00, Local0)
Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1)
Store (ShiftRight( And (Local1, 0xf00), 0x08), Local0)
Return (Local0)
}
Method (GHCD, 2, NotSerialized) // get the unit id base for the HT device in HC
{
Store (0x00, Local0)
Store (DerefOf (Index (\_SB.PCI0.HCDN, Arg0)), Local1)
Store (Arg1, Local2) // Arg1 could be 3, 2, 1, 0
Multiply (Local2, 0x08, Local2) // change to 24, 16, 8, 0
Store (And (ShiftRight( Local1, Local2), 0xff), Local0)
Return (Local0)
}
Method (GBUS, 2, NotSerialized)
{
Store (0x00, Local0)
While (LLess (Local0, 0x04))
{
Store (DerefOf (Index (\_SB.PCI0.BUSN, Local0)), Local1)
If (LEqual (And (Local1, 0x03), 0x03))
{
If (LEqual (Arg0, ShiftRight (And (Local1, 0x70), 0x04)))
{
If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x0300), 0x08))))
{
Return (ShiftRight (And (Local1, 0x00FF0000), 0x10))
}
}
}
Increment (Local0)
}
Return (0x00)
}
Method (GWBN, 2, NotSerialized)
{
Name (BUF0, ResourceTemplate ()
{
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, // Address Space Granularity
0x0000, // Address Range Minimum
0x0000, // Address Range Maximum
0x0000, // Address Translation Offset
0x0000,,,)
})
CreateWordField (BUF0, 0x08, BMIN)
CreateWordField (BUF0, 0x0A, BMAX)
CreateWordField (BUF0, 0x0E, BLEN)
Store (0x00, Local0)
While (LLess (Local0, 0x04))
{
Store (DerefOf (Index (\_SB.PCI0.BUSN, Local0)), Local1)
If (LEqual (And (Local1, 0x03), 0x03))
{
If (LEqual (Arg0, ShiftRight (And (Local1, 0x70), 0x04)))
{
If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x0300), 0x08))))
{
Store (ShiftRight (And (Local1, 0x00FF0000), 0x10), BMIN)
Store (ShiftRight (Local1, 0x18), BMAX)
Subtract (BMAX, BMIN, BLEN)
Increment (BLEN)
Return (RTAG (BUF0))
}
}
}
Increment (Local0)
}
Return (RTAG (BUF0))
}
Method (GMEM, 2, NotSerialized)
{
Name (BUF0, ResourceTemplate ()
{
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x00000000, // Address Space Granularity
0x00000000, // Address Range Minimum
0x00000000, // Address Range Maximum
0x00000000, // Address Translation Offset
0x00000000,,,
, AddressRangeMemory, TypeStatic)
})
CreateDWordField (BUF0, 0x0A, MMIN)
CreateDWordField (BUF0, 0x0E, MMAX)
CreateDWordField (BUF0, 0x16, MLEN)
Store (0x00, Local0)
Store (0x00, Local4)
Store (0x00, Local3)
While (LLess (Local0, 0x10))
{
Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local1)
Increment (Local0)
Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local2)
If (LEqual (And (Local1, 0x03), 0x03))
{
If (LEqual (Arg0, And (Local2, 0x07)))
{
If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local2, 0x30), 0x04))))
{
Store (ShiftLeft (And (Local1, 0xFFFFFF00), 0x08), MMIN)
Store (ShiftLeft (And (Local2, 0xFFFFFF00), 0x08), MMAX)
Or (MMAX, 0xFFFF, MMAX)
Subtract (MMAX, MMIN, MLEN)
If (Local4)
{
Concatenate (RTAG (BUF0), Local3, Local5)
Store (Local5, Local3)
}
Else
{
If (LOr (LAnd (LEqual (Arg1, 0xFF), LEqual (Arg0, 0x00)), LEqual (Arg1, \_SB.PCI0.SBLK)))
{
Store (\_SB.PCI0.TOM1, MMIN)
Subtract (MMAX, MMIN, MLEN)
Increment (MLEN)
}
Store (RTAG (BUF0), Local3)
}
Increment (Local4)
}
}
}
Increment (Local0)
}
If (LNot (Local4))
{
Store (BUF0, Local3)
}
Return (Local3)
}
Method (GIOR, 2, NotSerialized)
{
Name (BUF0, ResourceTemplate ()
{
DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
0x00000000, // Address Space Granularity
0x00000000, // Address Range Minimum
0x00000000, // Address Range Maximum
0x00000000, // Address Translation Offset
0x00000000,,,
, TypeStatic)
})
CreateDWordField (BUF0, 0x0A, PMIN)
CreateDWordField (BUF0, 0x0E, PMAX)
CreateDWordField (BUF0, 0x16, PLEN)
Store (0x00, Local0)
Store (0x00, Local4)
Store (0x00, Local3)
While (LLess (Local0, 0x08))
{
Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local1)
Increment (Local0)
Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local2)
If (LEqual (And (Local1, 0x03), 0x03))
{
If (LEqual (Arg0, And (Local2, 0x07)))
{
If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local2, 0x30), 0x04))))
{
Store (And (Local1, 0x01FFF000), PMIN)
Store (And (Local2, 0x01FFF000), PMAX)
Or (PMAX, 0x0FFF, PMAX)
Subtract (PMAX, PMIN, PLEN)
Increment (PLEN)
If (Local4)
{
Concatenate (RTAG (BUF0), Local3, Local5)
Store (Local5, Local3)
}
Else
{
If (LGreater (PMAX, PMIN))
{
If (LOr (LAnd (LEqual (Arg1, 0xFF), LEqual (Arg0, 0x00)), LEqual (Arg1, \_SB.PCI0.SBLK)))
{
Store (0x0D00, PMIN)
Subtract (PMAX, PMIN, PLEN)
Increment (PLEN)
}
Store (RTAG (BUF0), Local3)
Increment (Local4)
}
If (And (Local1, 0x10))
{
Store (0x03B0, PMIN)
Store (0x03DF, PMAX)
Store (0x30, PLEN)
If (Local4)
{
Concatenate (RTAG (BUF0), Local3, Local5)
Store (Local5, Local3)
}
Else
{
Store (RTAG (BUF0), Local3)
}
}
}
Increment (Local4)
}
}
}
Increment (Local0)
}
If (LNot (Local4))
{
Store (RTAG (BUF0), Local3)
}
Return (Local3)
}
Method (RTAG, 1, NotSerialized)
{
Store (Arg0, Local0)
Store (SizeOf (Local0), Local1)
Subtract (Local1, 0x02, Local1)
Multiply (Local1, 0x08, Local1)
CreateField (Local0, 0x00, Local1, RETB)
Store (RETB, Local2)
Return (Local2)
}
}

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src/mainboard/amd/serengeti_cheetah/dx/dsdt_lb.dsl Normal file
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/*
* Copyright 2005 AMD
*/
DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-K8", "AMDACPI", 100925440)
{
Scope (_PR)
{
Processor (CPU0, 0x00, 0x0000C010, 0x06) {}
Processor (CPU1, 0x01, 0x00000000, 0x00) {}
Processor (CPU2, 0x02, 0x00000000, 0x00) {}
Processor (CPU3, 0x03, 0x00000000, 0x00) {}
}
Method (FWSO, 0, NotSerialized) { }
Name (_S0, Package (0x04) { 0x00, 0x00, 0x00, 0x00 })
Name (_S1, Package (0x04) { 0x01, 0x01, 0x01, 0x01 })
Name (_S3, Package (0x04) { 0x05, 0x05, 0x05, 0x05 })
Name (_S5, Package (0x04) { 0x07, 0x07, 0x07, 0x07 })
Scope (_SB)
{
Device (PCI0)
{
/* BUS0 root bus */
External (BUSN)
External (MMIO)
External (PCIO)
External (SBLK)
External (TOM1)
External (HCLK)
External (SBDN)
External (HCDN)
External (CBST)
Name (_HID, EisaId ("PNP0A03"))
Name (_ADR, 0x00180000)
Name (_UID, 0x01)
Name (HCIN, 0x00) // HC1
Method (_BBN, 0, NotSerialized)
{
Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
}
Method (_CRS, 0, NotSerialized)
{
Name (BUF0, ResourceTemplate ()
{
IO (Decode16, 0x0CF8, 0x0CF8, 0x01, 0x08) //CF8-CFFh
IO (Decode16, 0xC000, 0xC000, 0x01, 0x80) //8000h
IO (Decode16, 0xC080, 0xC080, 0x01, 0x80) //8080h
WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
0x0000, // Address Space Granularity
0x8100, // Address Range Minimum
0xFFFF, // Address Range Maximum
0x0000, // Address Translation Offset
0x7F00,,,
, TypeStatic) //8100h-FFFFh
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
0x00000000, // Address Space Granularity
0x000C0000, // Address Range Minimum
0x00000000, // Address Range Maximum
0x00000000, // Address Translation Offset
0x00000000,,,
, AddressRangeMemory, TypeStatic) //Video BIOS A0000h-C7FFFh
Memory32Fixed (ReadWrite, 0x000D8000, 0x00004000)//USB HC D8000-DBFFF
WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
0x0000, // Address Space Granularity
0x0000, // Address Range Minimum
0x03AF, // Address Range Maximum
0x0000, // Address Translation Offset
0x03B0,,,
, TypeStatic) //0-CF7h
WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
0x0000, // Address Space Granularity
0x03E0, // Address Range Minimum
0x0CF7, // Address Range Maximum
0x0000, // Address Translation Offset
0x0918,,,
, TypeStatic) //0-CF7h
})
\_SB.OSTP ()
CreateDWordField (BUF0, 0x3E, VLEN)
CreateDWordField (BUF0, 0x36, VMAX)
CreateDWordField (BUF0, 0x32, VMIN)
ShiftLeft (VGA1, 0x09, Local0)
Add (VMIN, Local0, VMAX)
Decrement (VMAX)
Store (Local0, VLEN)
Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
Return (Local3)
}
Include ("pci0_hc.asl")
}
Device (PCI1)
{
Name (_HID, "PNP0A03")
Name (_ADR, 0x00000000)
Name (_UID, 0x02)
Method (_STA, 0, NotSerialized)
{
Return (\_SB.PCI0.CBST)
}
Name (_BBN, 0x00)
}
}
Scope (_GPE)
{
Method (_L08, 0, NotSerialized)
{
Notify (\_SB.PCI0, 0x02) //PME# Wakeup
}
Method (_L0F, 0, NotSerialized)
{
Notify (\_SB.PCI0.TP2P.USB0, 0x02) //USB Wakeup
}
Method (_L22, 0, NotSerialized) // GPIO18 (LID) - Pogo 0 Bridge B
{
Notify (\_SB.PCI0.PG0B, 0x02)
}
Method (_L29, 0, NotSerialized) // GPIO25 (Suspend) - Pogo 0 Bridge A
{
Notify (\_SB.PCI0.PG0A, 0x02)
}
}
Method (_PTS, 1, NotSerialized)
{
Or (Arg0, 0xF0, Local0)
Store (Local0, DBG1)
}
/*
Method (_WAK, 1, NotSerialized)
{
Or (Arg0, 0xE0, Local0)
Store (Local0, DBG1)
}
*/
Name (PICF, 0x00) //Flag Variable for PIC vs. I/O APIC Mode
Method (_PIC, 1, NotSerialized) //PIC Flag and Interface Method
{
Store (Arg0, PICF)
}
OperationRegion (DEBG, SystemIO, 0x80, 0x01)
Field (DEBG, ByteAcc, Lock, Preserve)
{
DBG1, 8
}
OperationRegion (EXTM, SystemMemory, 0x000FF83C, 0x04)
Field (EXTM, WordAcc, Lock, Preserve)
{
AMEM, 32
}
OperationRegion (VGAM, SystemMemory, 0x000C0002, 0x01)
Field (VGAM, ByteAcc, Lock, Preserve)
{
VGA1, 8
}
OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100)
Field (GRAM, ByteAcc, Lock, Preserve)
{
Offset (0x10),
FLG0, 8
}
OperationRegion (GSTS, SystemIO, 0xC028, 0x02)
Field (GSTS, ByteAcc, NoLock, Preserve)
{
, 4,
IRQR, 1
}
OperationRegion (Z007, SystemIO, 0x21, 0x01)
Field (Z007, ByteAcc, NoLock, Preserve)
{
Z008, 8
}
OperationRegion (Z009, SystemIO, 0xA1, 0x01)
Field (Z009, ByteAcc, NoLock, Preserve)
{
Z00A, 8
}
Include ("amdk8_util.asl")
}

2
src/mainboard/amd/serengeti_cheetah/dx/pci0_hc.asl Normal file
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Include ("amd8111.asl") //real SB at first
Include ("amd8131.asl")

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/*
* Copyright 2005 AMD
*/
DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440)
{
Scope (_SB)
{
External (DADD, MethodObj)
External (GHCE, MethodObj)
External (GHCN, MethodObj)
External (GHCL, MethodObj)
External (GHCD, MethodObj)
External (GNUS, MethodObj)
External (GIOR, MethodObj)
External (GMEM, MethodObj)
External (GWBN, MethodObj)
External (GBUS, MethodObj)
External (PICF)
External (\_SB.PCI0.LNKA, DeviceObj)
External (\_SB.PCI0.LNKB, DeviceObj)
External (\_SB.PCI0.LNKC, DeviceObj)
External (\_SB.PCI0.LNKD, DeviceObj)
Device (PCI2)
{
// BUS ? Second HT Chain
Name (HCIN, 0x01) // HC2
Name (_HID, "PNP0A03")
Method (_ADR, 0, NotSerialized) //Fake bus should be 0
{
Return (DADD(GHCN(HCIN), 0x00180000))
}
Name (_UID, 0x03)
Method (_BBN, 0, NotSerialized)
{
Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
}
Method (_STA, 0, NotSerialized)
{
Return (\_SB.GHCE(HCIN))
}
Method (_CRS, 0, NotSerialized)
{
Name (BUF0, ResourceTemplate () { })
Store( GHCN(HCIN), Local4)
Store( GHCL(HCIN), Local5)
Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
Return (Local3)
}
Include ("pci2_hc.asl")
}
}
}

1
src/mainboard/amd/serengeti_cheetah/dx/pci2_hc.asl Normal file
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Include ("amd8151.asl")

1
src/mainboard/amd/serengeti_cheetah/dx/superio.asl Normal file
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// Include ("w83627hf.asl")

149
src/mainboard/amd/serengeti_cheetah/fadt.c Normal file
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/*
* ACPI - create the Fixed ACPI Description Tables (FADT)
* (C) Copyright 2005 Stefan Reinauer <stepan@openbios.org>
*/
#include <string.h>
#include <console/console.h>
#include <arch/acpi.h>
extern unsigned pm_base; /* pm_base should be set in sb acpi */
void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
acpi_header_t *header=&(fadt->header);
printk_debug("pm_base: 0x%04x\n", pm_base);
/* Prepare the header */
memset((void *)fadt,0,sizeof(acpi_fadt_t));
memcpy(header->signature,"FACP",4);
header->length = 244;
header->revision = 1;
memcpy(header->oem_id,OEM_ID,6);
memcpy(header->oem_table_id,"LXBACPI ",8);
memcpy(header->asl_compiler_id,ASLC,4);
header->asl_compiler_revision=0;
fadt->firmware_ctrl=(u32)facs;
fadt->dsdt= (u32)dsdt;
fadt->res1=0x0;
// 3=Workstation,4=Enterprise Server, 7=Performance Server
fadt->preferred_pm_profile=0x03;
fadt->sci_int=9;
// disable system management mode by setting to 0:
fadt->smi_cmd = 0;//pm_base+0x2f;
fadt->acpi_enable = 0xf0;
fadt->acpi_disable = 0xf1;
fadt->s4bios_req = 0x0;
fadt->pstate_cnt = 0xe2;
fadt->pm1a_evt_blk = pm_base;
fadt->pm1b_evt_blk = 0x0000;
fadt->pm1a_cnt_blk = pm_base+0x04;
fadt->pm1b_cnt_blk = 0x0000;
fadt->pm2_cnt_blk = 0x0000;
fadt->pm_tmr_blk = pm_base+0x08;
fadt->gpe0_blk = pm_base+0x20;
fadt->gpe1_blk = pm_base+0xb0;
fadt->pm1_evt_len = 4;
fadt->pm1_cnt_len = 2;
fadt->pm2_cnt_len = 0;
fadt->pm_tmr_len = 4;
fadt->gpe0_blk_len = 4;
fadt->gpe1_blk_len = 8;
fadt->gpe1_base = 16;
fadt->cst_cnt = 0xe3;
fadt->p_lvl2_lat = 101;
fadt->p_lvl3_lat = 1001;
fadt->flush_size = 0;
fadt->flush_stride = 0;
fadt->duty_offset = 1;
fadt->duty_width = 3;
fadt->day_alrm = 0; // 0x7d these have to be
fadt->mon_alrm = 0; // 0x7e added to cmos.layout
fadt->century = 0; // 0x7f to make rtc alrm work
fadt->iapc_boot_arch = 0x3; // See table 5-11
fadt->flags = 0x25;
fadt->res2 = 0;
fadt->reset_reg.space_id = 1;
fadt->reset_reg.bit_width = 8;
fadt->reset_reg.bit_offset = 0;
fadt->reset_reg.resv = 0;
fadt->reset_reg.addrl = 0xcf9;
fadt->reset_reg.addrh = 0x0;
fadt->reset_value = 6;
fadt->x_firmware_ctl_l = (u32)facs;
fadt->x_firmware_ctl_h = 0;
fadt->x_dsdt_l = (u32)dsdt;
fadt->x_dsdt_h = 0;
fadt->x_pm1a_evt_blk.space_id = 1;
fadt->x_pm1a_evt_blk.bit_width = 32;
fadt->x_pm1a_evt_blk.bit_offset = 0;
fadt->x_pm1a_evt_blk.resv = 0;
fadt->x_pm1a_evt_blk.addrl = pm_base;
fadt->x_pm1a_evt_blk.addrh = 0x0;
fadt->x_pm1b_evt_blk.space_id = 1;
fadt->x_pm1b_evt_blk.bit_width = 4;
fadt->x_pm1b_evt_blk.bit_offset = 0;
fadt->x_pm1b_evt_blk.resv = 0;
fadt->x_pm1b_evt_blk.addrl = 0x0;
fadt->x_pm1b_evt_blk.addrh = 0x0;
fadt->x_pm1a_cnt_blk.space_id = 1;
fadt->x_pm1a_cnt_blk.bit_width = 16;
fadt->x_pm1a_cnt_blk.bit_offset = 0;
fadt->x_pm1a_cnt_blk.resv = 0;
fadt->x_pm1a_cnt_blk.addrl = pm_base+4;
fadt->x_pm1a_cnt_blk.addrh = 0x0;
fadt->x_pm1b_cnt_blk.space_id = 1;
fadt->x_pm1b_cnt_blk.bit_width = 2;
fadt->x_pm1b_cnt_blk.bit_offset = 0;
fadt->x_pm1b_cnt_blk.resv = 0;
fadt->x_pm1b_cnt_blk.addrl = 0x0;
fadt->x_pm1b_cnt_blk.addrh = 0x0;
fadt->x_pm2_cnt_blk.space_id = 1;
fadt->x_pm2_cnt_blk.bit_width = 0;
fadt->x_pm2_cnt_blk.bit_offset = 0;
fadt->x_pm2_cnt_blk.resv = 0;
fadt->x_pm2_cnt_blk.addrl = 0x0;
fadt->x_pm2_cnt_blk.addrh = 0x0;
fadt->x_pm_tmr_blk.space_id = 1;
fadt->x_pm_tmr_blk.bit_width = 32;
fadt->x_pm_tmr_blk.bit_offset = 0;
fadt->x_pm_tmr_blk.resv = 0;
fadt->x_pm_tmr_blk.addrl = pm_base+0x08;
fadt->x_pm_tmr_blk.addrh = 0x0;
fadt->x_gpe0_blk.space_id = 1;
fadt->x_gpe0_blk.bit_width = 32;
fadt->x_gpe0_blk.bit_offset = 0;
fadt->x_gpe0_blk.resv = 0;
fadt->x_gpe0_blk.addrl = pm_base+0x20;
fadt->x_gpe0_blk.addrh = 0x0;
fadt->x_gpe1_blk.space_id = 1;
fadt->x_gpe1_blk.bit_width = 64;
fadt->x_gpe1_blk.bit_offset = 16;
fadt->x_gpe1_blk.resv = 0;
fadt->x_gpe1_blk.addrl = pm_base+0xb0;
fadt->x_gpe1_blk.addrh = 0x0;
header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
}

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#include <console/console.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <string.h>
#include <stdint.h>
#if CONFIG_LOGICAL_CPUS==1
#include <cpu/amd/dualcore.h>
#endif
#include <cpu/amd/amdk8_sysconf.h>
#include "mb_sysconf.h"
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
struct mb_sysconf_t mb_sysconf;
static unsigned pci1234x[] =
{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not
//You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
0x0000ff0,
0x0000ff0,
// 0x0000ff0,
// 0x0000ff0,
// 0x0000ff0,
// 0x0000ff0,
// 0x0000ff0,
// 0x0000ff0
};
static unsigned hcdnx[] =
{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
0x20202020,
0x20202020,
// 0x20202020,
// 0x20202020,
// 0x20202020,
// 0x20202020,
// 0x20202020,
// 0x20202020,
};
extern void get_sblk_pci1234(void);
static unsigned get_bus_conf_done = 0;
void get_bus_conf(void)
{
unsigned apicid_base;
device_t dev;
int i;
struct mb_sysconf_t *m;
if(get_bus_conf_done == 1) return; //do it only once
get_bus_conf_done = 1;
sysconf.mb = &mb_sysconf;
m = sysconf.mb;
sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
for(i=0;i<sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i];
sysconf.hcdn[i] = hcdnx[i];
}
get_sblk_pci1234();
sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff;
m->sbdn3 = sysconf.hcdn[0] & 0xff;
m->sbdn5 = sysconf.hcdn[1] & 0xff;
m->bus_8132_0 = (sysconf.pci1234[0] >> 16) & 0xff;
m->bus_8111_0 = m->bus_8132_0;
/* 8111 */
dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn,0));
if (dev) {
m->bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
#if HT_CHAIN_END_UNITID_BASE >= HT_CHAIN_UNITID_BASE
m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
m->bus_isa++;
// printk_debug("bus_isa=%d\n",bus_isa);
#endif
}
else {
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8111_0, sysconf.sbdn);
}
/* 8132-1 */
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3,0));
if (dev) {
m->bus_8132_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
else {
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132_0, m->sbdn3);
}
/* 8132-2 */
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1,0));
if (dev) {
m->bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
m->bus_isa++;
// printk_debug("bus_isa=%d\n",bus_isa);
#endif
}
else {
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132_0, m->sbdn3+1);
}
/* HT chain 1 */
if((sysconf.pci1234[1] & 0x1) == 1) {
m->bus_8151_0 = (sysconf.pci1234[1] >> 16) & 0xff;
/* 8151 */
dev = dev_find_slot(m->bus_8151_0, PCI_DEVFN(m->sbdn5+1, 0));
if (dev) {
m->bus_8151_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
// printk_debug("bus_8151_1=%d\n",bus_8151_1);
m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
m->bus_isa++;
}
else {
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8151_0, m->sbdn5+1);
}
}
/*I/O APICs: APIC ID Version State Address*/
#if CONFIG_LOGICAL_CPUS==1
apicid_base = get_apicid_base(3);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
#endif
m->apicid_8111 = apicid_base+0;
m->apicid_8132_1 = apicid_base+1;
m->apicid_8132_2 = apicid_base+2;
}

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/* This file was generated by getpir.c, do not modify!
(but if you do, please run checkpir on it to verify)
Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
*/
#include <console/console.h>
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
#include <arch/pirq_routing.h>
#include <cpu/amd/amdk8_sysconf.h>
#include "mb_sysconf.h"
static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
uint8_t slot, uint8_t rfu)
{
pirq_info->bus = bus;
pirq_info->devfn = devfn;
pirq_info->irq[0].link = link0;
pirq_info->irq[0].bitmap = bitmap0;
pirq_info->irq[1].link = link1;
pirq_info->irq[1].bitmap = bitmap1;
pirq_info->irq[2].link = link2;
pirq_info->irq[2].bitmap = bitmap2;
pirq_info->irq[3].link = link3;
pirq_info->irq[3].bitmap = bitmap3;
pirq_info->slot = slot;
pirq_info->rfu = rfu;
}
extern void get_bus_conf(void);
unsigned long write_pirq_routing_table(unsigned long addr)
{
struct irq_routing_table *pirq;
struct irq_info *pirq_info;
unsigned slot_num;
uint8_t *v;
uint8_t sum=0;
int i;
struct mb_sysconf_t *m;
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
m = sysconf.mb;
/* Align the table to be 16 byte aligned. */
addr += 15;
addr &= ~15;
/* This table must be betweeen 0xf0000 & 0x100000 */
printk_info("Writing IRQ routing tables to 0x%x...", addr);
pirq = (void *)(addr);
v = (uint8_t *)(addr);
pirq->signature = PIRQ_SIGNATURE;
pirq->version = PIRQ_VERSION;
pirq->rtr_bus = m->bus_8111_0;
pirq->rtr_devfn = ((sysconf.sbdn+1)<<3)|0;
pirq->exclusive_irqs = 0;
pirq->rtr_vendor = 0x1022;
pirq->rtr_device = 0x746b;
pirq->miniport_data = 0;
memset(pirq->rfu, 0, sizeof(pirq->rfu));
pirq_info = (void *) ( &pirq->checksum + 1);
slot_num = 0;
{
device_t dev;
dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn+1,3));
if (dev) {
/* initialize PCI interupts - these assignments depend
on the PCB routing of PINTA-D
PINTA = IRQ3
PINTB = IRQ5
PINTC = IRQ10
PINTD = IRQ11
*/
pci_write_config16(dev, 0x56, 0xba53);
}
}
//pci bridge
printk_debug("setting Onboard AMD Southbridge \n");
static const unsigned char slotIrqs_1_4[4] = { 3, 5, 10, 11 };
pci_assign_irqs(m->bus_8111_0, sysconf.sbdn+1, slotIrqs_1_4);
write_pirq_info(pirq_info, m->bus_8111_0, ((sysconf.sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; slot_num++;
printk_debug("setting Onboard AMD USB \n");
static const unsigned char slotIrqs_8111_1_0[4] = { 0, 0, 0, 11};
pci_assign_irqs(m->bus_8111_1, 0, slotIrqs_8111_1_0);
write_pirq_info(pirq_info, m->bus_8111_1,0, 0, 0, 0, 0, 0, 0, 0x4, 0xdef8, 0, 0);
pirq_info++; slot_num++;
//pcix bridge
// write_pirq_info(pirq_info, m->bus_8132_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
// pirq_info++; slot_num++;
if(sysconf.pci1234[1] & 0xf) {
//agp bridge
write_pirq_info(pirq_info, m->bus_8151_0, (m->sbdn5<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
}
pirq_info++; slot_num++;
pirq->size = 32 + 16 * slot_num;
for (i = 0; i < pirq->size; i++)
sum += v[i];
sum = pirq->checksum - sum;
if (sum != pirq->checksum) {
pirq->checksum = sum;
}
printk_info("done.\n");
return (unsigned long) pirq_info;
}

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src/mainboard/amd/serengeti_cheetah/mainboard.c Normal file
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#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include "chip.h"
#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_amd_serengeti_cheetah_ops = {
CHIP_NAME("AMD serengeti_cheetah mainboard")
};
#endif

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src/mainboard/amd/serengeti_cheetah/mb_sysconf.h Normal file
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#ifndef MB_SYSCONF_H
#define MB_SYSCONF_H
struct mb_sysconf_t {
unsigned char bus_isa;
unsigned char bus_8132_0;
unsigned char bus_8132_1;
unsigned char bus_8132_2;
unsigned char bus_8111_0;
unsigned char bus_8111_1;
unsigned char bus_8151_0;
unsigned char bus_8151_1;
unsigned apicid_8111;
unsigned apicid_8132_1;
unsigned apicid_8132_2;
unsigned sbdn3;
unsigned sbdn5;
};
#endif

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#include <console/console.h>
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
#if CONFIG_LOGICAL_CPUS==1
#include <cpu/amd/dualcore.h>
#endif
#include <cpu/amd/amdk8_sysconf.h>
#include "mb_sysconf.h"
extern void get_bus_conf(void);
void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "AMD ";
static const char productid[12] = "SERENGETI ";
struct mp_config_table *mc;
unsigned char bus_num;
int i;
struct mb_sysconf_t *m;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
memset(mc, 0, sizeof(*mc));
memcpy(mc->mpc_signature, sig, sizeof(sig));
mc->mpc_length = sizeof(*mc); /* initially just the header */
mc->mpc_spec = 0x04;
mc->mpc_checksum = 0; /* not yet computed */
memcpy(mc->mpc_oem, oem, sizeof(oem));
memcpy(mc->mpc_productid, productid, sizeof(productid));
mc->mpc_oemptr = 0;
mc->mpc_oemsize = 0;
mc->mpc_entry_count = 0; /* No entries yet... */
mc->mpc_lapic = LAPIC_ADDR;
mc->mpe_length = 0;
mc->mpe_checksum = 0;
mc->reserved = 0;
smp_write_processors(mc);
get_bus_conf();
m = sysconf.mb;
/*Bus: Bus ID Type*/
/* define bus and isa numbers */
for(bus_num = 0; bus_num < m->bus_isa; bus_num++) {
smp_write_bus(mc, bus_num, "PCI ");
}
smp_write_bus(mc, m->bus_isa, "ISA ");
/*I/O APICs: APIC ID Version State Address*/
smp_write_ioapic(mc, m->apicid_8111, 0x11, 0xfec00000); //8111
{
device_t dev;
struct resource *res;
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, m->apicid_8132_1, 0x11, res->base);
}
}
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, m->apicid_8132_2, 0x11, res->base);
}
}
}
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_8111, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x1, m->apicid_8111, 0x1);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_8111, 0x2);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x3, m->apicid_8111, 0x3);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x4, m->apicid_8111, 0x4);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x5, m->apicid_8111, 0x5);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x6, m->apicid_8111, 0x6);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x7, m->apicid_8111, 0x7);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x8, m->apicid_8111, 0x8);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x9, m->apicid_8111, 0x9);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xc, m->apicid_8111, 0xc);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xd, m->apicid_8111, 0xd);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xe, m->apicid_8111, 0xe);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xf, m->apicid_8111, 0xf);
//??? What
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13);
// Onboard AMD USB
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0<<2)|3, m->apicid_8111, 0x13);
if(sysconf.pci1234[1] & 0xf) {
// Slot AGP
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151_1, 0x0, m->apicid_8111, 0x11);
}
//Slot 3 PCI 32
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5<<2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16
}
//Slot 4 PCI 32
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4<<2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16
}
//Slot 1 PCI-X 133/100/66
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1<<2)|i, m->apicid_8132_2, (0+i)%4); //
}
//Slot 2 PCI-X 133/100/66
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1<<2)|i, m->apicid_8132_1, (1+i)%4); //25
}
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
printk_debug("Wrote the mp table end at: %p - %p\n",
mc, smp_next_mpe_entry(mc));
return smp_next_mpe_entry(mc);
}
unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr);
return (unsigned long)smp_write_config_table(v);
}

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src/mainboard/amd/serengeti_cheetah/readme_acpi.txt Normal file
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At this time, For acpi support We got
1. support AMK K8 SRAT --- dynamically (LinuxBIOS run-time) (src/northbridge/amd/amdk8/amdk8_acpi.c)
2. support MADT ---- dynamically (LinuxBIOS run-time) (src/northbridge/amd/amdk8/amdk8_acpi.c , src/mainboard/amd/serengeti_cheetah/acpi_tables.c)
3. support DSDT ---- dynamically (Compile time, LinuxBIOS run-time, ACPI run-time) (src/mainboard/amd/serengeti_cheetah/{dx/*, get_bus_conf.c}, src/northbridge/amd/amdk8/get_sblk_pci1234.c)
4. Chipset support: amd8111, amd8132
The developers need to change for different MB
Change dx/dsdt_lb.dsl, according to MB layout
pci1, pci2, pci3, pci4, ...., pci8
if there is HT-IO board, may use pci2.asl.... to create ssdt2.c, and ssdt3,c and ssdt4.c, ....ssdt8.c
Change acpi_tables.c
sbdn: Real SB device Num. for 8111 =3 or 1 depend if 8131 presents. ---- Actually you don't need to change it, it is LinuxBIOS run-time configurable now.
if there is HT-IO board, need to adjust SSDTX_NUM...., and preset pci1234 array. acpi_tables.c will decide to put the SSDT on the RSDT or not according if the HT-IO board is installed
Regarding pci bridge apic and pic
need to modify entries amd8111.asl and amd8131.asl and amd8151.asl.... acording to your MB laybout, it is like that in mptable.c
About other chipsets, need to develop their special asl such as
ck804.asl --- NB ck804
bcm5785.asl or bcm5780.asl ---- Serverworks HT1000/HT2000
use a to create hex file
use c to delele hex file
yhlu
09/18/2005

265
src/mainboard/amd/serengeti_cheetah/resourcemap.c Normal file
View File

@ -0,0 +1,265 @@
/*
* AMD serengeti_cheetah needs a different resource map
*
*/
static void setup_serengeti_cheetah_resource_map(void)
{
static const unsigned int register_values[] = {
/* Careful set limit registers before base registers which contain the enables */
/* DRAM Limit i Registers
* F1:0x44 i = 0
* F1:0x4C i = 1
* F1:0x54 i = 2
* F1:0x5C i = 3
* F1:0x64 i = 4
* F1:0x6C i = 5
* F1:0x74 i = 6
* F1:0x7C i = 7
* [ 2: 0] Destination Node ID
* 000 = Node 0
* 001 = Node 1
* 010 = Node 2
* 011 = Node 3
* 100 = Node 4
* 101 = Node 5
* 110 = Node 6
* 111 = Node 7
* [ 7: 3] Reserved
* [10: 8] Interleave select
* specifies the values of A[14:12] to use with interleave enable.
* [15:11] Reserved
* [31:16] DRAM Limit Address i Bits 39-24
* This field defines the upper address bits of a 40 bit address
* that define the end of the DRAM region.
*/
PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
/* DRAM Base i Registers
* F1:0x40 i = 0
* F1:0x48 i = 1
* F1:0x50 i = 2
* F1:0x58 i = 3
* F1:0x60 i = 4
* F1:0x68 i = 5
* F1:0x70 i = 6
* F1:0x78 i = 7
* [ 0: 0] Read Enable
* 0 = Reads Disabled
* 1 = Reads Enabled
* [ 1: 1] Write Enable
* 0 = Writes Disabled
* 1 = Writes Enabled
* [ 7: 2] Reserved
* [10: 8] Interleave Enable
* 000 = No interleave
* 001 = Interleave on A[12] (2 nodes)
* 010 = reserved
* 011 = Interleave on A[12] and A[14] (4 nodes)
* 100 = reserved
* 101 = reserved
* 110 = reserved
* 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
* [15:11] Reserved
* [13:16] DRAM Base Address i Bits 39-24
* This field defines the upper address bits of a 40-bit address
* that define the start of the DRAM region.
*/
PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
/* Memory-Mapped I/O Limit i Registers
* F1:0x84 i = 0
* F1:0x8C i = 1
* F1:0x94 i = 2
* F1:0x9C i = 3
* F1:0xA4 i = 4
* F1:0xAC i = 5
* F1:0xB4 i = 6
* F1:0xBC i = 7
* [ 2: 0] Destination Node ID
* 000 = Node 0
* 001 = Node 1
* 010 = Node 2
* 011 = Node 3
* 100 = Node 4
* 101 = Node 5
* 110 = Node 6
* 111 = Node 7
* [ 3: 3] Reserved
* [ 5: 4] Destination Link ID
* 00 = Link 0
* 01 = Link 1
* 10 = Link 2
* 11 = Reserved
* [ 6: 6] Reserved
* [ 7: 7] Non-Posted
* 0 = CPU writes may be posted
* 1 = CPU writes must be non-posted
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
* This field defines the upp adddress bits of a 40-bit address that
* defines the end of a memory-mapped I/O region n
*/
PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
/* Memory-Mapped I/O Base i Registers
* F1:0x80 i = 0
* F1:0x88 i = 1
* F1:0x90 i = 2
* F1:0x98 i = 3
* F1:0xA0 i = 4
* F1:0xA8 i = 5
* F1:0xB0 i = 6
* F1:0xB8 i = 7
* [ 0: 0] Read Enable
* 0 = Reads disabled
* 1 = Reads Enabled
* [ 1: 1] Write Enable
* 0 = Writes disabled
* 1 = Writes Enabled
* [ 2: 2] Cpu Disable
* 0 = Cpu can use this I/O range
* 1 = Cpu requests do not use this I/O range
* [ 3: 3] Lock
* 0 = base/limit registers i are read/write
* 1 = base/limit registers i are read-only
* [ 7: 4] Reserved
* [31: 8] Memory-Mapped I/O Base Address i (39-16)
* This field defines the upper address bits of a 40bit address
* that defines the start of memory-mapped I/O region i
*/
PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
/* PCI I/O Limit i Registers
* F1:0xC4 i = 0
* F1:0xCC i = 1
* F1:0xD4 i = 2
* F1:0xDC i = 3
* [ 2: 0] Destination Node ID
* 000 = Node 0
* 001 = Node 1
* 010 = Node 2
* 011 = Node 3
* 100 = Node 4
* 101 = Node 5
* 110 = Node 6
* 111 = Node 7
* [ 3: 3] Reserved
* [ 5: 4] Destination Link ID
* 00 = Link 0
* 01 = Link 1
* 10 = Link 2
* 11 = reserved
* [11: 6] Reserved
* [24:12] PCI I/O Limit Address i
* This field defines the end of PCI I/O region n
* [31:25] Reserved
*/
PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000,
PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
/* PCI I/O Base i Registers
* F1:0xC0 i = 0
* F1:0xC8 i = 1
* F1:0xD0 i = 2
* F1:0xD8 i = 3
* [ 0: 0] Read Enable
* 0 = Reads Disabled
* 1 = Reads Enabled
* [ 1: 1] Write Enable
* 0 = Writes Disabled
* 1 = Writes Enabled
* [ 3: 2] Reserved
* [ 4: 4] VGA Enable
* 0 = VGA matches Disabled
* 1 = matches all address < 64K and where A[9:0] is in the
* range 3B0-3BB or 3C0-3DF independen of the base & limit registers
* [ 5: 5] ISA Enable
* 0 = ISA matches Disabled
* 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
* from matching agains this base/limit pair
* [11: 6] Reserved
* [24:12] PCI I/O Base i
* This field defines the start of PCI I/O region n
* [31:25] Reserved
*/
PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003,
PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
/* Config Base and Limit i Registers
* F1:0xE0 i = 0
* F1:0xE4 i = 1
* F1:0xE8 i = 2
* F1:0xEC i = 3
* [ 0: 0] Read Enable
* 0 = Reads Disabled
* 1 = Reads Enabled
* [ 1: 1] Write Enable
* 0 = Writes Disabled
* 1 = Writes Enabled
* [ 2: 2] Device Number Compare Enable
* 0 = The ranges are based on bus number
* 1 = The ranges are ranges of devices on bus 0
* [ 3: 3] Reserved
* [ 6: 4] Destination Node
* 000 = Node 0
* 001 = Node 1
* 010 = Node 2
* 011 = Node 3
* 100 = Node 4
* 101 = Node 5
* 110 = Node 6
* 111 = Node 7
* [ 7: 7] Reserved
* [ 9: 8] Destination Link
* 00 = Link 0
* 01 = Link 1
* 10 = Link 2
* 11 - Reserved
* [15:10] Reserved
* [23:16] Bus Number Base i
* This field defines the lowest bus number in configuration region i
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration regin i
*/
PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0
PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x08070013, // AMD 8151 on link0 of CPU 1
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
};
int max;
max = sizeof(register_values)/sizeof(register_values[0]);
setup_resource_map(register_values, max);
}

8
src/mainboard/amd/serengeti_leopard/Config.lb
View File

@ -56,14 +56,14 @@ end
#if HAVE_ACPI_TABLES
# object acpi_tables.o
# object fadt.o
# if K8_SB_HT_CHAIN_ON_BUS0
# if SB_HT_CHAIN_ON_BUS0
# object dsdt_bus0.o
# else
# object dsdt.o
# end
# object ssdt.o
# if ACPI_SSDTX_NUM
# if K8_SB_HT_CHAIN_ON_BUS0
# if SB_HT_CHAIN_ON_BUS0
# object ssdt2_bus0.o
# else
# object ssdt2.o
@ -74,7 +74,7 @@ end
if HAVE_ACPI_TABLES
object acpi_tables.o
object fadt.o
if K8_SB_HT_CHAIN_ON_BUS0
if SB_HT_CHAIN_ON_BUS0
makerule dsdt.c
depends "$(MAINBOARD)/dx_bus0/dsdt_lb.dsl"
action "/usr/sbin/iasl -tc $(MAINBOARD)/dx_bus0/dsdt_lb.dsl"
@ -98,7 +98,7 @@ if HAVE_ACPI_TABLES
object ./ssdt.o
if ACPI_SSDTX_NUM
if K8_SB_HT_CHAIN_ON_BUS0
if SB_HT_CHAIN_ON_BUS0
makerule ssdt2.c
depends "$(MAINBOARD)/dx/pci2.asl"
action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci2.asl"

18
src/mainboard/amd/serengeti_leopard/Options.lb
View File

@ -54,13 +54,13 @@ uses OBJCOPY
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses K8_HW_MEM_HOLE_SIZEK
uses K8_HW_MEM_HOLE_SIZE_AUTO_INC
uses HW_MEM_HOLE_SIZEK
uses HW_MEM_HOLE_SIZE_AUTO_INC
uses K8_HT_FREQ_1G_SUPPORT
uses HT_CHAIN_UNITID_BASE
uses HT_CHAIN_END_UNITID_BASE
uses K8_SB_HT_CHAIN_ON_BUS0
uses SB_HT_CHAIN_ON_BUS0
uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
uses USE_DCACHE_RAM
@ -152,14 +152,14 @@ default CONFIG_CHIP_NAME=1
#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
#2G
default K8_HW_MEM_HOLE_SIZEK=0x200000
default HW_MEM_HOLE_SIZEK=0x200000
#1G
#default K8_HW_MEM_HOLE_SIZEK=0x100000
#default HW_MEM_HOLE_SIZEK=0x100000
#512M
#default K8_HW_MEM_HOLE_SIZEK=0x80000
#default HW_MEM_HOLE_SIZEK=0x80000
#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
#default K8_HW_MEM_HOLE_SIZE_AUTO_INC=1
#default HW_MEM_HOLE_SIZE_AUTO_INC=1
#Opteron K8 1G HT Support
default K8_HT_FREQ_1G_SUPPORT=1
@ -175,7 +175,7 @@ default HT_CHAIN_UNITID_BASE=0x4
default HT_CHAIN_END_UNITID_BASE=0x1
#make the SB HT chain on bus 0
default K8_SB_HT_CHAIN_ON_BUS0=1
default SB_HT_CHAIN_ON_BUS0=1
#allow capable device use that above 4G
#default CONFIG_PCI_64BIT_PREF_MEM=1
@ -186,7 +186,7 @@ default K8_SB_HT_CHAIN_ON_BUS0=1
default USE_DCACHE_RAM=1
default DCACHE_RAM_BASE=0xcc000
default DCACHE_RAM_SIZE=0x4000
default CONFIG_USE_INIT=1
default CONFIG_USE_INIT=0
##
## Build code to setup a generic IOAPIC

4
src/mainboard/arima/hdama/auto.c
View File

@ -12,7 +12,6 @@
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
@ -22,7 +21,6 @@
#include "superio/NSC/pc87360/pc87360_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#include "cpu/amd/dualcore/dualcore.c"
#define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
@ -141,7 +139,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "sdram/generic_sdram.c"
#include "cpu/amd/dualcore/dualcore.c"
#include "northbridge/amd/amdk8/resourcemap.c"
#include "debug.c"

8
src/mainboard/broadcom/blast/Options.lb
View File

@ -53,10 +53,10 @@ uses OBJCOPY
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses K8_HW_MEM_HOLE_SIZEK
uses HW_MEM_HOLE_SIZEK
uses HT_CHAIN_UNITID_BASE
uses HT_CHAIN_END_UNITID_BASE
uses K8_SB_HT_CHAIN_ON_BUS0
uses SB_HT_CHAIN_ON_BUS0
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
@ -128,7 +128,7 @@ default CONFIG_LOGICAL_CPUS=1
default CONFIG_CHIP_NAME=1
#1G memory hole
default K8_HW_MEM_HOLE_SIZEK=0x100000
default HW_MEM_HOLE_SIZEK=0x100000
#VGA Console
#default CONFIG_CONSOLE_VGA=1
@ -141,7 +141,7 @@ default HT_CHAIN_UNITID_BASE=0x6
default HT_CHAIN_END_UNITID_BASE=0x1
#make the SB HT chain on bus 0
default K8_SB_HT_CHAIN_ON_BUS0=1
default SB_HT_CHAIN_ON_BUS0=1
##
## enable CACHE_AS_RAM specifics

4
src/mainboard/ibm/e325/auto.c
View File

@ -13,7 +13,6 @@
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
@ -25,7 +24,6 @@
#include "superio/NSC/pc87366/pc87366_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#include "cpu/amd/dualcore/dualcore.c"
#define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
@ -125,8 +123,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "sdram/generic_sdram.c"
#include "mainboard/ibm/e325/resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#define FIRST_CPU 1
#define SECOND_CPU 1

4
src/mainboard/ibm/e326/auto.c
View File

@ -13,7 +13,6 @@
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
@ -25,7 +24,6 @@
#include "superio/NSC/pc87366/pc87366_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#include "cpu/amd/dualcore/dualcore.c"
#define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
@ -125,8 +123,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "sdram/generic_sdram.c"
#include "mainboard/ibm/e326/resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#define FIRST_CPU 1
#define SECOND_CPU 1

4
src/mainboard/newisys/khepri/auto.c
View File

@ -18,12 +18,10 @@
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include <cpu/amd/model_fxx_rev.h>
#include "superio/NSC/pc87360/pc87360_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#include "cpu/amd/dualcore/dualcore.c"
#define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
@ -80,11 +78,13 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "sdram/generic_sdram.c"
/* newisys khepri does not want the default */
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#define NODE_RAM(x) \
.node_id = 0+x, \

8
src/mainboard/sunw/ultra40/Options.lb
View File

@ -52,7 +52,7 @@ uses CONFIG_GDB_STUB
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses K8_HW_MEM_HOLE_SIZEK
uses HW_MEM_HOLE_SIZEK
uses K8_HT_FREQ_1G_SUPPORT
uses USE_DCACHE_RAM
@ -66,7 +66,7 @@ uses LIFT_BSP_APIC_ID
uses HT_CHAIN_UNITID_BASE
uses HT_CHAIN_END_UNITID_BASE
uses K8_SB_HT_CHAIN_ON_BUS0
uses SB_HT_CHAIN_ON_BUS0
uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
## ROM_SIZE is the size of boot ROM that this board will use.
@ -134,7 +134,7 @@ default CONFIG_LOGICAL_CPUS=1
#default CONFIG_CHIP_NAME=1
#1G memory hole
default K8_HW_MEM_HOLE_SIZEK=0x100000
default HW_MEM_HOLE_SIZEK=0x100000
#Opteron K8 1G HT Support
default K8_HT_FREQ_1G_SUPPORT=1
@ -146,7 +146,7 @@ default HT_CHAIN_UNITID_BASE=0x0
#default HT_CHAIN_END_UNITID_BASE=0x0
#make the SB HT chain on bus 0, default is not (0)
default K8_SB_HT_CHAIN_ON_BUS0=2
default SB_HT_CHAIN_ON_BUS0=2
##only offset for SB chain?, default is yes(1)
default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0

6
src/mainboard/tyan/s2850/Options.lb
View File

@ -52,7 +52,7 @@ uses OBJCOPY
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses K8_HW_MEM_HOLE_SIZEK
uses HW_MEM_HOLE_SIZEK
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
@ -122,7 +122,7 @@ default CONFIG_LOGICAL_CPUS=1
default CONFIG_CHIP_NAME=1
#1G memory hole
default K8_HW_MEM_HOLE_SIZEK=0x100000
default HW_MEM_HOLE_SIZEK=0x100000
#VGA Console
default CONFIG_CONSOLE_VGA=1
@ -135,7 +135,7 @@ default CONFIG_PCI_ROM_RUN=1
default USE_DCACHE_RAM=1
default DCACHE_RAM_BASE=0xcf000
default DCACHE_RAM_SIZE=0x1000
default CONFIG_USE_INIT=1
default CONFIG_USE_INIT=0
##
## Build code to setup a generic IOAPIC

6
src/mainboard/tyan/s2875/Options.lb
View File

@ -52,7 +52,7 @@ uses OBJCOPY
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses K8_HW_MEM_HOLE_SIZEK
uses HW_MEM_HOLE_SIZEK
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
@ -123,7 +123,7 @@ default CONFIG_LOGICAL_CPUS=1
default CONFIG_CHIP_NAME=1
#1G memory hole
default K8_HW_MEM_HOLE_SIZEK=0x100000
default HW_MEM_HOLE_SIZEK=0x100000
#VGA Console
default CONFIG_CONSOLE_VGA=1
@ -136,7 +136,7 @@ default CONFIG_PCI_ROM_RUN=1
default USE_DCACHE_RAM=1
default DCACHE_RAM_BASE=0xcf000
default DCACHE_RAM_SIZE=0x1000
default CONFIG_USE_INIT=1
default CONFIG_USE_INIT=0
##
## Build code to setup a generic IOAPIC

6
src/mainboard/tyan/s2880/Options.lb
View File

@ -52,7 +52,7 @@ uses OBJCOPY
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses K8_HW_MEM_HOLE_SIZEK
uses HW_MEM_HOLE_SIZEK
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
@ -122,7 +122,7 @@ default CONFIG_LOGICAL_CPUS=0
default CONFIG_CHIP_NAME=1
#1G memory hole
default K8_HW_MEM_HOLE_SIZEK=0x100000
default HW_MEM_HOLE_SIZEK=0x100000
#VGA Console
default CONFIG_CONSOLE_VGA=1
@ -135,7 +135,7 @@ default CONFIG_PCI_ROM_RUN=1
default USE_DCACHE_RAM=1
default DCACHE_RAM_BASE=0xcf000
default DCACHE_RAM_SIZE=0x1000
default CONFIG_USE_INIT=1
default CONFIG_USE_INIT=0
##
## Build code to setup a generic IOAPIC

6
src/mainboard/tyan/s2881/Options.lb
View File

@ -52,7 +52,7 @@ uses OBJCOPY
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses K8_HW_MEM_HOLE_SIZEK
uses HW_MEM_HOLE_SIZEK
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
@ -122,7 +122,7 @@ default CONFIG_LOGICAL_CPUS=1
default CONFIG_CHIP_NAME=1
#1G memory hole
default K8_HW_MEM_HOLE_SIZEK=0x100000
default HW_MEM_HOLE_SIZEK=0x100000
#VGA Console
#default CONFIG_CONSOLE_VGA=1
@ -135,7 +135,7 @@ default K8_HW_MEM_HOLE_SIZEK=0x100000
default USE_DCACHE_RAM=1
default DCACHE_RAM_BASE=0xcf000
default DCACHE_RAM_SIZE=0x1000
default CONFIG_USE_INIT=1
default CONFIG_USE_INIT=0
##
## Build code to setup a generic IOAPIC

6
src/mainboard/tyan/s2882/Options.lb
View File

@ -52,7 +52,7 @@ uses OBJCOPY
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses K8_HW_MEM_HOLE_SIZEK
uses HW_MEM_HOLE_SIZEK
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
@ -122,7 +122,7 @@ default CONFIG_LOGICAL_CPUS=1
default CONFIG_CHIP_NAME=1
#1G memory hole
default K8_HW_MEM_HOLE_SIZEK=0x100000
default HW_MEM_HOLE_SIZEK=0x100000
#VGA Console
default CONFIG_CONSOLE_VGA=1
@ -135,7 +135,7 @@ default CONFIG_PCI_ROM_RUN=1
default USE_DCACHE_RAM=1
default DCACHE_RAM_BASE=0xcf000
default DCACHE_RAM_SIZE=0x1000
default CONFIG_USE_INIT=1
default CONFIG_USE_INIT=0
##
## Build code to setup a generic IOAPIC

6
src/mainboard/tyan/s2885/Options.lb
View File

@ -52,7 +52,7 @@ uses OBJCOPY
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses K8_HW_MEM_HOLE_SIZEK
uses HW_MEM_HOLE_SIZEK
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
@ -126,7 +126,7 @@ default CONFIG_LOGICAL_CPUS=1
default CONFIG_CHIP_NAME=1
#1G memory hole
default K8_HW_MEM_HOLE_SIZEK=0x100000
default HW_MEM_HOLE_SIZEK=0x100000
#VGA Console
default CONFIG_CONSOLE_VGA=1
@ -139,7 +139,7 @@ default CONFIG_PCI_ROM_RUN=1
default USE_DCACHE_RAM=1
default DCACHE_RAM_BASE=0xcf000
default DCACHE_RAM_SIZE=0x1000
default CONFIG_USE_INIT=1
default CONFIG_USE_INIT=0
default ENABLE_APIC_EXT_ID=1
default APIC_ID_OFFSET=0x10

8
src/mainboard/tyan/s2891/Options.lb
View File

@ -53,7 +53,7 @@ uses CONFIG_GDB_STUB
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses K8_HW_MEM_HOLE_SIZEK
uses HW_MEM_HOLE_SIZEK
uses K8_HT_FREQ_1G_SUPPORT
uses USE_DCACHE_RAM
@ -69,7 +69,7 @@ uses CONFIG_PCI_64BIT_PREF_MEM
uses HT_CHAIN_UNITID_BASE
uses HT_CHAIN_END_UNITID_BASE
uses K8_SB_HT_CHAIN_ON_BUS0
uses SB_HT_CHAIN_ON_BUS0
uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
uses CONFIG_LB_MEM_TOPK
@ -137,7 +137,7 @@ default CONFIG_MAX_PHYSICAL_CPUS=2
default CONFIG_LOGICAL_CPUS=1
#1G memory hole
default K8_HW_MEM_HOLE_SIZEK=0x100000
default HW_MEM_HOLE_SIZEK=0x100000
#Opteron K8 1G HT Support
default K8_HT_FREQ_1G_SUPPORT=1
@ -149,7 +149,7 @@ default HT_CHAIN_UNITID_BASE=0x0
#default HT_CHAIN_END_UNITID_BASE=0x0
#make the SB HT chain on bus 0, default is not (0)
default K8_SB_HT_CHAIN_ON_BUS0=2
default SB_HT_CHAIN_ON_BUS0=2
##only offset for SB chain?, default is yes(1)
default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0

8
src/mainboard/tyan/s2892/Options.lb
View File

@ -53,7 +53,7 @@ uses CONFIG_GDB_STUB
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses K8_HW_MEM_HOLE_SIZEK
uses HW_MEM_HOLE_SIZEK
uses K8_HT_FREQ_1G_SUPPORT
uses USE_DCACHE_RAM
@ -63,7 +63,7 @@ uses CONFIG_USE_INIT
uses HT_CHAIN_UNITID_BASE
uses HT_CHAIN_END_UNITID_BASE
uses K8_SB_HT_CHAIN_ON_BUS0
uses SB_HT_CHAIN_ON_BUS0
uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
## ROM_SIZE is the size of boot ROM that this board will use.
@ -129,7 +129,7 @@ default CONFIG_MAX_PHYSICAL_CPUS=2
default CONFIG_LOGICAL_CPUS=1
#1G memory hole
default K8_HW_MEM_HOLE_SIZEK=0x100000
default HW_MEM_HOLE_SIZEK=0x100000
#Opteron K8 1G HT Support
default K8_HT_FREQ_1G_SUPPORT=1
@ -141,7 +141,7 @@ default HT_CHAIN_UNITID_BASE=0x0
#default HT_CHAIN_END_UNITID_BASE=0x0
#make the SB HT chain on bus 0, default is not (0)
default K8_SB_HT_CHAIN_ON_BUS0=2
default SB_HT_CHAIN_ON_BUS0=2
##only offset for SB chain?, default is yes(1)
default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0

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