AMD Rev F support

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-04 20:46:15 +00:00
parent 2e3757d11c
commit d4b278c02c
130 changed files with 11668 additions and 657 deletions
--- a/src/config/Config.lb
+++ b/src/config/Config.lb
@@ -1,6 +1,7 @@
 ## This is Architecture independant part of the makefile

 uses HAVE_OPTION_TABLE
+uses CONFIG_AP_CODE_IN_CAR

 makedefine CPP:= $(CC) -x assembler-with-cpp -DASSEMBLY -E
 makedefine LIBGCC_FILE_NAME := $(shell $(CC) -print-libgcc-file-name)
@@ -31,6 +32,12 @@ makerule linuxbios.strip
 	action	"$(OBJCOPY) -O binary linuxbios linuxbios.strip"
 end

+makerule linuxbios.a
+        depends "$(OBJECTS)"
+        action  "rm -f linuxbios.a"
+        action  "ar cr linuxbios.a $(OBJECTS)"
+end
+
 makerule linuxbios_ram.o
 	depends	"$(DRIVER) linuxbios.a $(LIBGCC_FILE_NAME)" 
 	action	"$(CC) -nostdlib -r -o $@ c_start.o $(DRIVER) linuxbios.a $(LIBGCC_FILE_NAME)"
@@ -63,16 +70,59 @@ makerule linuxbios_ram.rom
 	action	"cp $(LINUXBIOS_RAM-1) linuxbios_ram.rom"
 end

-makerule linuxbios   
-	depends	"crt0.o $(INIT-OBJECTS) linuxbios_ram.rom ldscript.ld"
-	action	"$(CC) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld crt0.o $(INIT-OBJECTS)"
-	action	"$(CROSS_COMPILE)nm -n linuxbios | sort > linuxbios.map"
+makedefine LINUXBIOS_APC:=
+
+if CONFIG_AP_CODE_IN_CAR
+	#for ap code in cache
+
+	makerule linuxbios_apc.a
+		depends "apc_auto.o"
+		action  "rm -f linuxbios_apc.a"
+		action  "ar cr linuxbios_apc.a apc_auto.o"
+	end
+
+	makerule linuxbios_apc.o
+		depends "linuxbios_apc.a c_start.o $(LIBGCC_FILE_NAME)"
+        action  "$(CC) -nostdlib -r -o $@ c_start.o linuxbios_apc.a $(LIBGCC_FILE_NAME)"
+	end
+
+	makerule linuxbios_apc
+		depends "linuxbios_apc.o $(TOP)/src/config/linuxbios_apc.ld ldoptions"
+		action  "$(CC) -nostdlib -nostartfiles -static -o $@ -T $(TOP)/src/config/linuxbios_apc.ld linuxbios_apc.o"
+		action  "$(CROSS_COMPILE)nm -n linuxbios_apc | sort > linuxbios_apc.map"
+	end
+
+	##
+	## By default compress the part of linuxbios that runs from cache as ram
+	##
+	makedefine LINUXBIOS_APC-$(CONFIG_COMPRESS):=linuxbios_apc.nrv2b
+	makedefine LINUXBIOS_APC-$(CONFIG_UNCOMPRESSED):=linuxbios_apc.bin
+
+	makerule linuxbios_apc.bin
+		depends "linuxbios_apc"
+		action  "$(OBJCOPY) -O binary $< $@"
+	end
+
+	makerule linuxbios_apc.nrv2b
+        depends "linuxbios_apc.bin nrv2b"
+        action  "./nrv2b e $< $@"
+	end
+
+	makerule linuxbios_apc.rom
+		depends "$(LINUXBIOS_APC-1)"
+		action  "cp $(LINUXBIOS_APC-1) linuxbios_apc.rom"
+	end
+
+	makedefine LINUXBIOS_APC:=linuxbios_apc.rom
+
 end

-makerule linuxbios.a   
-	depends	"$(OBJECTS)" 
-	action	"rm -f linuxbios.a"
-	action	"ar cr linuxbios.a $(OBJECTS)"
+makedefine LINUXBIOS_RAM_ROM:=linuxbios_ram.rom
+
+makerule linuxbios   
+	depends	"crt0.o $(INIT-OBJECTS) $(LINUXBIOS_APC) $(LINUXBIOS_RAM_ROM) ldscript.ld"
+	action	"$(CC) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld crt0.o $(INIT-OBJECTS)"
+	action	"$(CROSS_COMPILE)nm -n linuxbios | sort > linuxbios.map"
 end

 #makerule crt0.S   
@@ -159,7 +209,7 @@ makerule clean
 	action	"rm -f ldscript.ld"
 	action	"rm -f a.out *.s *.l *.o *.E *.inc"
 	action	"rm -f TAGS tags romcc*"
-	action	"rm -f docipl buildrom* chips.c *chip.c linuxbios_ram* linuxbios_pay*"
+	action	"rm -f docipl buildrom* chips.c *chip.c linuxbios_apc* linuxbios_ram* linuxbios_pay*"
 	action	"rm -f build_opt_tbl* nrv2b* option_table.c crt0.S"
 end

--- a/src/config/Options.lb
+++ b/src/config/Options.lb
@@ -178,18 +178,36 @@ define HAVE_FALLBACK_BOOT
 	export always
 	comment "Set if fallback booting required"
 end
+define HAVE_FAILOVER_BOOT
+	format "%d"
+	default 0
+	export always
+	comment "Set if failover booting required"
+end
 define USE_FALLBACK_IMAGE
 	format "%d"
 	default 0
 	export used
 	comment "Set to build a fallback image"
 end
+define USE_FAILOVER_IMAGE
+        format "%d"
+        default 0
+        export used
+        comment "Set to build a failover image"
+end
 define FALLBACK_SIZE
 	default 65536
 	format "0x%x"
 	export used
 	comment "Default fallback image size"
 end
+define FAILOVER_SIZE
+        default 0
+        format "0x%x"
+        export used
+        comment "Default failover image size"
+end
 define ROM_SIZE
 	default none
 	format "0x%x"
@@ -274,9 +292,9 @@ define USE_DCACHE_RAM
 	comment "Use data cache as temporary RAM if possible"
 end
 define DCACHE_RAM_BASE
-	default none
+	default 0xc0000
 	format "0x%x"
-	export used
+	export always
 	comment "Base address of data cache when using it for temporary RAM"
 end
 define DCACHE_RAM_SIZE
@@ -291,6 +309,21 @@ define DCACHE_RAM_GLOBAL_VAR_SIZE
 	export always
 	comment "Size of region that for global variable of cache as ram stage"
 end
+define CONFIG_AP_CODE_IN_CAR
+        default 0
+        export always
+        comment "will copy linuxbios_apc to AP cache ane execute in AP"
+end
+define MEM_TRAIN_SEQ
+        default 0
+        export always
+        comment "0: three for in bsp, 1: on every core0, 2: one for on bsp"
+end
+define WAIT_BEFORE_CPUS_INIT
+        default 0
+        export always
+        comment "execute cpus_ready_for_init if it is set to 1"
+end
 define XIP_ROM_BASE
 	default 0
 	format "0x%x"
@@ -853,7 +886,7 @@ end
 define HT_CHAIN_UNITID_BASE
 	default 1
 	export always
-	comment "first hypertransport device's unitid base. if southbridge ht chain only has one ht device, it could be 0"
+	comment "this will be first hypertransport device's unitid base, if sb ht chain only has one ht device, it could be 0"
 end

 define HT_CHAIN_END_UNITID_BASE
@@ -868,30 +901,67 @@ define SB_HT_CHAIN_UNITID_OFFSET_ONLY
        comment "this will decided if only offset SB hypertransport chain"
 end

-define K8_SB_HT_CHAIN_ON_BUS0
+define SB_HT_CHAIN_ON_BUS0
        default 0 
        export always
-        comment "this will make SB hypertransport chain sit on bus 0, if it is 2 will put other chain on 0x40, 0x80, 0xc0"
+        comment "this will make SB hypertransport chain sit on bus 0, if it is 1, will put sb ht chain on bus 0, if it is 2 will put other chain on 0x40, 0x80, 0xc0"
 end

-define K8_HW_MEM_HOLE_SIZEK
+define HW_MEM_HOLE_SIZEK
        default 0
        export always
        comment "Opteron E0 later memory hole size in K, 0 mean disable"
 end

-define K8_HW_MEM_HOLE_SIZE_AUTO_INC
+define HW_MEM_HOLE_SIZE_AUTO_INC
        default 0
        export always
        comment "Opteron E0 later memory hole size auto increase to avoid hole startk equal to basek"
 end

 define K8_HT_FREQ_1G_SUPPORT
-	default 0
+	default 0 
 	export always
 	comment "Optern E0 later could support 1G HT, but still depends MB design"
 end

+define K8_REV_F_SUPPORT
+        default 0
+        export always
+        comment "Opteron Rev F (DDR2) support"
+end
+
+define CBB
+	default 0
+	export always
+	comment "Opteron cpu bus num base"
+end
+
+define CDB
+	default 0x18
+	export always
+	comment "Opteron cpu device num base"
+end
+
+define DIMM_SUPPORT
+        default 0x0108
+	format "0x%x"
+        export always
+        comment "DIMM support: bit 0 - sdram, bit 1: ddr1, bit 2: ddr2, bit 3: ddr3, bit 4: fbdimm, bit 8: reg"
+end
+
+define CPU_SOCKET_TYPE
+	default 0x10
+	export always
+	comment "cpu socket type, 0x10 mean Socket F, 0x11 mean socket M2, 0x20, Soxket G, and 0x21 mean socket M3"
+end
+
+define CPU_ADDR_BITS
+	default 36
+	export always
+	comment "CPU hardware address lines num, for AMD K8 could be 40, and GH could be 48"
+end
+
 define CONFIG_PCI_ROM_RUN
 	default 0
 	export always
--- a/src/config/linuxbios_ram.ld
+++ b/src/config/linuxbios_ram.ld
@@ -109,7 +109,7 @@ SECTIONS
 	_ram_seg = _text; 
 	_eram_seg = _eheap;

-	_bogus = ASSERT( ((_eram_seg>>10)<CONFIG_LB_MEM_TOPK) , "please increase CONFIG_LB_MEM_TOPK");
+	_bogus = ASSERT( ( (_eram_seg>>10) < (CONFIG_LB_MEM_TOPK)) , "please increase CONFIG_LB_MEM_TOPK");

        _bogus = ASSERT( !((CONFIG_CONSOLE_VGA || CONFIG_PCI_ROM_RUN) && ((_ram_seg<0xa0000) && (_eram_seg>0xa0000))) , "please increase CONFIG_LB_MEM_TOPK and if still fail, try to set _RAMBASE more than 1M");