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mb/google/brox/var/lotso: Tune I2C frequency for 400 kHz

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Before:
I2C0 - 401kHz
I2C4 - 405kHz

After:
I2C0 - 392kHz
I2C4 - 395kHz

HW: Change R8409/R8411 to 33ohm.

BUG=b:349743464,b:349735055
TEST=emerge-brox sys-boot/coreboot
     Test pass by EE

Change-Id: I985837b1b80e973f148529b446905580c0f95e98
Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83290
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
This commit is contained in:
Jing Tong 2024-07-01 13:42:33 +08:00 committed by Felix Held
parent cae81a5674
commit d5de10f02e
1 changed files with 16 additions and 0 deletions
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16
src/mainboard/google/brox/variants/lotso/overridetree.cb
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@ -48,6 +48,22 @@ chip soc/intel/alderlake
register "tcss_ports[0]" = "TCSS_PORT_EMPTY" # Disable TCP0
register "tcss_ports[2]" = "TCSS_PORT_EMPTY" # Disable TCP2
register "common_soc_config" = "{
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 650,
.fall_time_ns = 350,
.data_hold_time_ns = 400,
},
.i2c[4] = {
.early_init = 1,
.speed = I2C_SPEED_FAST,
.rise_time_ns = 600,
.fall_time_ns = 110,
.data_hold_time_ns = 100,
},
}"
register "serial_io_gspi_mode" = "{
[PchSerialIoIndexGSPI0] = PchSerialIoPci,
[PchSerialIoIndexGSPI1] = PchSerialIoPci,