mb/siemens/mc_ehl1: Clean up PCIe root port settings in devicetree
PCIe root ports #5 (00:1c.4) and #6 (00:1c.5) are not used on this mainboard and are not routed either, so remove them from the devicetree completely. PCIe root port #7 (00:1c.6) is connected and used. Add the missing settings for L1 substates and latency reporting to disable these features for this port as well. Change-Id: I06f59f0369ffcd958b5fe12bb3c646d37103811f Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58568 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
committed by
Patrick Georgi
parent
fec936659c
commit
d6798e96fc
@@ -51,8 +51,6 @@ chip soc/intel/elkhartlake
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register "PcieRpEnable[1]" = "1"
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register "PcieRpEnable[2]" = "1"
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register "PcieRpEnable[3]" = "1"
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register "PcieRpEnable[4]" = "1"
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register "PcieRpEnable[5]" = "1"
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register "PcieRpEnable[6]" = "1"
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register "PcieClkSrcUsage[0]" = "0x00"
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@@ -74,16 +72,14 @@ chip soc/intel/elkhartlake
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register "PcieRpL1Substates[1]" = "L1_SS_DISABLED"
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register "PcieRpL1Substates[2]" = "L1_SS_DISABLED"
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register "PcieRpL1Substates[3]" = "L1_SS_DISABLED"
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register "PcieRpL1Substates[4]" = "L1_SS_DISABLED"
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register "PcieRpL1Substates[5]" = "L1_SS_DISABLED"
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register "PcieRpL1Substates[6]" = "L1_SS_DISABLED"
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# Disable LTR for all PCIe root ports
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register "PcieRpLtrDisable[0]" = "true"
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register "PcieRpLtrDisable[1]" = "true"
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register "PcieRpLtrDisable[2]" = "true"
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register "PcieRpLtrDisable[3]" = "true"
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register "PcieRpLtrDisable[4]" = "true"
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register "PcieRpLtrDisable[5]" = "true"
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register "PcieRpLtrDisable[6]" = "true"
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# Storage (SATA/SDCARD/EMMC) related UPDs
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register "SataSalpSupport" = "0"
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@@ -157,8 +153,6 @@ chip soc/intel/elkhartlake
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device pci 1c.1 on end # RP2 (pcie0 single VC)
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device pci 1c.2 on end # RP3 (pcie0 single VC)
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device pci 1c.3 on end # RP4 (pcie0 single VC)
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device pci 1c.4 on end # RP5 (pcie1 multi VC)
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device pci 1c.5 on end # RP6 (pcie2 multi VC)
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device pci 1c.6 on end # RP7 (pcie3 multi VC)
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device pci 1e.0 on end # UART0
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