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mb/siemens/mc_ehl1: Clean up PCIe root port settings in devicetree

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PCIe root ports #5 (00:1c.4) and #6 (00:1c.5) are not used on this
mainboard and are not routed either, so remove them from the devicetree
completely. PCIe root port #7 (00:1c.6) is connected and used. Add the
missing settings for L1 substates and latency reporting to disable these
features for this port as well.

Change-Id: I06f59f0369ffcd958b5fe12bb3c646d37103811f
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58568
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Werner Zeh
2021-10-22 10:59:41 +02:00
committed by Patrick Georgi
parent fec936659c
commit d6798e96fc
1 changed files with 2 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
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@@ -51,8 +51,6 @@ chip soc/intel/elkhartlake
register "PcieRpEnable[1]" = "1" register "PcieRpEnable[1]" = "1"
register "PcieRpEnable[2]" = "1" register "PcieRpEnable[2]" = "1"
register "PcieRpEnable[3]" = "1" register "PcieRpEnable[3]" = "1"
register "PcieRpEnable[4]" = "1"
register "PcieRpEnable[5]" = "1"
register "PcieRpEnable[6]" = "1" register "PcieRpEnable[6]" = "1"
register "PcieClkSrcUsage[0]" = "0x00" register "PcieClkSrcUsage[0]" = "0x00"
@@ -74,16 +72,14 @@ chip soc/intel/elkhartlake
register "PcieRpL1Substates[1]" = "L1_SS_DISABLED" register "PcieRpL1Substates[1]" = "L1_SS_DISABLED"
register "PcieRpL1Substates[2]" = "L1_SS_DISABLED" register "PcieRpL1Substates[2]" = "L1_SS_DISABLED"
register "PcieRpL1Substates[3]" = "L1_SS_DISABLED" register "PcieRpL1Substates[3]" = "L1_SS_DISABLED"
register "PcieRpL1Substates[4]" = "L1_SS_DISABLED" register "PcieRpL1Substates[6]" = "L1_SS_DISABLED"
register "PcieRpL1Substates[5]" = "L1_SS_DISABLED"
# Disable LTR for all PCIe root ports # Disable LTR for all PCIe root ports
register "PcieRpLtrDisable[0]" = "true" register "PcieRpLtrDisable[0]" = "true"
register "PcieRpLtrDisable[1]" = "true" register "PcieRpLtrDisable[1]" = "true"
register "PcieRpLtrDisable[2]" = "true" register "PcieRpLtrDisable[2]" = "true"
register "PcieRpLtrDisable[3]" = "true" register "PcieRpLtrDisable[3]" = "true"
register "PcieRpLtrDisable[4]" = "true" register "PcieRpLtrDisable[6]" = "true"
register "PcieRpLtrDisable[5]" = "true"
# Storage (SATA/SDCARD/EMMC) related UPDs # Storage (SATA/SDCARD/EMMC) related UPDs
register "SataSalpSupport" = "0" register "SataSalpSupport" = "0"
@@ -157,8 +153,6 @@ chip soc/intel/elkhartlake
device pci 1c.1 on end # RP2 (pcie0 single VC) device pci 1c.1 on end # RP2 (pcie0 single VC)
device pci 1c.2 on end # RP3 (pcie0 single VC) device pci 1c.2 on end # RP3 (pcie0 single VC)
device pci 1c.3 on end # RP4 (pcie0 single VC) device pci 1c.3 on end # RP4 (pcie0 single VC)
device pci 1c.4 on end # RP5 (pcie1 multi VC)
device pci 1c.5 on end # RP6 (pcie2 multi VC)
device pci 1c.6 on end # RP7 (pcie3 multi VC) device pci 1c.6 on end # RP7 (pcie3 multi VC)
device pci 1e.0 on end # UART0 device pci 1e.0 on end # UART0