soc/mediatek/mt8186: Add DSI driver
Enable DSI for display. BUG=b:209930699 TEST=Firmware display looked good Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Idb6bd3a1d32ac96a9d1a2553b8a70db4e59eec16 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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@@ -46,6 +46,7 @@ romstage-y += ../common/rtc.c ../common/rtc_osc_init.c rtc.c
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ramstage-y += ../common/auxadc.c
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ramstage-y += ../common/ddp.c ddp.c
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ramstage-y += devapc.c
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ramstage-y += ../common/dsi.c ../common/mtk_mipi_dphy.c
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ramstage-y += emi.c
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ramstage-y += ../common/flash_controller.c
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ramstage-y += ../common/gpio.c gpio.c
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60
src/soc/mediatek/mt8186/include/soc/dsi.h
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src/soc/mediatek/mt8186/include/soc/dsi.h
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@@ -0,0 +1,60 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* This file is created based on MT8186 Functional Specification
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* Chapter number: 6.9
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*/
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#ifndef SOC_MEDIATEK_MT8186_DSI_H
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#define SOC_MEDIATEK_MT8186_DSI_H
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#include <soc/dsi_common.h>
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/* DSI features */
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#define MTK_DSI_MIPI_RATIO_NUMERATOR 100
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#define MTK_DSI_MIPI_RATIO_DENOMINATOR 100
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#define MTK_DSI_DATA_RATE_MIN_MHZ 125
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#define MTK_DSI_HAVE_SIZE_CON 1
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#define PIXEL_STREAM_CUSTOM_HEADER 0xb
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/* MIPITX is SOC specific and cannot live in common. */
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/* MIPITX_REG */
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struct mipi_tx_regs {
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u32 reserved0[3];
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u32 lane_con;
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u32 reserved1[6];
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u32 pll_pwr;
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u32 pll_con0;
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u32 pll_con1;
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u32 pll_con2;
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u32 pll_con3;
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u32 pll_con4;
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u32 reserved2[65];
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u32 d2_sw_ctl_en;
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u32 reserved3[63];
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u32 d0_sw_ctl_en;
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u32 reserved4[56];
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u32 ck_ckmode_en;
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u32 reserved5[6];
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u32 ck_sw_ctl_en;
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u32 reserved6[63];
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u32 d1_sw_ctl_en;
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u32 reserved7[63];
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u32 d3_sw_ctl_en;
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};
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check_member(mipi_tx_regs, pll_con4, 0x3c);
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check_member(mipi_tx_regs, d3_sw_ctl_en, 0x544);
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static struct mipi_tx_regs *const mipi_tx = (void *)MIPITX_BASE;
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/* Register values */
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#define DSI_CK_CKMODE_EN BIT(0)
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#define DSI_SW_CTL_EN BIT(0)
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#define AD_DSI_PLL_SDM_PWR_ON BIT(0)
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#define AD_DSI_PLL_SDM_ISO_EN BIT(1)
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#define RG_DSI_PLL_EN BIT(4)
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#define RG_DSI_PLL_POSDIV (0x7 << 8)
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#endif
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