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mb/intel/shadowmountain: Enable HECI1 interface

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The patch enables HECI1 interface

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ia2638559bcaac78d024e35abd09534b61eacb843
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
This commit is contained in:
Sridhar Siricilla 2021-04-16 13:08:38 +05:30 committed by Felix Held
parent 9452aab4d3
commit d742d02fe2
1 changed files with 1 additions and 1 deletions
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src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
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@ -268,7 +268,7 @@ chip soc/intel/alderlake
end
end # I2C2
device pci 15.3 on end # I2C3
device pci 16.0 off end # HECI1
device pci 16.0 on end # HECI1
device pci 16.1 off end # HECI2
device pci 16.2 off end # CSME
device pci 16.3 off end # CSME