mb/siemens/chili: Remove superfluous device entries from dt
Remove the entries which have the same state as the ones from the chipset devicetree. Change-Id: I4981cd835ef28a673d480808dd486fed4d9b45e5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
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@@ -7,21 +7,10 @@ chip soc/intel/cannonlake
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register "PchHdaDspEnable" = "0"
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register "PchHdaAudioLinkHda" = "1"
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device cpu_cluster 0 on end
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device domain 0 on
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device ref system_agent on end
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device ref peg0 off end
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device ref peg1 off end
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device ref peg2 off end
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device ref igpu on end
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device ref dptf on end
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device ref ipu off end
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device ref gna off end
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device ref thermal on end
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device ref ufs off end
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device ref gspi2 off end
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device ref ish off end
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device ref xhci on
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# USB2
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register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C?
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@@ -37,20 +26,7 @@ chip soc/intel/cannonlake
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register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Realtek storage?
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register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" # single blue
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end
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device ref xdci off end
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device ref shared_sram on end
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device ref cnvi_wifi off end
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device ref sdxc off end
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device ref i2c0 off end
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device ref i2c1 off end
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device ref i2c2 off end
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device ref i2c3 off end
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device ref heci1 on end
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device ref heci2 off end
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device ref csme_ider off end
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device ref csme_ktr off end
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device ref heci3 off end
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device ref heci4 off end
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device ref sata on
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register "SataSalpSupport" = "1"
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register "SataPortsEnable[0]" = "1" # HDD / SSD
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@@ -60,14 +36,6 @@ chip soc/intel/cannonlake
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register "SataPortsDevSlp[0]" = "1" # M.2
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register "SataPortsDevSlp[2]" = "1" # HDD / SSD
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end
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device ref i2c4 off end
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device ref i2c5 off end
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device ref uart2 off end
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device ref emmc off end
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device ref pcie_rp1 off end
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device ref pcie_rp2 off end
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device ref pcie_rp3 off end
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device ref pcie_rp4 off end
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device ref pcie_rp5 on
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device pci 00.0 on end # x1 i219
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register "PcieRpEnable[4]" = "1"
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@@ -87,15 +55,6 @@ chip soc/intel/cannonlake
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register "PcieRpSlotImplemented[6]" = "1"
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smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X"
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end
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device ref pcie_rp8 off end
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device ref pcie_rp9 off end
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device ref pcie_rp10 off end
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device ref pcie_rp11 off end
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device ref pcie_rp12 off end
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device ref pcie_rp13 off end
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device ref pcie_rp14 off end
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device ref pcie_rp15 off end
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device ref pcie_rp16 off end
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device ref pcie_rp17 on
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register "PcieRpEnable[16]" = "1"
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register "PcieClkSrcUsage[7]" = "16"
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@@ -103,28 +62,13 @@ chip soc/intel/cannonlake
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register "PcieRpSlotImplemented[16]" = "1"
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smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
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end
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device ref pcie_rp18 off end
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device ref pcie_rp19 off end
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device ref pcie_rp20 off end
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device ref pcie_rp21 off end
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device ref pcie_rp22 off end
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device ref pcie_rp23 off end
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device ref pcie_rp24 off end
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device ref uart0 off end
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device ref uart1 off end
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device ref gspi0 off end
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device ref gspi1 off end
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device ref lpc_espi on
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chip drivers/pc80/tpm
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device pnp 0c31.0 on end
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end
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end
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device ref p2sb hidden end
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device ref pmc hidden end
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device ref hda on end
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device ref smbus on end
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device ref fast_spi on end
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device ref gbe on end
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device ref tracehub off end
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end
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end
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@@ -7,21 +7,10 @@ chip soc/intel/cannonlake
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register "PchHdaDspEnable" = "0"
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register "PchHdaAudioLinkHda" = "1"
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device cpu_cluster 0 on end
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device domain 0 on
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device ref system_agent on end
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device ref peg0 off end
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device ref peg1 off end
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device ref peg2 off end
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device ref igpu on end
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device ref dptf on end
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device ref ipu off end
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device ref gna off end
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device ref thermal on end
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device ref ufs off end
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device ref gspi2 off end
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device ref ish off end
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device ref xhci on
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# USB2
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register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Debug
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@@ -30,10 +19,7 @@ chip soc/intel/cannonlake
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# USB3
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Debug
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end
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device ref xdci off end
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device ref shared_sram on end
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device ref cnvi_wifi off end
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device ref sdxc off end
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device ref i2c0 on
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chip drivers/secunet/dmi
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device i2c 0x57 on end # Serial EEPROM
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@@ -94,28 +80,11 @@ chip soc/intel/cannonlake
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}"
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end
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end
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device ref i2c1 off end
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device ref i2c2 off end
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device ref i2c3 off end
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device ref heci1 on end
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device ref heci2 off end
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device ref csme_ider off end
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device ref csme_ktr off end
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device ref heci3 off end
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device ref heci4 off end
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device ref sata off end
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device ref i2c4 off end
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device ref i2c5 off end
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device ref uart2 off end
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device ref emmc off end
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device ref pcie_rp1 off
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register "PcieRpEnable[0]" = "0" # Debug (x1)
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register "PcieClkSrcUsage[2]" = "0"
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register "PcieClkSrcClkReq[2]" = "2"
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end
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device ref pcie_rp2 off end
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device ref pcie_rp3 off end
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device ref pcie_rp4 off end
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device ref pcie_rp5 on
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register "PcieRpEnable[4]" = "1" # CORE (x1)
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register "PcieClkSrcUsage[4]" = "4"
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@@ -143,14 +112,6 @@ chip soc/intel/cannonlake
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register "PcieClkSrcClkReq[0]" = "0"
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register "PcieRpSlotImplemented[7]" = "0"
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end
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device ref pcie_rp9 off end
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device ref pcie_rp10 off end
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device ref pcie_rp11 off end
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device ref pcie_rp12 off end
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device ref pcie_rp13 off end
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device ref pcie_rp14 off end
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device ref pcie_rp15 off end
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device ref pcie_rp16 off end
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device ref pcie_rp17 on
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register "PcieRpEnable[16]" = "1" # NVMe (x4)
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register "PcieClkSrcUsage[7]" = "16"
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@@ -158,28 +119,13 @@ chip soc/intel/cannonlake
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register "PcieRpSlotImplemented[16]" = "1"
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smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X"
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end
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device ref pcie_rp18 off end
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device ref pcie_rp19 off end
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device ref pcie_rp20 off end
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device ref pcie_rp21 off end
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device ref pcie_rp22 off end
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device ref pcie_rp23 off end
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device ref pcie_rp24 off end
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device ref uart0 on end
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device ref uart1 off end
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device ref gspi0 off end
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device ref gspi1 off end
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device ref lpc_espi on
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chip drivers/pc80/tpm
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device pnp 0c31.0 on end
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end
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end
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device ref p2sb hidden end
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device ref pmc hidden end
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device ref hda on end
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device ref smbus on end
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device ref fast_spi on end
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device ref gbe off end
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device ref tracehub off end
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end
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end
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