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mb/google: Re-arrange mainboard_smi_sleep()

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Change the order of enabling EC and GPE wake sources, so it comes more
obvious we can use existing chromeec handlers without changes.

Change-Id: I5a10afa2b816dc8c01074be68a63114ee027c1e2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74604
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2023-01-05 18:05:11 +02:00
parent 7f4f99d5a5
commit d84ace50e3
3 changed files with 24 additions and 9 deletions
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15
src/mainboard/google/cyan/smihandler.c
View File

@ -37,15 +37,10 @@ void mainboard_smi_sleep(uint8_t slp_typ)
switch (slp_typ) { switch (slp_typ) {
case ACPI_S3: case ACPI_S3:
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
/* Enable wake pin in GPE block. */ /* Enable wake pin in GPE block. */
enable_gpe(WAKE_GPIO_EN); enable_gpe(WAKE_GPIO_EN);
break; break;
case ACPI_S5: case ACPI_S5:
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);
/* Disabling wake from SUS_GPIO1 (TOUCH INT) and /* Disabling wake from SUS_GPIO1 (TOUCH INT) and
* SUS_GPIO7 (TRACKPAD INT) in North bank as they are not * SUS_GPIO7 (TRACKPAD INT) in North bank as they are not
* valid S5 wake sources * valid S5 wake sources
@ -54,7 +49,17 @@ void mainboard_smi_sleep(uint8_t slp_typ)
GPIO_WAKE_MASK_REG0); GPIO_WAKE_MASK_REG0);
mask = ~(GPIO_SUS1_WAKE_MASK | GPIO_SUS7_WAKE_MASK); mask = ~(GPIO_SUS1_WAKE_MASK | GPIO_SUS7_WAKE_MASK);
write32(addr, read32(addr) & mask); write32(addr, read32(addr) & mask);
break;
}
switch (slp_typ) {
case ACPI_S3:
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
break;
case ACPI_S5:
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);
break; break;
} }

9
src/mainboard/google/rambi/smihandler.c
View File

@ -28,11 +28,16 @@ void mainboard_smi_sleep(uint8_t slp_typ)
switch (slp_typ) { switch (slp_typ) {
case ACPI_S3: case ACPI_S3:
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
/* Enable wake pin in GPE block. */ /* Enable wake pin in GPE block. */
enable_gpe(WAKE_GPIO_EN); enable_gpe(WAKE_GPIO_EN);
break; break;
}
switch (slp_typ) {
case ACPI_S3:
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
break;
case ACPI_S5: case ACPI_S5:
/* Enable wake events */ /* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS); google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);

9
src/mainboard/intel/strago/smihandler.c
View File

@ -33,11 +33,16 @@ void mainboard_smi_sleep(uint8_t slp_typ)
switch (slp_typ) { switch (slp_typ) {
case ACPI_S3: case ACPI_S3:
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
/* Enable wake pin in GPE block. */ /* Enable wake pin in GPE block. */
enable_gpe(WAKE_GPIO_EN); enable_gpe(WAKE_GPIO_EN);
break; break;
}
switch (slp_typ) {
case ACPI_S3:
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
break;
case ACPI_S5: case ACPI_S5:
/* Enable wake events */ /* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS); google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);