skl mainboards/dt: Drop SataSalpSupport setting if disabled

The attributes are initialized with 0 and thus setting them to 0 makes
them superfluous. Remove them.

Change-Id: Icb41f0a9baded01267410bd4c9458ab4bfb82b70
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83175
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>

src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb

@@ -58,7 +58,6 @@ chip soc/intel/skylake
 		device ref thermal	on	end
 		device ref heci1	on	end
 		device ref sata		on
-			register "SataSalpSupport" = "0"
 			# Ports
 			register "SataPortsEnable[0]" = "1"
 			register "SataPortsEnable[2]" = "1"

src/mainboard/google/eve/devicetree.cb

@@ -36,7 +36,6 @@ chip soc/intel/skylake
 	register "gen3_dec" = "0x00fc0901"
 
 	# FSP Configuration
-	register "SataSalpSupport" = "0"
 	register "SataPortsEnable[0]" = "0"
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"

src/mainboard/google/fizz/variants/baseboard/devicetree.cb

@@ -65,7 +65,6 @@ chip soc/intel/skylake
 	register "s0ix_enable" = true
 
 	# FSP Configuration
-	register "SataSalpSupport" = "0"
 	register "SataPortsEnable[0]" = "1"
 	register "SataPortsEnable[1]" = "1"
 	register "SataPortsDevSlp[1]" = "1"

src/mainboard/google/glados/devicetree.cb

@@ -35,7 +35,6 @@ chip soc/intel/skylake
 	register "dptf_enable" = "1"
 
 	# FSP Configuration
-	register "SataSalpSupport" = "0"
 	register "SataPortsEnable[0]" = "0"
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"

src/mainboard/google/poppy/variants/atlas/devicetree.cb

@@ -43,7 +43,6 @@ chip soc/intel/skylake
 	register "CmdTriStateDis" = "1"
 
 	# FSP Configuration
-	register "SataSalpSupport" = "0"
 	register "SataPortsEnable[0]" = "0"
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"

src/mainboard/google/poppy/variants/baseboard/devicetree.cb

@@ -31,7 +31,6 @@ chip soc/intel/skylake
 	register "s0ix_enable" = true
 
 	# FSP Configuration
-	register "SataSalpSupport" = "0"
 	register "SataPortsEnable[0]" = "0"
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"

src/mainboard/google/poppy/variants/nami/devicetree.cb

@@ -40,7 +40,6 @@ chip soc/intel/skylake
 	register "s0ix_enable" = true
 
 	# FSP Configuration
-	register "SataSalpSupport" = "0"
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
 	register "ScsEmmcHs400Enabled" = "1"

src/mainboard/google/poppy/variants/nautilus/devicetree.cb

@@ -40,7 +40,6 @@ chip soc/intel/skylake
 	register "s0ix_enable" = true
 
 	# FSP Configuration
-	register "SataSalpSupport" = "0"
 	register "SataPortsEnable[0]" = "0"
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"

src/mainboard/google/poppy/variants/nocturne/devicetree.cb

@@ -36,7 +36,6 @@ chip soc/intel/skylake
 	register "CmdTriStateDis" = "1"
 
 	# FSP Configuration
-	register "SataSalpSupport" = "0"
 	register "SataPortsEnable[0]" = "0"
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"

src/mainboard/google/poppy/variants/rammus/devicetree.cb

@@ -43,7 +43,6 @@ chip soc/intel/skylake
 	register "CmdTriStateDis" = "1"
 
 	# FSP Configuration
-	register "SataSalpSupport" = "0"
 	register "SataPortsEnable[0]" = "0"
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"

src/mainboard/google/poppy/variants/soraka/devicetree.cb

@@ -40,7 +40,6 @@ chip soc/intel/skylake
 	register "s0ix_enable" = true
 
 	# FSP Configuration
-	register "SataSalpSupport" = "0"
 	register "SataPortsEnable[0]" = "0"
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"

src/mainboard/libretrend/lt1000/devicetree.cb

@@ -33,7 +33,6 @@ chip soc/intel/skylake
 	register "dptf_enable" = "0"
 
 	# FSP Configuration
-	register "SataSalpSupport" = "0"
 	register "SataPortsEnable" = "{
 		[0] = 1,
 		[1] = 1,

src/mainboard/protectli/vault_kbl/devicetree.cb

@@ -28,7 +28,6 @@ chip soc/intel/skylake
 	register "tcc_offset" = "5" # TCC of 95C
 
 	# FSP Configuration
-	register "SataSalpSupport" = "0"
 	register "DspEnable" = "0"
 	register "IoBufferOwnership" = "0"
 	register "SkipExtGfxScan" = "1"

src/mainboard/purism/librem_skl/devicetree.cb

@@ -41,7 +41,6 @@ chip soc/intel/skylake
 	register "dptf_enable" = "0"
 
 	# FSP Configuration
-	register "SataSalpSupport" = "0"
 	register "SataPortsEnable[0]" = "1"
 	register "SataPortsEnable[1]" = "0"
 	register "SataPortsEnable[2]" = "1"

src/mainboard/razer/blade_stealth_kbl/devicetree.cb

@@ -22,7 +22,6 @@ chip soc/intel/skylake
 	register "dptf_enable" = "0"
 
 	# FSP Configuration
-	register "SataSalpSupport" = "0"
 	register "SataPortsEnable" = "{
 		[0] = 0,
 		[1] = 0,

src/mainboard/system76/kbl-u/devicetree.cb

@@ -128,7 +128,6 @@ chip soc/intel/skylake
 		end
 		device ref thermal on end
 		device ref sata on
-			register "SataSalpSupport" = "0"
 			register "SataSpeedLimit" = "2"
 			register "SataPortsEnable" = "{
 				[0] = 1,