mainboard/google/reef: add baseboard memory configuration
Move the current memory configuration implementation to the baseboard area such that other variants can leverage it. The swizzle config is exported as a global to allow duplicate swizzles to use the same structure while still allowing different memory SKUs. BUG=chrome-os-partner:56677 Change-Id: I57201118053051c01f0e3f164ab4bbaf650b892b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16430 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Aaron Durbin
parent
475d2cb19e
commit
d94967dd22
@ -13,165 +13,17 @@
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <gpio.h>
|
||||
#include <baseboard/variants.h>
|
||||
#include <soc/meminit.h>
|
||||
#include <soc/romstage.h>
|
||||
#include <variant/gpio.h>
|
||||
|
||||
static const struct lpddr4_swizzle_cfg board_swizzle = {
|
||||
/* CH0_DQA[0:31] SoC pins -> U22 LPDDR4 module pins */
|
||||
.phys[LP4_PHYS_CH0A] = {
|
||||
/* DQA[0:7] pins of LPDDR4 module. */
|
||||
.dqs[LP4_DQS0] = { 6, 7, 5, 4, 3, 1, 0, 2 },
|
||||
/* DQA[8:15] pins of LPDDR4 module. */
|
||||
.dqs[LP4_DQS1] = { 12, 10, 11, 13, 14, 8, 9, 15 },
|
||||
/* DQB[0:7] pins of LPDDR4 module with offset of 16. */
|
||||
.dqs[LP4_DQS2] = { 16, 22, 23, 20, 18, 17, 19, 21 },
|
||||
/* DQB[7:15] pins of LPDDR4 module with offset of 16. */
|
||||
.dqs[LP4_DQS3] = { 30, 28, 29, 25, 24, 26, 27, 31 },
|
||||
},
|
||||
.phys[LP4_PHYS_CH0B] = {
|
||||
/* DQA[0:7] pins of LPDDR4 module. */
|
||||
.dqs[LP4_DQS0] = { 7, 3, 5, 2, 6, 0, 1, 4 },
|
||||
/* DQA[8:15] pins of LPDDR4 module. */
|
||||
.dqs[LP4_DQS1] = { 9, 14, 12, 13, 10, 11, 8, 15 },
|
||||
/* DQB[0:7] pins of LPDDR4 module with offset of 16. */
|
||||
.dqs[LP4_DQS2] = { 20, 22, 23, 16, 19, 17, 18, 21 },
|
||||
/* DQB[7:15] pins of LPDDR4 module with offset of 16. */
|
||||
.dqs[LP4_DQS3] = { 28, 24, 26, 27, 29, 30, 31, 25 },
|
||||
},
|
||||
.phys[LP4_PHYS_CH1A] = {
|
||||
/* DQA[0:7] pins of LPDDR4 module. */
|
||||
.dqs[LP4_DQS0] = { 2, 1, 6, 7, 5, 4, 3, 0 },
|
||||
/* DQA[8:15] pins of LPDDR4 module. */
|
||||
.dqs[LP4_DQS1] = { 11, 10, 8, 9, 12, 15, 13, 14 },
|
||||
/* DQB[0:7] pins of LPDDR4 module with offset of 16. */
|
||||
.dqs[LP4_DQS2] = { 17, 23, 19, 16, 21, 22, 20, 18 },
|
||||
/* DQB[7:15] pins of LPDDR4 module with offset of 16. */
|
||||
.dqs[LP4_DQS3] = { 31, 29, 26, 25, 28, 27, 24, 30 },
|
||||
},
|
||||
.phys[LP4_PHYS_CH1B] = {
|
||||
/* DQA[0:7] pins of LPDDR4 module. */
|
||||
.dqs[LP4_DQS0] = { 4, 3, 7, 5, 6, 1, 0, 2 },
|
||||
/* DQA[8:15] pins of LPDDR4 module. */
|
||||
.dqs[LP4_DQS1] = { 15, 9, 8, 11, 14, 13, 12, 10 },
|
||||
/* DQB[0:7] pins of LPDDR4 module with offset of 16. */
|
||||
.dqs[LP4_DQS2] = { 20, 23, 22, 21, 18, 19, 16, 17 },
|
||||
/* DQB[7:15] pins of LPDDR4 module with offset of 16. */
|
||||
.dqs[LP4_DQS3] = { 25, 28, 30, 31, 26, 27, 24, 29 },
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* Proto boards didn't have a memory SKU id. The configuration pins use
|
||||
* an internal weak pullup with stronger pulldowns for the 0 bits. As
|
||||
* proto boards didn't use the memory SKU pins the SKU id reads as 4'b1111,
|
||||
* i.e. 15.
|
||||
*/
|
||||
#define PROTO_SKU 15
|
||||
|
||||
static const struct lpddr4_sku skus[] = {
|
||||
/*
|
||||
* K4F6E304HB-MGCJ - both logical channels While the parts
|
||||
* are listed at 16Gb there are 2 ranks per channel so indicate
|
||||
* the deneisty as 8Gb per rank.
|
||||
*/
|
||||
[0] = {
|
||||
.speed = LP4_SPEED_2400,
|
||||
.ch0_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch1_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch0_dual_rank = 1,
|
||||
.ch1_dual_rank = 1,
|
||||
.part_num = "K4F6E304HB-MGCJ",
|
||||
},
|
||||
/* K4F8E304HB-MGCJ - both logical channels */
|
||||
[1] = {
|
||||
.speed = LP4_SPEED_2400,
|
||||
.ch0_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch1_rank_density = LP4_8Gb_DENSITY,
|
||||
.part_num = "K4F8E304HB-MGCJ",
|
||||
},
|
||||
/*
|
||||
* MT53B512M32D2NP-062WT:C - both logical channels. While the parts
|
||||
* are listed at 16Gb there are 2 ranks per channel so indicate
|
||||
* the deneisty as 8Gb per rank.
|
||||
*/
|
||||
[2] = {
|
||||
.speed = LP4_SPEED_2400,
|
||||
.ch0_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch1_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch0_dual_rank = 1,
|
||||
.ch1_dual_rank = 1,
|
||||
.part_num = "MT53B512M32D2NP",
|
||||
.disable_periodic_retraining = 1,
|
||||
},
|
||||
/* MT53B256M32D1NP-062 WT:C - both logical channels */
|
||||
[3] = {
|
||||
.speed = LP4_SPEED_2400,
|
||||
.ch0_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch1_rank_density = LP4_8Gb_DENSITY,
|
||||
.part_num = "MT53B256M32D1NP",
|
||||
.disable_periodic_retraining = 1,
|
||||
},
|
||||
/*
|
||||
* H9HCNNNBPUMLHR-NLE - both logical channels. While the parts
|
||||
* are listed at 16Gb there are 2 ranks per channel so indicate the
|
||||
* density as 8Gb per rank.
|
||||
*/
|
||||
[4] = {
|
||||
.speed = LP4_SPEED_2400,
|
||||
.ch0_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch1_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch0_dual_rank = 1,
|
||||
.ch1_dual_rank = 1,
|
||||
.part_num = "H9HCNNNBPUMLHR",
|
||||
},
|
||||
/* H9HCNNN8KUMLHR-NLE - both logical channels */
|
||||
[5] = {
|
||||
.speed = LP4_SPEED_2400,
|
||||
.ch0_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch1_rank_density = LP4_8Gb_DENSITY,
|
||||
.part_num = "H9HCNNN8KUMLHR",
|
||||
},
|
||||
/* K4F8E304HB-MGCH - both logical channels */
|
||||
[PROTO_SKU] = {
|
||||
.speed = LP4_SPEED_2400,
|
||||
.ch0_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch1_rank_density = LP4_8Gb_DENSITY,
|
||||
.part_num = "K4F8E304HB-MGCH",
|
||||
},
|
||||
};
|
||||
|
||||
static const struct lpddr4_cfg lp4cfg = {
|
||||
.skus = skus,
|
||||
.num_skus = ARRAY_SIZE(skus),
|
||||
.swizzle_config = &board_swizzle,
|
||||
};
|
||||
|
||||
static int get_mem_sku(void)
|
||||
{
|
||||
gpio_t pads[] = {
|
||||
[3] = MEM_CONFIG3, [2] = MEM_CONFIG2,
|
||||
[1] = MEM_CONFIG1, [0] = MEM_CONFIG0,
|
||||
};
|
||||
|
||||
/*
|
||||
* Read memory SKU id with internal pullups enabled to handle
|
||||
* proto boards with no SKU id pins.
|
||||
*/
|
||||
return gpio_pullup_base2_value(pads, ARRAY_SIZE(pads));
|
||||
}
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *memupd)
|
||||
{
|
||||
int mem_sku = get_mem_sku();
|
||||
|
||||
meminit_lpddr4_by_sku(&memupd->FspmConfig, &lp4cfg, mem_sku);
|
||||
meminit_lpddr4_by_sku(&memupd->FspmConfig,
|
||||
variant_lpddr4_config(), variant_memory_sku());
|
||||
}
|
||||
|
||||
void mainboard_save_dimm_info(void)
|
||||
{
|
||||
int mem_sku = get_mem_sku();
|
||||
|
||||
save_lpddr4_dimm_info(&lp4cfg, mem_sku);
|
||||
save_lpddr4_dimm_info(variant_lpddr4_config(), variant_memory_sku());
|
||||
}
|
||||
|
||||
@ -1,6 +1,7 @@
|
||||
bootblock-y += gpio.c
|
||||
|
||||
romstage-y += boardid.c
|
||||
romstage-y += memory.c
|
||||
|
||||
ramstage-y += boardid.c
|
||||
ramstage-y += gpio.c
|
||||
|
||||
@ -17,6 +17,7 @@
|
||||
#define BASEBOARD_VARIANTS_H
|
||||
|
||||
#include <soc/gpio.h>
|
||||
#include <soc/meminit.h>
|
||||
#include <stdint.h>
|
||||
#include <vendorcode/google/chromeos/chromeos.h>
|
||||
|
||||
@ -29,6 +30,13 @@ const struct pad_config *variant_gpio_table(size_t *num);
|
||||
const struct pad_config *variant_early_gpio_table(size_t *num);
|
||||
const struct pad_config *variant_sleep_gpio_table(size_t *num);
|
||||
|
||||
/* Baseboard default swizzle. Can be reused if swizzle is same. */
|
||||
extern const struct lpddr4_swizzle_cfg baseboard_lpddr4_swizzle;
|
||||
/* Return LPDDR4 configuration structure. */
|
||||
const struct lpddr4_cfg *variant_lpddr4_config(void);
|
||||
/* Return memory SKU for the board. */
|
||||
size_t variant_memory_sku(void);
|
||||
|
||||
/* Return ChromeOS gpio table and fill in number of entries. */
|
||||
const struct cros_gpio *variant_cros_gpios(size_t *num);
|
||||
|
||||
|
||||
168
src/mainboard/google/reef/variants/baseboard/memory.c
Normal file
168
src/mainboard/google/reef/variants/baseboard/memory.c
Normal file
@ -0,0 +1,168 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2016 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <baseboard/variants.h>
|
||||
#include <gpio.h>
|
||||
#include <soc/meminit.h>
|
||||
#include <variant/gpio.h>
|
||||
|
||||
const struct lpddr4_swizzle_cfg baseboard_lpddr4_swizzle = {
|
||||
/* CH0_DQA[0:31] SoC pins -> U22 LPDDR4 module pins */
|
||||
.phys[LP4_PHYS_CH0A] = {
|
||||
/* DQA[0:7] pins of LPDDR4 module. */
|
||||
.dqs[LP4_DQS0] = { 6, 7, 5, 4, 3, 1, 0, 2 },
|
||||
/* DQA[8:15] pins of LPDDR4 module. */
|
||||
.dqs[LP4_DQS1] = { 12, 10, 11, 13, 14, 8, 9, 15 },
|
||||
/* DQB[0:7] pins of LPDDR4 module with offset of 16. */
|
||||
.dqs[LP4_DQS2] = { 16, 22, 23, 20, 18, 17, 19, 21 },
|
||||
/* DQB[7:15] pins of LPDDR4 module with offset of 16. */
|
||||
.dqs[LP4_DQS3] = { 30, 28, 29, 25, 24, 26, 27, 31 },
|
||||
},
|
||||
.phys[LP4_PHYS_CH0B] = {
|
||||
/* DQA[0:7] pins of LPDDR4 module. */
|
||||
.dqs[LP4_DQS0] = { 7, 3, 5, 2, 6, 0, 1, 4 },
|
||||
/* DQA[8:15] pins of LPDDR4 module. */
|
||||
.dqs[LP4_DQS1] = { 9, 14, 12, 13, 10, 11, 8, 15 },
|
||||
/* DQB[0:7] pins of LPDDR4 module with offset of 16. */
|
||||
.dqs[LP4_DQS2] = { 20, 22, 23, 16, 19, 17, 18, 21 },
|
||||
/* DQB[7:15] pins of LPDDR4 module with offset of 16. */
|
||||
.dqs[LP4_DQS3] = { 28, 24, 26, 27, 29, 30, 31, 25 },
|
||||
},
|
||||
.phys[LP4_PHYS_CH1A] = {
|
||||
/* DQA[0:7] pins of LPDDR4 module. */
|
||||
.dqs[LP4_DQS0] = { 2, 1, 6, 7, 5, 4, 3, 0 },
|
||||
/* DQA[8:15] pins of LPDDR4 module. */
|
||||
.dqs[LP4_DQS1] = { 11, 10, 8, 9, 12, 15, 13, 14 },
|
||||
/* DQB[0:7] pins of LPDDR4 module with offset of 16. */
|
||||
.dqs[LP4_DQS2] = { 17, 23, 19, 16, 21, 22, 20, 18 },
|
||||
/* DQB[7:15] pins of LPDDR4 module with offset of 16. */
|
||||
.dqs[LP4_DQS3] = { 31, 29, 26, 25, 28, 27, 24, 30 },
|
||||
},
|
||||
.phys[LP4_PHYS_CH1B] = {
|
||||
/* DQA[0:7] pins of LPDDR4 module. */
|
||||
.dqs[LP4_DQS0] = { 4, 3, 7, 5, 6, 1, 0, 2 },
|
||||
/* DQA[8:15] pins of LPDDR4 module. */
|
||||
.dqs[LP4_DQS1] = { 15, 9, 8, 11, 14, 13, 12, 10 },
|
||||
/* DQB[0:7] pins of LPDDR4 module with offset of 16. */
|
||||
.dqs[LP4_DQS2] = { 20, 23, 22, 21, 18, 19, 16, 17 },
|
||||
/* DQB[7:15] pins of LPDDR4 module with offset of 16. */
|
||||
.dqs[LP4_DQS3] = { 25, 28, 30, 31, 26, 27, 24, 29 },
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* Proto boards didn't have a memory SKU id. The configuration pins use
|
||||
* an internal weak pullup with stronger pulldowns for the 0 bits. As
|
||||
* proto boards didn't use the memory SKU pins the SKU id reads as 4'b1111,
|
||||
* i.e. 15.
|
||||
*/
|
||||
#define PROTO_SKU 15
|
||||
|
||||
static const struct lpddr4_sku skus[] = {
|
||||
/*
|
||||
* K4F6E304HB-MGCJ - both logical channels While the parts
|
||||
* are listed at 16Gb there are 2 ranks per channel so indicate
|
||||
* the deneisty as 8Gb per rank.
|
||||
*/
|
||||
[0] = {
|
||||
.speed = LP4_SPEED_2400,
|
||||
.ch0_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch1_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch0_dual_rank = 1,
|
||||
.ch1_dual_rank = 1,
|
||||
.part_num = "K4F6E304HB-MGCJ",
|
||||
},
|
||||
/* K4F8E304HB-MGCJ - both logical channels */
|
||||
[1] = {
|
||||
.speed = LP4_SPEED_2400,
|
||||
.ch0_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch1_rank_density = LP4_8Gb_DENSITY,
|
||||
.part_num = "K4F8E304HB-MGCJ",
|
||||
},
|
||||
/*
|
||||
* MT53B512M32D2NP-062WT:C - both logical channels. While the parts
|
||||
* are listed at 16Gb there are 2 ranks per channel so indicate
|
||||
* the deneisty as 8Gb per rank.
|
||||
*/
|
||||
[2] = {
|
||||
.speed = LP4_SPEED_2400,
|
||||
.ch0_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch1_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch0_dual_rank = 1,
|
||||
.ch1_dual_rank = 1,
|
||||
.part_num = "MT53B512M32D2NP",
|
||||
.disable_periodic_retraining = 1,
|
||||
},
|
||||
/* MT53B256M32D1NP-062 WT:C - both logical channels */
|
||||
[3] = {
|
||||
.speed = LP4_SPEED_2400,
|
||||
.ch0_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch1_rank_density = LP4_8Gb_DENSITY,
|
||||
.part_num = "MT53B256M32D1NP",
|
||||
.disable_periodic_retraining = 1,
|
||||
},
|
||||
/*
|
||||
* H9HCNNNBPUMLHR-NLE - both logical channels. While the parts
|
||||
* are listed at 16Gb there are 2 ranks per channel so indicate the
|
||||
* density as 8Gb per rank.
|
||||
*/
|
||||
[4] = {
|
||||
.speed = LP4_SPEED_2400,
|
||||
.ch0_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch1_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch0_dual_rank = 1,
|
||||
.ch1_dual_rank = 1,
|
||||
.part_num = "H9HCNNNBPUMLHR",
|
||||
},
|
||||
/* H9HCNNN8KUMLHR-NLE - both logical channels */
|
||||
[5] = {
|
||||
.speed = LP4_SPEED_2400,
|
||||
.ch0_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch1_rank_density = LP4_8Gb_DENSITY,
|
||||
.part_num = "H9HCNNN8KUMLHR",
|
||||
},
|
||||
/* K4F8E304HB-MGCH - both logical channels */
|
||||
[PROTO_SKU] = {
|
||||
.speed = LP4_SPEED_2400,
|
||||
.ch0_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch1_rank_density = LP4_8Gb_DENSITY,
|
||||
.part_num = "K4F8E304HB-MGCH",
|
||||
},
|
||||
};
|
||||
|
||||
static const struct lpddr4_cfg lp4cfg = {
|
||||
.skus = skus,
|
||||
.num_skus = ARRAY_SIZE(skus),
|
||||
.swizzle_config = &baseboard_lpddr4_swizzle,
|
||||
};
|
||||
|
||||
const struct lpddr4_cfg * __attribute__((weak)) variant_lpddr4_config(void)
|
||||
{
|
||||
return &lp4cfg;
|
||||
}
|
||||
|
||||
size_t __attribute__((weak)) variant_memory_sku(void)
|
||||
{
|
||||
gpio_t pads[] = {
|
||||
[3] = MEM_CONFIG3, [2] = MEM_CONFIG2,
|
||||
[1] = MEM_CONFIG1, [0] = MEM_CONFIG0,
|
||||
};
|
||||
|
||||
/*
|
||||
* Read memory SKU id with internal pullups enabled to handle
|
||||
* proto boards with no SKU id pins.
|
||||
*/
|
||||
return gpio_pullup_base2_value(pads, ARRAY_SIZE(pads));
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user