sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Merge 4.16

Browse Source 
Change-Id: I11db70a8e25a6656c5ec640a703e7b06d5a3672e
This commit is contained in:
Jeremy Soller
2022-03-04 07:19:45 -07:00
parent af64e5d166
commit d97e25ac13
3138 changed files with 317025 additions and 23253 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
Documentation/acpi/gpio.md
View File

@@ -84,15 +84,6 @@ the raw Rx gpio value.
## Implementation Details
ACPI library in coreboot will provide weak definitions for all the
above functions with error messages indicating that these functions
are being used. This allows drivers to conditionally make use of GPIOs
based on device-tree entries or any other config option. It is
recommended that the SoC code in coreboot should provide
implementations of all the above functions generating ACPI AML code
irrespective of them being used in any driver. This allows mainboards
to use any drivers and take advantage of this common infrastructure.
Platforms are restricted to using Local5, Local6 and Local7 variables
only in implementations of the above functions. Any AML methods called
by the above functions do not have any such restrictions on use of

7
Documentation/community/index.md Normal file
View File

@@ -0,0 +1,7 @@
# Community
* [Code of Conduct](code_of_conduct.md)
* [Language style](language_style.md)
* [Community forums](forums.md)
* [Project services](services.md)
* [coreboot at conferences](conferences.md)

2
Documentation/community/services.md
View File

@@ -1,6 +1,6 @@
# Accounts on coreboot.org
There are a number of places where you can benefit from creaating an account
There are a number of places where you can benefit from creating an account
in our community. Since there is no single sign-on system in place (at this
time), they come with their own setup routines.

249
Documentation/contributing/gsoc.md Normal file
View File

@@ -0,0 +1,249 @@
# Google Summer of Code
## Contacts
If you are interested in participating in GSoC as a contributor or mentor,
please have a look at our [community forums] and reach out to us. Working closely
with the community is highly encouraged, as we've seen that our most successful
contributors are generally very involved.
Felix Singer, David Hendricks and Martin Roth are the coreboot GSoC admins for
2022. Please feel free to reach out to them directly if you have any questions.
## Why work on coreboot for GSoC?
* coreboot offers you the opportunity to work with various architectures
right on the iron. coreboot supports both current and older silicon for a
wide variety of chips and technologies.
* coreboot has a worldwide developer and user base.
* We are a very passionate team, so you will interact directly with the
project initiators and project leaders.
* We have a large, helpful community. coreboot has some extremely talented
and helpful experts in firmware involved in the project. They are ready to
assist and mentor contributors participating in GSoC.
* One of the last areas where open source software is not common is firmware.
Running proprietary firmware can have severe effects on user's freedom and
security. coreboot has a mission to change that by providing a common
framework for initial hardware initialization and you can help us succeed.
## Contributor requirements & commitments
Google Summer of Code is a significant time commitment for you. Medium-sized
projects are estimated to take 175 hours, while large-sized projects are
estimated to take 350 hours. Depending on the project size, this means we
expect you to work roughly half-time or full-time on your project during the
three months of coding. We expect to be able to see this level of effort in the
results.
The standard program duration is 12 weeks and in consultation with the mentor
it can be extended up to 22 weeks. Please keep in mind that the actual number
of hours you spend on the project highly depends on your skills and previous
experience.
Make sure that your schedule (exams, courses, day job) gives you a sufficient
amount of spare time. If this is not the case, then you should not apply.
### Before applying
* Join the [mailing list] and our other [community forums]. Introduce yourself
and mention that you are a prospective GSoC contributor. Ask questions and
discuss the project that you are considering. Community involvement is a
key component of coreboot development.
* You accept our [Code of Conduct] and [Language style].
* Demonstrate that you can work with the coreboot codebase.
* Look over some of the development processes guidelines: [Getting started],
[Tutorial], [Flashing firmware tutorial] and [Coding style].
* Download, build and boot coreboot in QEMU or on real hardware. Please email
your serial output results to the [mailing list].
* Look through some patches on Gerrit to get an understanding of the review
process and common issues.
* Get signed up for Gerrit and push at least one patch to Gerrit for review.
Check Easy projects or ask for simple tasks on the [mailing list] or on our
other [community forums] if you need ideas.
### During the program
* To pass and to be paid by Google requires that you meet certain milestones.
* First, you must be in good standing with the community before the official
start of the program. We expect you to post some design emails to the
[mailing list], and get feedback on them, both before applying, and during
the "community bonding period" between acceptance and official start.
* You must have made progress and committed significant code before the
mid-term point and by the final.
* We require that accepted contributors to maintain a blog, where you are
expected to write about your project *WEEKLY*. This is a way to measure
progress and for the community at large to be able to help you. GSoC is
*NOT* a private contract between your mentor and you.
* You must be active in the community on IRC and the [mailing list].
* You are expected to work on development publicly, and to push commits to the
project on a regular basis. Depending on the project and what your mentor
agrees to, these can be published directly to the project or to a public
repository such as Gitlab or Github. If you are not publishing directly to
the project codebase, be aware that we do not want large dumps of code that
need to be rushed to meet the mid-term and final goals.
We don't expect our contributors to be experts in our problem domain, but we
don't want you to fail because some basic misunderstanding was in your way of
completing the task.
## Projects
There are many development tasks available in coreboot. We prepared some ideas
for Summer of Code projects. These are projects that we think can be managed in
the timeline of GSoC, and they cover areas where coreboot is trying to reach
new users and new use cases.
Of course your application does not have to be based on any of the ideas listed.
It is entirely possible that you have a great idea that we just didn't think of
yet. Please let us know!
The blog posts related to previous GSoC projects might give some insights to
what it is like to be a coreboot GSoC contributor.
## coreboot Summer of Code Application
coreboot welcomes contributors from all backgrounds and levels of experience.
Your application should include a complete project proposal. You should
document that you have the knowledge and the ability to complete your proposed
project. This may require a little research and understanding of coreboot prior
to sending your application. The community and coreboot project mentors are your
best resource in fleshing out your project ideas and helping with a project
timeline. We recommend that you get feedback and recommendations on your
proposal before the application deadline.
Please complete the standard GSoC application and project proposal. Provide the
following information as part of your application. Make sure to provide multiple
ways of communicating in case your equipment (such as a laptop) is lost,
damaged, or stolen, or in case of a natural disaster that disrupts internet
service. You risk automatically failing if your mentor cannot contact you and if
you cannot provide updates according to GSoC deadlines.
**Personal Information**
* Name
* Email and contact options (IRC, Matrix, …)
* Phone number (optional, but recommended)
* Timezone, Usual working hours (UTC)
* School / University, Degree Program, expected graduation date
* Short bio / Overview of your background
* What are your other time commitments? Do you have a job, classes, vacations?
When and how long?
**Software experience**
If applicable, please provide the following information:
* Portfolio, Website, blog, microblog, Github, Gitlab, ...
* Links to one or more patches submitted
* Links to posts on the [mailing list] with the serial output of your build.
* Please comment on your software and firmware experience.
* Have you contributed to an open source project? Which one? What was your
experience?
* What was your experience while building and running coreboot? Did you have
problems?
**Your project**
* Provide an overview of your project (in your own words).
* Provide a breakdown of your project in small specific weekly goals. Think
about the potential timeline.
* How will you accomplish this goal? What is your working style?
* Explain what risks or potential problems your project might experience.
* What would you expect as a minimum level of success?
* Do you have a stretch goal?
**Other**
* Resume (optional)
### Advice on how to apply
* [GSoC Contributor Guide]
* The Drupal project has a great page on how to write an GSoC application.
* Secrets for GSoC success: [2]
## Mentors
Each accepted project will have at least one mentor. We will match mentors and
contributors based on the project and experience level. If possible, we also
will try to match their time zones.
Mentors are expected to stay in frequent contact with the contributor and
provide guidance such as code reviews, pointers to useful documentation, etc.
This should generally be a time commitment of several hours per week.
Some projects might have more than one mentor, who can serve as a backup. They
are expected to coordinate with each other and a contributor on a regular basis,
and keep track of the contributor process. They should be able to take over
mentoring duty if one of the mentors is unavailable (vacations, sickness,
emergencies).
### Volunteering to be a mentor
If you'd like to volunteer to be a mentor, please read the [GSoC Mentor Guide].
This will give you a better idea of expectations, and where to go for help.
After that, contact Org Admins (see coreboot contacts section above).
The following coreboot developers have volunteered to be GSoC 2022 mentors.
Please stop by in our community forums and say hi to them and ask them
questions.
* Tim Wawrzynczak
* Raul Rangel
* Ron Minnich
[community forums]: ../community/forums.md
[mailing list]: https://mail.coreboot.org/postorius/lists/coreboot.coreboot.org
[Getting started]: ../getting_started/index.md
[Tutorial]: ../tutorial/index.md
[Flashing firmware tutorial]: ../flash_tutorial/index.md
[Coding style]: coding_style.md
[Code of Conduct]: ../community/code_of_conduct.md
[Language style]: ../community/language_style.md
[GSoC Contributor Guide]: https://google.github.io/gsocguides/student
[GSoC Mentor Guide]: https://google.github.io/gsocguides/mentor

6
Documentation/contributing/index.md Normal file
View File

@@ -0,0 +1,6 @@
# Contributing
* [Coding Style](coding_style.md)
* [Project Ideas](project_ideas.md)
* [Documentation Ideas](documentation_ideas.md)
* [Google Summer of Code](gsoc.md)

7
Documentation/distributions.md
View File

@@ -24,6 +24,13 @@ ships with coreboot and support upstream maintenance for the devices through a
third party, [3mdeb](https://3mdeb.com). They provide current and tested
firmware binaries on [GitHub](https://pcengines.github.io).
### Star Labs
[Star Labs](https://starlabs.systems/) offers a range of laptops designed and
built specifically for Linux that are available with coreboot firmware. They
use Tianocore as the payload and include an NVRAM option to disable the
Intel Management Engine.
### System76
[System76](https://system76.com/) manufactures Linux laptops, desktops, and

6
Documentation/getting_started/gerrit_guidelines.md
View File

@@ -193,8 +193,10 @@ the wip flag:
* When pushing patches that are not for submission, these should be marked
as such. This can be done in the title ‘[DONOTSUBMIT]’, or can be pushed as
private changes, so that only explicitly added reviewers will see them. These
sorts of patches are frequently posted as ideas or RFCs for the community
to look at. To push a private change, use the command:
sorts of patches are frequently posted as ideas or RFCs for the community to
look at. Note that private changes can still be fetched from Gerrit by anybody
who knows their commit ID, so don't use this for sensitive changes. To push
a private change, use the command:
git push origin HEAD:refs/for/master%private
* Multiple push options can be combined:

47
Documentation/getting_started/gpio.md
View File

@@ -162,6 +162,53 @@ The first is configuring a pin as an output, when it was designed to be an
input. There is a real risk in this case of short-circuiting a component which
could cause catastrophic failures, up to and including your mainboard!
### Intel SoCs
As per Intel Platform Controller Hub (PCH) EDS since Skylake, a GPIO PAD register
supports four different types of GPIO reset as:
| PAD Reset Config | Platform Reset | GPP | GPD |
|-------------------------------------------------|----------------|-----|-----|
| 00 - Power Good (GPP: RSMRST, GPD: DSW_PWROK) | Warm Reset | N | N |
| | Cold Reset | N | N |
| | S3/S4/S5 | N | N |
| | Global Reset | N | N |
| | Deep Sx | Y | N |
| | G3 | Y | N |
| 01 - Deep | Warm Reset | Y | Y |
| | Cold Reset | Y | Y |
| | S3/S4/S5 | N | N |
| | Global Reset | Y | Y |
| | Deep Sx | Y | Y |
| | G3 | Y | Y |
| 10 - Host Reset/PLTRST | Warm Reset | Y | Y |
| | Cold Reset | Y | Y |
| | S3/S4/S5 | Y | Y |
| | Global Reset | Y | Y |
| | Deep Sx | Y | Y |
| | G3 | Y | Y |
| 11 - Resume Reset (GPP: Reserved, GPD: RSMRST) | Warm Reset | - | N |
| | Cold Reset | - | N |
| | S3/S4/S5 | - | N |
| | Global Reset | - | N |
| | Deep Sx | - | Y |
| | G3 | - | Y |
Each GPIO Community has a Pad Configuration Lock register for a GPP allowing locking
specific register fields in the PAD configuration register.
The Pad Config Lock registers reset type is default hardcoded to **Power Good** and
it's **not** configurable by GPIO PAD DW0.PadRstCfg. Hence, it may appear that for a GPP,
the Pad Reset Config (DW0 Bit 31) is configured differently from `Power Good`.
This would create confusion where the Pad configuration is returned to its `default`
value but remains `locked`, this would prevent software to reprogram the GPP.
Additionally, this means software can't rely on GPIOs being reset by PLTRST# or Sx entry.
Hence, as per GPIO BIOS Writers Guide (BWG) it's recommended to change the Pad Reset
Configuration for lock GPP as `Power Good` so that pad configuration and lock bit are
always in sync and can be reset at the same time.
## Soft Straps
Soft straps, that can be configured by the vendor in the Intel Flash Image Tool

10
Documentation/index.md
View File

@@ -168,14 +168,8 @@ Contents:
* [Getting Started](getting_started/index.md)
* [Tutorial](tutorial/index.md)
* [Coding Style](contributing/coding_style.md)
* [Project Ideas](contributing/project_ideas.md)
* [Documentation Ideas](contributing/documentation_ideas.md)
* [Code of Conduct](community/code_of_conduct.md)
* [Language style](community/language_style.md)
* [Community forums](community/forums.md)
* [Project services](community/services.md)
* [coreboot at conferences](community/conferences.md)
* [Contributing](contributing/index.md)
* [Community](community/index.md)
* [Payloads](payloads.md)
* [Distributions](distributions.md)
* [Technotes](technotes/index.md)

177
Documentation/mainboard/acer/g43t-am3.md Normal file
View File

@@ -0,0 +1,177 @@
# Acer G43T-AM3
The Acer G43T-AM3 is a microATX-sized desktop board. It was used for the
Acer models Aspire M3800, Aspire M5800 and possibly more.
## Technology
```eval_rst
+------------------+--------------------------------------------------+
| Northbridge | Intel G43 (called x4x in coreboot code) |
+------------------+--------------------------------------------------+
| Southbridge | Intel ICH10R (called i82801jx in coreboot code) |
+------------------+--------------------------------------------------+
| CPU socket | LGA 775 |
+------------------+--------------------------------------------------+
| RAM | 4 x DDR3-1066 |
+------------------+--------------------------------------------------+
| SuperIO | ITE IT8720F |
+------------------+--------------------------------------------------+
| Audio | Realtek ALC888S |
+------------------+--------------------------------------------------+
| Network | Intel 82567V-2 Gigabit Ethernet |
+------------------+--------------------------------------------------+
```
There is no serial port. Serial console output is possible by soldering
to a point at the corresponding Super I/O pin and patching the
mainboard-specific code accordingly.
## Status
### Working
Tests were done with SeaBIOS 1.14.0 and slackware64-live from 2019-07-12
(linux-4.19.50).
+ Intel Core 2 processors at up to FSB 1333
+ All four DIMM slots at 1066 MHz (tested 2x2GB + 2x4GB)
+ Integrated graphics (libgfxinit)
+ HDMI and VGA ports
+ Both PCI slots
+ Both PCI-e slots
+ USB (8 internal, 4 external)
+ All six SATA ports
+ Onboard Ethernet
+ Onboard sound card with output on the rear stereo connector
+ PS/2 mouse and keyboard
+ With SeaBIOS, use CONFIG_SEABIOS_PS2_TIMEOUT, tested: 500
+ With FILO it works without further settings
+ Temperature readings from the Super I/O (including the CPU temperature
via PECI)
+ Super I/O EC automatic fan control
+ S3 suspend/resume
+ Poweroff
### Not working
+ DDR3 memory with 512Mx8 chips (G43 limitation)
+ 4x4GB of DDR3 memory (works, but showed a single bit error within one
pass of Memtest86+ 5.01)
+ Super I/O voltage reading conversions
### Untested
+ Other audio jacks or the front panel header
+ S/PDIF output
+ On-board Firewire
+ Wake-on-LAN
## Flashing coreboot
```eval_rst
+-------------------+---------------------+
| Type | Value |
+===================+=====================+
| Socketed flash | No |
+-------------------+---------------------+
| Model | Macronix MX25L1605D |
+-------------------+---------------------+
| Size | 2 MiB |
+-------------------+---------------------+
| Package | 8-Pin SOP |
+-------------------+---------------------+
| Write protection | No |
+-------------------+---------------------+
| Dual BIOS feature | No |
+-------------------+---------------------+
| Internal flashing | Yes |
+-------------------+---------------------+
```
The flash is divided into the following regions, as obtained with
`ifdtool -f rom.layout backup.rom`:
```
00000000:00001fff fd
00100000:001fffff bios
00006000:000fffff me
00002000:00005fff gbe
```
In general, flashing is possible internally and from an external header. It
might be necessary to specify the chip type; `MX25L1605D/MX25L1608D/MX25L1673E`
is the correct one, not `MX25L1605`.
### Internal flashing
Internal access to the flash chip is unrestricted. When installing coreboot,
only the BIOS region should be updated by passing the `--ifd` and `-i bios`
parameters to flashrom. A full backup is advisable.
Here is an example:
```
$ sudo flashrom \
-p internal \
-c "MX25L1605D/MX25L1608D/MX25L1673E" \
-r backup.rom
$ sudo flashrom \
-p internal \
-c "MX25L1605D/MX25L1608D/MX25L1673E" \
--ifd -i bios \
-w coreboot.rom
```
```eval_rst
In addition to the information here, please see the
:doc:`../../flash_tutorial/index`.
```
### External flashing
The SPI flash chip on this board can be flashed externally through the
SPI_ROM1 header while the board is off and disconnected from power. There
seems to be a diode that prevents the external programmer from powering the
whole board.
The signal assigment on the header is identical to the pinout of the flash
chip. The pinout diagram below is valid when the PCI slots are on the left
and the CPU is on the right. Note that HOLD# and WP# must be pulled high
(to VCC) to be able to flash the chip.
+---+---+
SPI_CSn <- | x | x | -> VCC
+---+---+
SPI_MISO <- | x | x | -> HOLDn
+---+---+
WPn <- | x | x | -> SPI_CLK
+---+---+
GND <- | x | x | -> SPI_MOSI
+---+---+
## Intel Management Engine
The Intel Management Engine (ME) can be disabled by setting the ME_DISABLE
jumper on the board. It pulls GPIO33 on the ICH10 low, causing the "Flash
Descriptor Security Override Strap" to be set. This disables the ME and also
disables any read/write restrictions to the flash chip that may be set in the
Intel Flash Descriptor (IFD) (none on this board). Note that changing this
jumper only comes into effect when starting the board from a shutdown or
suspend state, not during normal operation.
To completely remove the ME blob from the flash image and to decrease the size
of the ME region, thus increasing the size of the BIOS region, `me_cleaner` can
be used with the `-t`, `-r` and `-S` options.
## Fan control
There are two fan connectors that can be controlled individually. CPU_FAN
can only control a fan by a PWM signal and SYS_FAN only by voltage. See
the mainboard's `devicetree.cb` file for how coreboot configures the Super
I/O to control the fans.
## Variants
Various similar mainboards exist, like the Acer Q45T-AM. During a discussion
in #coreboot on IRC, ECS was suspected to be the original designer of this
series of mainboards. They have similar models such as the ECS G43T-WM.

174
Documentation/mainboard/asrock/h77pro4-m.md Normal file
View File

@@ -0,0 +1,174 @@
# ASRock H77 Pro4-M
The ASRock H77 Pro4-M is a microATX-sized desktop board for Intel Sandy
Bridge and Ivy Bridge CPUs.
## Technology
```eval_rst
+------------------+--------------------------------------------------+
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
+------------------+--------------------------------------------------+
| Southbridge | Intel H77 (bd82x6x) |
+------------------+--------------------------------------------------+
| CPU socket | LGA 1155 |
+------------------+--------------------------------------------------+
| RAM | 4 x DDR3-1600 |
+------------------+--------------------------------------------------+
| Super I/O | Nuvoton NCT6776 |
+------------------+--------------------------------------------------+
| Audio | Realtek ALC892 |
+------------------+--------------------------------------------------+
| Network | Realtek RTL8111E |
+------------------+--------------------------------------------------+
| Serial | Internal header (RS-232) |
+------------------+--------------------------------------------------+
```
## Status
Tests were done with SeaBIOS 1.14.0 and slackware64-live from 2019-07-12
(linux-4.19.50).
### Working
- Sandy Bridge and Ivy Bridge CPUs (tested: i5-2500, Pentium G2120)
- Native RAM initialization with four DIMMs
- PS/2 combined port (mouse or keyboard)
- Integrated GPU by libgfxinit on all monitor ports (DVI-D, HDMI, D-Sub)
- PCIe graphics in the PEG slot
- All three additional PCIe slots
- All rear and internal USB2 ports
- All rear and internal USB3 ports
- All six SATA ports from the PCH (two 6 Gb/s, four 3 Gb/s)
- All two SATA ports from the ASM1061 PCIe-to-SATA bridge (6 Gb/s)
- Rear eSATA connector (multiplexed with one ASM1061 port)
- Gigabit Ethernet
- Console output on the serial port
- SeaBIOS 1.14.0 and 1.15.0 to boot Windows 10 (needs VGA BIOS) and Linux via
extlinux
- Internal flashing with flashrom-1.2, see
[Internal Programming](#internal-programming)
- External flashing with flashrom-1.2 and a Raspberry Pi 1
- S3 suspend/resume from either Linux or Windows 10
- Poweroff
### Not working
- Booting from the two SATA ports provided by the ASM1061
- Automatic fan control with the NCT6776D Super I/O
### Untested
- EHCI debug
- S/PDIF audio
- Other audio jacks than the green one, and the front panel header
- Parallel port
- Infrared/CIR
- Wakeup from anything but the power button
## Flashing coreboot
```eval_rst
+---------------------+------------+
| Type | Value |
+=====================+============+
| Socketed flash | yes |
+---------------------+------------+
| Model | W25Q64.V |
+---------------------+------------+
| Size | 8 MiB |
+---------------------+------------+
| Package | DIP-8 |
+---------------------+------------+
| Write protection | no |
+---------------------+------------+
| Dual BIOS feature | no |
+---------------------+------------+
| Internal flashing | yes |
+---------------------+------------+
```
The flash is divided into the following regions, as obtained with
`ifdtool -f rom.layout backup.rom`:
```
00000000:00000fff fd
00200000:007fffff bios
00001000:001fffff me
```
### Internal programming
The main SPI flash can be accessed using flashrom. By default, only
the BIOS region of the flash is writable. If you wish to change any
other region (Management Engine or flash descriptor), then an external
programmer is required.
The following command may be used to flash coreboot:
```
$ sudo flashrom --noverify-all --ifd -i bios -p internal -w coreboot.rom
```
The use of `--noverify-all` is required since the Management Engine
region is not readable even by the host.
```eval_rst
In addition to the information here, please see the
:doc:`../../flash_tutorial/index`.
```
## Hardware monitoring and fan control
There are two fan headers for the CPU cooler, CPU_FAN1 and CPU_FAN2. They share
a single fan tachometer input on the Super I/O while some dedicated logic
selects which one is allowed to reach it. Two GPIO pins on the Super I/O are
used to control that logic. The firmware has to set them; coreboot selects
CPU_FAN1 by default, but the user can change that setting if it was built with
CONFIG_USE_OPTION_TABLE:
```
$ sudo nvramtool -e cpu_fan_header
[..]
$ sudo nvramtool -w cpu_fan_header=CPU_FAN2
$ sudo nvramtool -w cpu_fan_header=None
$ sudo nvramtool -w cpu_fan_header=Both
```
The setting will take effect after a reboot. Selecting and connecting both fan
headers is possible but the Super I/O will report wrong fan speeds.
Currently there is no automatic, OS-independent fan control, but a software
like `fancontrol` from the lm-sensors package can be used instead.
## Serial port header
Serial port 1, provided by the Super I/O, is exposed on a pin header. The
RS-232 signals are assigned to the header so that its pin numbers map directly
to the pin numbers of a DE-9 connector. If your serial port doesn't seem to
work, check if your bracket expects a different assignment. Also don't try to
connect it directly to a device that operates at TTL levels - it would need a
level converter like a MAX232.
Here is a top view of the serial port header found on this board:
+---+---+
N/C | | 9 | RI -> pin 9
+---+---+
Pin 8 <- CTS | 8 | 7 | RTS -> pin 7
+---+---+
Pin 6 <- DSR | 6 | 5 | GND -> pin 5
+---+---+
Pin 4 <- DTR | 4 | 3 | TxD -> pin 3
+---+---+
Pin 2 <- RxD | 2 | 1 | DCD -> pin 1
+---+---+
## eSATA
The eSATA port on the rear I/O panel and the internal connector SATA3_A1 share
the same controller port on the ASM1061. Attaching an eSATA drive causes a
multiplexer chip to disconnect the internal port from the SATA controller and
connect the eSATA port instead. This can be seen on GP23 of the Super I/O
GPIOs: it is '0' when something is connected to the eSATA port and '1'
otherwise.

52
Documentation/mainboard/emulation/qemu-power9.md Normal file
View File

@@ -0,0 +1,52 @@
# QEMU PPC64 emulator
This page describes how to build and run coreboot for QEMU/PPC64.
## Building coreboot
```bash
make defconfig KBUILD_DEFCONFIG=configs/config.emulation_qemu_power9
make
```
This builds coreboot with no payload.
## Payloads
You can configure ELF or `skiboot` payload via `make menuconfig`. In either case
you might need to adjust "ROM chip size" and make it large enough to accommodate
the payload (see how much space it needs in the error you get if it doesn't
fit).
## Running coreboot in QEMU
```bash
qemu-system-ppc64 -M powernv,hb-mode=on \
-cpu power9 \
-bios build/coreboot.rom \
-drive file=build/coreboot.rom,if=mtd \
-serial stdio \
-display none
```
- The default CPU in QEMU for AArch64 is a 604. You specify a suitable
PowerPC CPU via `-cpu power9`.
- By default Hostboot mode is off and needs to be turned on to run coreboot
as a firmware rather than like an OS.
- `-bios` specifies initial program (bootloader should suffice, but whole image
works fine too).
- `-drive` specifies image for emulated flash device.
## Running with a kernel
Loading `skiboot` (built automatically by coreboot or otherwise) allows
specifying kernel and root file system to be run.
```bash
qemu-system-ppc64 -M powernv,hb-mode=on \
-cpu power9 \
-bios build/coreboot.rom \
-drive file=build/coreboot.rom,if=mtd \
-serial stdio \
-display none \
-kernel zImage \
-initrd initrd.cpio.xz
```
- Specify path to your kernel via `-kernel`.
- Specify path to your rootfs via `-initrd`.

5
Documentation/mainboard/facebook/fbg1701.md
View File

@@ -5,10 +5,7 @@ This page describes how to run coreboot on the Facebook FBG1701.
FBG1701 are assembled with different onboard memory modules:
Rev 1.0 Onboard Samsung K4B8G1646D-MYKO memory
Rev 1.1 and 1.2 Onboard Micron MT41K512M16HA-125A memory
Rev 1.3 Onboard Kingston B5116ECMDXGGB memory
Use make menuconfig to configure `onboard memory manufacturer Samsung` in
Mainboard menu.
Rev 1.3 and 1.4 Onboard Kingston B5116ECMDXGGB memory
## Required blobs

9
Documentation/mainboard/index.md
View File

@@ -6,11 +6,16 @@ This section contains documentation about coreboot on specific mainboards.
- [X210](51nb/x210.md)
## Acer
- [G43T-AM3](acer/g43t-am3.md)
## AMD
- [padmelon](amd/padmelon/padmelon.md)
## ASRock
- [H77 Pro4-M](asrock/h77pro4-m.md)
- [H81M-HDS](asrock/h81m-hds.md)
- [H110M-DVS](asrock/h110m-dvs.md)
@@ -172,6 +177,10 @@ The boards in this section are not real mainboards, but emulators.
- [SiFive HiFive Unleashed](sifive/hifive-unleashed.md)
## Star Labs Systems
- [StarBook Mk V](starlabs/starbook_tgl.md)
## Supermicro
- [X10SLM+-F](supermicro/x10slm-f.md)

16
Documentation/mainboard/ocp/deltalake.md
View File

@@ -7,7 +7,16 @@ Delta Lake server platform.
OCP Delta Lake server platform is a component of multi-host server system
Yosemite-V3. Both [Delta Lake server design spec] and [Yosemite-V3 design
spec] were contributed to [OCP].
spec] were [OCP] accepted.
On the other hand, Wiwynn's Yosemite-V3 system and Delta Lake server product
along with its OSF implementation, which is based on FSP/coreboot/LinuxBoot
stack, was [OCP] accepted; For details, check:
- [The OCP blog]
- [The Wiwynn Press Release]
- [The Wiwynn's Yosemite-V3 product in OCP market place]
Wiwynn and 9Elements formed a partnership to offer the Wiwynn's Yosemite-V3
product and OSF for it.
Delta Lake server is a single socket Cooper Lake Scalable Processor (CPX-SP) server.
Intel Cooper Lake Scalable Processor was launched in Q2 2020.
@@ -15,7 +24,7 @@ Intel Cooper Lake Scalable Processor was launched in Q2 2020.
Yosemite-V3 has multiple configurations. Depending on configurations, it may
host up to 4 Delta Lake servers (blades) in one sled.
The Yosemite-V3 system is in mass production. Facebook, Intel and partners
The Yosemite-V3 system is in mass production. Meta, Intel and partners
jointly develop Open System Firmware (OSF) solution on Delta Lake as an alternative
solution. The OSF solution is based on FSP/coreboot/LinuxBoot stack. The
OSF solution reached production quality for some use cases in July, 2021.
@@ -187,6 +196,9 @@ and [u-root] as initramfs.
[OCP]: https://www.opencompute.org
[Delta Lake server design spec]: https://www.opencompute.org/documents/delta-lake-1s-server-design-specification-1v05-pdf
[Yosemite-V3 design spec]: https://www.opencompute.org/documents/ocp-yosemite-v3-platform-design-specification-1v16-pdf
[The OCP blog]: https://www.opencompute.org/blog/open-system-firmware-for-ocp-server-deltalake-is-published
[The Wiwynn Press Release]: https://www.prnewswire.com/news-releases/wiwynn-successfully-implemented-open-system-firmware-on-its-ocp-yosemite-v3-server-301417374.html?tc=eml_cleartime
[The Wiwynn's Yosemite-V3 product in OCP market place]: https://www.opencompute.org/products/423/wiwynn-yosemite-v3-server
[osf-builder]: https://github.com/facebookincubator/osf-builder
[OCP virtual summit 2020]: https://www.opencompute.org/summit/virtual-summit/schedule
[flashrom]: https://flashrom.org/Flashrom

BIN
Documentation/mainboard/starlabs/BiosLock.jpg Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 61 KiB

BIN
Documentation/mainboard/starlabs/SwitchBranch.png Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 25 KiB

BIN
Documentation/mainboard/starlabs/fwupdVersion.png Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 28 KiB

154
Documentation/mainboard/starlabs/starbook_tgl.md Normal file
View File

@@ -0,0 +1,154 @@
# StarBook Mk V
## Specs
- CPU (full processor specs available at https://ark.intel.com)
- Intel i7-1165G7 (Tiger Lake)
- Intel i3-1110G4 (Tiger Lake)
- EC
- ITE IT5570E
- Backlit Keyboard, with standard PS/2 keycodes and SCI hotkeys
- Battery
- Charger, using AC adapter or USB-C PD
- Suspend / resume
- GPU
- Intel® Iris® Xe Graphics
- GOP driver is recommended, VBT is provided
- eDP 14-inch 1920x1080 LCD
- HDMI video
- USB-C DisplayPort video
- Memory
- 2 x DDR4 SODIMM
- Networking
- AX201 2230 WiFi / Bluetooth
- Sound
- Realtek ALC256
- Internal speakers
- Internal microphone
- Combined headphone / microphone 3.5-mm jack
- HDMI audio
- USB-C DisplayPort audio
- Storage
- M.2 PCIe SSD
- RTS5129 MicroSD card reader
- USB
- 1280x720 CCD camera
- Thunderbolt 4.0 (left)
- USB 3.1 Gen 2 Type-A (left)
- USB 3.1 Gen 1 Type-A (right)
- USB 2.0 Type-A (right)
## Building coreboot
### Preliminaries
Prior to building coreboot the following files are required:
* Intel Flash Descriptor file (descriptor.bin)
* Intel Management Engine firmware (me.bin)
* ITE Embedded Controller firmware (ec.bin)
The files listed below are optional:
- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
### Build
The following commands will build a working image:
```bash
make distclean
make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_starbook_tgl
make
```
## Flashing coreboot
```eval_rst
+---------------------+------------+
| Type | Value |
+=====================+============+
| Socketed flash | no |
+---------------------+------------+
| Vendor | Winbond |
+---------------------+------------+
| Model | 25Q128JVSQ |
+---------------------+------------+
| Size | 16 MiB |
+---------------------+------------+
| Package | SOIC-8 |
+---------------------+------------+
| Internal flashing | yes |
+---------------------+------------+
| External flashing | yes |
+---------------------+------------+
#### **Requirements:**
* fwupd version 1.5.6 or later
* The battery must be charged to at least 30%
* The charger must be connected (either USB-C or DC Jack)
* BIOS Lock must be disabled
* Supported Linux distribution (Ubuntu 20.04 +, Linux Mint 20.1 + elementaryOS 6 +, Manjaro 21+)
**fwupd 1.5.6 or later**
To check the version of **fwupd** you have installed, open a terminal window and enter the below command:
```
fwupdmgr --version
```
This will show the version number. **1.5.6** or greater will work.
![fwupd version](fwupdVersion.png)
On Ubuntu 20.04, Ubuntu 20.10, Linux Mint 20.1 and elementaryOS 6, fwupd 1.5.6 can be installed from our PPA with the below terminal commands:
```
sudo add-apt-repository ppa:starlabs/ppa
sudo apt update
sudo apt install fwupd
```
On Manjaro:
```
sudo pacman -Sy fwupd-git flashrom-starlabs
```
Instructions for other distributions will be added once fwupd 1.5.6 is available. If you are not using one of the distributions listed above, it is possible to install coreboot using a Live USB.
**Disable BIOS Lock**
BIOS Lock must be disabled when switching from the standard AMI (American Megatrends Inc.) firmware to coreboot. To disable BIOS Lock:
1\. Start with your LabTop turned off\. Turn it on whilst holding the **F2** key to access the BIOS settings.
2\. When the BIOS settings load, use the arrow keys to navigate to the **Advanced** tab\. Here you will see **BIOS Lock**\.
3\. Press `Enter` to change this setting from **Enabled** to **Disabled**
![Disable BIOS Lock](BiosLock.jpg)
4\. Next, press the `F10` key to **Save & Exit** and then `Enter` to confirm.
#### **Switching Branch**
Switching branch refers to changing from AMI firmware to coreboot, or vice versa.
First, check for new firmware files with the below terminal command:
```
fwupdmgr refresh --force
```
Then, to change branch, enter the below terminal command:
```
fwupdmgr switch-branch
```
You can then select which branch you would like to use, by typing in the corresponding number:
![Switch Branch](SwitchBranch.png)
You will be prompted to confirm, press `y` to continue or `n` to cancel.
Once the switch has been completed, you will be prompted to restart.
The next reboot can take up to **5 minutes,** do not interrupt this process or disconnect the charger. Once the reboot is complete, that's it - you'll continue to receive updates for whichever branch you are using.
You can switch branch at any time.

2
Documentation/releases/coreboot-4.14-relnotes.md
View File

@@ -142,7 +142,7 @@ primarily to serve the needs of the server market.
coreboot support for Xeon-SP is in src/soc/intel/xeon_sp directory.
This release has support for SkyLake-SP (SKX-SP) which is the 2nd
generation, and for CooperLake-SP (CPX-SP) which is the 3rd generation
generation, and for Cooper Lake-SP (CPX-SP) which is the 3rd generation
or the latest generation [2] on market.
With this release, the codebase for multiple generations of Xeon-SP

22
Documentation/releases/coreboot-4.15-relnotes.md
View File

@@ -1,18 +1,22 @@
Upcoming release - coreboot 4.15
coreboot 4.15
================================
The 4.15 release is planned for November 1st, 2021.
coreboot 4.15 was released on November 5th, 2021.
Since 4.14 there have been more than 2448 new commits by more than 219 developers.
Since 4.14 there have been more than 2597 new commits by more than 219 developers.
Of these, over 73 contributed to coreboot for the first time.
Welcome to the project!
Thank you to all the developers who continue to make coreboot the
great open source firmware project that it is.
Important Announcement
----------------------
We are going to be changing the cadence from every 6 months, to every 3 months.
That means the 4.16 release will be coming in February, 2022.
New mainboards
--------------
* Asus p8h61-m_pro_cm6630
@@ -23,11 +27,19 @@ New mainboards
* Siemens mc_ehl
* SuperMicro x9sae
* System76 addw1
* System76 addw2
* System76 bonw14
* System76 darp6
* System76 darp7
* System76 galp2
* System76 galp3
* System76 galp3-b
* System76 galp4
* System76 galp5
* System76 gaze14
* System76 lemp10
* System76 oryp7
* System76 oryp8
Removed mainboards
------------------

342
Documentation/releases/coreboot-4.16-relnotes.md
View File

@@ -1,16 +1,340 @@
Upcoming release - coreboot 4.16
================================
coreboot 4.16
========================================================================
The 4.16 release is planned for May 2022.
The 4.16 release was done on February 25th, 2022.
Update this document with changes that should be in the release notes.
Since 4.15 there have been more than 1770 new commits by more than 170
developers. Of these, more than 35 contributed to coreboot for the
first time.
* Please use Markdown.
* See the past few release notes for the general format.
* The chip and board additions and removals will be updated right
before the release, so those do not need to be added.
Welcome to the project!
Thank you to all the developers who continue to make coreboot the
great open source firmware project that it is.
New mainboards:
---------------
* Acer Aspire VN7-572G
* AMD Chausie
* ASROCK H77 Pro4-M
* ASUS P8Z77-M
* Emulation QEMU power9
* Google Agah
* Google Anahera4ES
* Google Banshee
* Google Beadrix
* Google Brya4ES
* Google Crota
* Google Dojo
* Google Gimble4ES
* Google Herobrine_Rev0
* Google Kingler
* Google Kinox
* Google Krabby
* Google Moli
* Google Nereid
* Google Nivviks
* Google Primus4ES
* Google Redrix4ES
* Google Skyrim
* Google Taeko4ES
* Google Taniks
* Google Vell
* Google Volmar
* Intel Alderlake-N RVP
* Prodrive Atlas
* Star Labs Star Labs StarBook Mk V (i3-1115G4 and i7-1165G7)
* System76 gaze16 3050
* System76 gaze16 3060
* System76 gaze16 3060-b
Removed mainboards:
-------------------
* Google -> Corsola
* Google -> Nasher
* Google -> Stryke
Added processors:
-----------------
* src/cpu/power9
* src/soc/amd/sabrina
Submodule Updates
-----------------
* /3rdparty/amd_blobs (6 commits)
* /3rdparty/arm-trusted-firmware (965 commits)
* /3rdparty/blobs (30 commits)
* /3rdparty/chromeec (2212 commits)
* /3rdparty/intel-microcode (1 commits)
* /3rdparty/qc_blobs (13 commits)
* /3rdparty/vboot (44 commits)
Plans to move platform support to a branch:
-------------------------------------------
After the 4.18 release in November 2022, we plan to move support for any
boards still requiring RESOURCE_ALLOCATOR_V3 to the 4.18 branch. V4 was
introduced more than a year ago and with minor changes most platforms
were able to work just fine with it. A major difference is that V3 uses
just one continuous region below 4G to allocate all PCI memory BAR's. V4
uses all available space below 4G and if asked to, also above 4G too.
This makes it important that SoC code properly reports all fixed
resources.
Currently only AGESA platforms have issues with it. On Gerrit both
attempts to fix AMD AGESA codebases to use V4 and compatibility modes
inside the V4 allocator have been proposed, but both efforts seem
stalled. See the (not yet merged) documentation
[CR:43603](https://review.coreboot.org/c/coreboot/+/43603) on it's
details. It looks like properly reporting all fixed resources is the
issue.
At this point, we are not specifying which platforms this will include
as there are a number of patches to fix these issues in flight.
Hopefully, all platforms will end up being migrated to the v4 resource
allocator so that none of the platforms need to be supported on the
branch.
Additionally, even if the support for the platform is moved to a branch,
it can be brought back to ToT if they're fixed to support the v4
allocator.
Plans for Code Deprecation
--------------------------
As of release 4.18 (November 2022) we plan to deprecate LEGACY_SMP_INIT.
This also includes the codepath for SMM_ASEG. This code is used to start
APs and do some feature programming on each AP, but also set up SMM.
This has largely been superseded by PARALLEL_MP, which should be able to
cover all use cases of LEGACY_SMP_INIT, with little code changes. The
reason for deprecation is that having 2 codepaths to do the virtually
the same increases maintenance burden on the community a lot, while also
being rather confusing.
A few things are lacking in PARALLEL_MP init:
- Support for !CONFIG_SMP on single core systems. It's likely easy to
extend PARALLEL_MP or write some code that just does CPU detection on
the BSP CPU.
- Support SMM in the legacy ASEG (0xa0000 - 0xb0000) region. A POC
showed that it's not that hard to do with PARALLEL_MP
https://review.coreboot.org/c/coreboot/+/58700
No platforms in the tree have any hardware limitations that would block
migrating to PARALLEL_MP / a simple !CONFIG_SMP codebase.
Significant changes
-------------------
This is, of course, not a complete list of all changes in the 4.16
coreboot release, but a sampling of some of the more interesting and
significant changes.
### Add significant changes here
### Option to disable Intel Management Engine
Disable the Intel (Converged Security) Management Engine ((CS)ME) via
HECI based on Intel Core processors from Skylake to Alder Lake. State is
set based on a CMOS value of `me_state`. A value of `0` will result in a
(CS)ME state of `0` (working) and value of `1` will result in a (CS)ME
state of `3` (disabled). For an example CMOS layout and more info, see
[cse.c](../../src/soc/intel/common/block/cse/cse.c).
### Add [AMD] apcb_v3_edit tool
apcb_v3_edit.py tool edits APCB V3 binaries. Specifically it will inject
up to 16 SPDs into an existing APCB. The APCB must have a magic number
at the top of each SPD slot.
### Allow enable/disable ME via CMOS
Add .enable method that will set the CSME state. The state is based on
the new CMOS option me_state, with values of 0 and 1. The method is very
stable when switching between different firmware platforms.
This method should not be used in combination with USE_ME_CLEANER.
State 1 will result in:
ME: Current Working State : 4
ME: Current Operation State : 1
ME: Current Operation Mode : 3
ME: Error Code : 2
State 0 will result in:
ME: Current Working State : 5
ME: Current Operation State : 1
ME: Current Operation Mode : 0
ME: Error Code : 0
### Move LAPIC configuration to MP init
Implementation for setup_lapic() did two things -- call enable_lapic()
and virtual_wire_mode_init().
In PARALLEL_MP case enable_lapic() was redundant as it was already
executed prior to initialize_cpu() call. For the !PARALLEL_MP case
enable_lapic() is added to AP CPUs.
### Add ANSI escape sequences for highlighting
Add ANSI escape sequences to highlight a log line based on its loglevel
to the output of "interactive" consoles that are meant to be displayed
on a terminal (e.g. UART). This should help make errors and warnings
stand out better among the usual spew of debug messages. For users whose
terminal or use case doesn't support these sequences for some reason (or
who simply don't like them), they can be disabled with a Kconfig.
While ANSI escape sequences can be used to add color, minicom (the
presumably most common terminal emulator for UART endpoints?) doesn't
support color output unless explicitly enabled (via -c command line
flag), and other terminal emulators may have similar restrictions, so in
an effort to make this as widely useful by default as possible I have
chosen not to use color codes and implement this highlighting via
bolding, underlining and inverting alone (which seem to go through in
all cases). If desired, support for separate color highlighting could be
added via Kconfig later.
### Add cbmem_dump_console
This function is similar to cbmem_dump_console_to_uart except it uses
the normally configured consoles. A console_paused flag was added to
prevent the cbmem console from writing to itself.
### Add coreboot-configurator
A simple GUI to change CMOS settings in coreboot's CBFS, via the
nvramtool utility. Testing on Debian, Ubuntu and Manjaro with coreboot
4.14+, but should work with any distribution or coreboot release that
has an option table. For more info, please check the
[README](https://web.archive.org/web/20220225194308/https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/util/coreboot-configurator/README.md).
### Update live ISO configs to NixOS 21.11
Update configs so that they work with NixOS 21.11. Drop `iasl` package
since it was replaced with `acpica-tools`.
### Move to U-Boot v2021.10
Move to building the latest U-Boot.
### Support systems with >128 cores
Each time the spinlock is acquired a byte is decreased and then the
sign of the byte is checked. If there are more than 128 cores the sign
check will overflow. An easy fix is to increase the word size of the
spinlock acquiring and releasing.
### Add [samsung] sx9360 [proximity sensor] driver
Add driver for setting up Semtech sx9360 SAR sensor.
The driver is based on sx9310.c. The core of the driver is the same, but
the bindings are slightly different.
Registers are documented [in the kernel tree:](https://web.archive.org/web/20220225182803/https://patchwork.kernel.org/project/linux-iio/patch/20211213024057.3824985-4-gwendal@chromium.org/)
Documentation/devicetree/bindings/iio/proximity/semtech,sx9360.yaml
### Add driver for Genesys Logic [SD Controller] GL9750
The device is a PCIe Gen1 to SD 3.0 card reader controller to be
used in the Chromebook. The datasheet name is GL9750S and the revision
is 01.
The patch disables ASPM L0s.
### Add support for Realtek RT8125
The Realtek RT8168 and RT8125 have a similar programming interface,
therefore add the PCI device ID for the RT8125 into driver for support.
### Add Fibocom 5G WWAN ACPI support
Support PXSX._RST and PXSX.MRST._RST for warm and cold reset.
PXSX._RST is invoked on driver removal.
build dependency:
soc/intel/common/block/pcie/rtd3
This driver will use the rtd3 methods for the same parent in the device
tree. The rtd3 chip needs to be added on the same root port in the
devicetree separately.
### Fix bug in vr_config
The `cpu_get_power_max()` function returns the TDP in milliwatts, but
the vr_config code interprets the value in watts. Divide the value by
1000 to fix this.
This also fixes an integer overflow when `cpu_get_power_max()` returns
a value greater than 65535 (UINT16_MAX).
### Make mixed topology work
When using a mixed memory topology with DDR4, it's not possible to boot
when no DIMMs are installed, even though memory-down is available. This
happens because the DIMM SPD length defaults to 256 when no DIMM SPD is
available. Relax the length check when no DIMMs are present to overcome
this problem.
### Add FSP 2.3 support
FSP 2.3 specification introduces following changes:
1. FSP_INFO_HEADER changes
Updated SpecVersion from 0x22 to 0x23
Updated HeaderRevision from 5 to 6
Added ExtendedImageRevision
FSP_INFO_HEADER length changed to 0x50
2. Added FSP_NON_VOLATILE_STORAGE_HOB2
Following changes are implemented in the patch to support FSP 2.3:
- Add Kconfig option
- Update FSP build binary version info based on ExtendedImageRevision
field in header
- New NV HOB related changes will be pushed as part of another patch
### Join hash calculation for verification and measurement
This patch moves the CBFS file measurement when CONFIG_TPM_MEASURED_BOOT
is enabled from the lookup step into the code where a file is actually
loaded or mapped from flash. This has the advantage that CBFS routines
which just look up a file to inspect its metadata (e.g. cbfs_get_size())
do not cause the file to be measured twice. It also removes the existing
inefficiency that files are loaded twice when measurement is enabled
(once to measure and then again when they are used). When CBFS
verification is enabled and uses the same hash algorithm as the TPM, we
are even able to only hash the file a single time and use the result for
both purposes.
### Skip FSP Notify APIs
Alder Lake SoC deselects Kconfigs as below:
- USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
- USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
to skip FSP notify APIs (Ready to boot and End of Firmware) and make
use of native coreboot driver to perform SoC recommended operations
prior booting to payload/OS.
Additionally, created a helper function `heci_finalize()` to keep HECI
related operations separated for easy guarding again config.
TODO: coreboot native implementation to skip FSP notify phase API (post
pci enumeration) is still WIP.
### Add support for PCIe Resizable BARs
Section 7.8.6 of the PCIe spec (rev 4) indicates that some devices can
indicates support for "Resizable BARs" via a PCIe extended capability.
When support this capability is indicated by the device, the size of
each BAR is determined in a different way than the normal "moving
bits" method. Instead, a pair of capability and control registers is
allocated in config space for each BAR, which can be used to both
indicate the different sizes the device is capable of supporting for
the BAR (powers-of-2 number of bits from 20 [1 MiB] to 63 [8 EiB]), and
to also inform the device of the size that the allocator actually
reserved for the MMIO range.
This patch adds a Kconfig for a mainboard to select if it knows that it
will have a device that requires this support during PCI enumeration.
If so, there is a corresponding Kconfig to indicate the maximum number
of bits of address space to hand out to devices this way (again, limited
by what devices can support and each individual system may want to
support, but just like above, this number can range from 20 to 63) If
the device can support more bits than this Kconfig, the resource request
is truncated to the number indicated by this Kconfig.

19
Documentation/releases/coreboot-4.17-relnotes.md Normal file
View File

@@ -0,0 +1,19 @@
Upcoming release - coreboot 4.17
================================
The 4.17 release is planned for May, 2022.
We are continuing the quarterly release cadence in order to enable others to
release quarterly on a fresher version of coreboot.
Update this document with changes that should be in the release notes.
* Please use Markdown.
* See the past few release notes for the general format.
* The chip and board additions and removals will be updated right
before the release, so those do not need to be added.
Significant changes
-------------------
### Add significant changes here

8
Documentation/releases/index.md
View File

@@ -16,6 +16,7 @@ Release notes for previous releases
* [4.13 - November 2020](coreboot-4.13-relnotes.md)
* [4.14 - May 2021](coreboot-4.14-relnotes.md)
* [4.15 - November 2021](coreboot-4.15-relnotes.md)
* [4.16 - Feb 2022](coreboot-4.16-relnotes.md)
The checklist contains instructions to ensure that a release covers all
important things and provides a reliable format for tarballs, branch
@@ -23,8 +24,13 @@ names etc.
* [checklist](checklist.md)
For release related communications consider using a template so everything
important is taken care of.
* [templates](templates.md)
Upcoming release
----------------
Please add to the release notes as changes are added:
* [4.16 - May 2022](coreboot-4.16-relnotes.md)
* [4.17 - May 2022](coreboot-4.17-relnotes.md)

83
Documentation/releases/templates.md Normal file
View File

@@ -0,0 +1,83 @@
# Communication templates related to release management
## Deprecation notices
Deprecation notices are part of release notes to act as a warning: at some
point in the future some part of coreboot gets removed. That point must be
at least 6 months after the release of the notice and it must be right after
some release: That is, the specified release must still contain the part in
question while one git commit later it might be removed.
The usual reason is progress: Infrastructure module X has been replaced by
infrastructure module X+1. Removing X helps keep the sources manageable
and likely opens opportunities to improve the codebase even more.
Sometimes everything using some module has been converted to its successor
already and it's natural for such modules to be removed. Even then it might
be useful to add an entry to the release notes to make everybody aware of
such a change, for maintainers of incomplete boards that they might keep in
their local trees and also to give credit to the developers of that change.
However this template isn't about such cases. Sometimes the tree contains
mainboards that rely on X and can't be easily migrated to X+1, often because
no active developer has access to these mainboards, and that is where this
type of deprecation notice comes in:
A deprecation notice shall outline what is being removed, when it is planned
for removal (always directly _after_ a future release so it remains clear when
something is part of coreboot and when it isn't anymore) and which devices
would be affected at the time of writing. Since past deprecation notices have
been read as "we plan to remove mainboards A, B, and C", sparking outrage
with the devoted users of A, B, or C, some care is necessary to make clear
which parts are slated for removal and which parts are merely consequences
if no action is taken. Or put differently: It should be obvious that besides
the deprecation plan, there is a call to action to save a couple of devices
from becoming officially unsupported.
As such, consider the following template when announcing a deprecation:
### The Thing to remove
A short description of the Thing slated for removal.
A short rationale why it's being removed (e.g. new and better Thing exists
in parallel; new Thing already demonstrated to work in this many releases;
removing Thing enables this or that improvement)
Timeline: Announced here, Thing will be removed right after the release X
months out (where X >= 6)
#### Call to action
Removing Thing requires work on a number of (boards, chipsets, …) that didn't
make the switch yet. The work approximately looks like this: (e.g. pointers to
commits where a board has been successfully migrated from Thing to new Thing).
Working on migrating away from Thing involves (hardware components, coreboot
systems, …) 1, 2, and 3. It's difficult to do on the remaining devices because
...
Parts of the tree that need work to become independent of Thing.
- chipset A
- board A1
- board A2
- chipset B
- board B1
We prefer to move them along, but if we don't see any maintenance in our tree
we'll have to assume that there's no more interest in these platforms. As a
consequence these devices either have to work without Thing by the removal
date or they will be removed together with Thing. (side note: these removals
aren't the law, so if there's work in progress to move boards off X and a
roadmap that makes it probable to succeed, just not within the announced
deprecation timeline, we can still decide to postpone the actual removal by
one release. This needn't be put in the release notes themselves though or
it might encourage people to look for simple escape hatches.)
(If there are developers offering to write patches: )
There are developers interested in helping move these forward but they can't
test any changes for lack of equipment. If you have an affected device and
can run tests on it, please reach out to developers α, β, and γ.
(Otherwise maybe something more generic like this: )
If you want to take this on, the coreboot developer community will try to
help you: Reach out through one of our [forums](../community/forums.md).

128
Documentation/security/vboot/list_vboot.md
View File

@@ -1,6 +1,7 @@
# vboot-enabled devices
## AMD
- Chausie
- Majolica
## Clevo
@@ -29,8 +30,37 @@
- Panther (ASUS Chromebox CN60)
- Tricky (Dell Chromebox 3010)
- Zako (HP Chromebox G1)
- Agah
- Anahera
- Anahera4ES
- Brask
- Brya 0
- Brya4ES
- Felwinter
- Gimble
- Gimble4ES
- Kano
- Nivviks
- Nereid
- Primus
- Primus4ES
- Redrix
- Redrix4ES
- Taeko
- Taeko4ES
- Taniks
- Vell
- Volmar
- Banshee
- Crota
- Moli
- Kinox
- Butterfly (HP Pavilion Chromebook 14)
- Cherry
- Dojo
- Tomato
- Kingler
- Krabby
- Banon (Acer Chromebook 15 (CB3-532))
- Celes (Samsung Chromebook 3)
- Cyan (Acer Chromebook R11 (C738T))
@@ -66,60 +96,68 @@
- Nefario
- Rainier
- Guybrush
- Akemi
- Dratini
- Duffy Legacy (32MB)
- Duffy
- Faffy
- Hatch
- Jinlon
- Kaisa Legacy (32MB)
- Kaisa
- Kohaku
- Kindred
- Helios
- Mushu
- Palkia
- Nightfury
- Noibat
- Puff
- Helios_Diskswap
- Stryke
- Wyvern
- Dooly
- Nipperkin
- Dewatt
- Akemi (IdeaPad Flex 5/5i Chromebook)
- Ambassador
- Dooly
- Dratini (HP Pro c640 Chromebook)
- Duffy Legacy (32MB)
- Duffy (ASUS Chromebox 4)
- Faffy (ASUS Fanless Chromebox)
- Genesis
- Hatch
- Helios (ASUS Chromebook Flip C436FA)
- Helios_Diskswap
- Jinlon (HP Elite c1030 Chromebook)
- Kaisa Legacy (32MB)
- Kaisa (Acer Chromebox CXI4)
- Kindred (Acer Chromebook 712)
- Kohaku (Samsung Galaxy Chromebook)
- Moonbuggy
- Mushu
- Nightfury (Samsung Galaxy Chromebook 2)
- Noibat (HP Chromebox G3)
- Palkia
- Puff
- Scout
- Wyvern (CTL Chromebox CBx2)
- Herobrine
- Herobrine_Rev0
- Senor
- Piglin
- Hoglin
- Guado (ASUS Chromebox CN62)
- Jecht
- Rikku (Acer Chromebox CXI2)
- Tidus (Lenovo ThinkCentre Chromebox)
- Aleena
- Careena
- Aleena/Kasumi (Acer Chromebook 315 (CB315-2H), 311 (C721) / Spin 311 (R721T))
- Barla/Careena (HP Chromebook 11A G6/G8 EE, 14A G5/G6)
- Grunt
- Liara
- Liara (Lenovo 14e Chromebook, Chromebook S345-14)
- Nuwani
- Treeya
- Treeya (Lenovo 100e/300e Gen2 AMD)
- Kukui
- Krane
- Kodama
- Krane (Lenovo Chromebook Duet/Lenovo IdeaPad Duet Chromebook)
- Kodama (Lenovo 10e Chromebook Tablet)
- Kakadu
- Flapjack
- Katsu
- Jacuzzi
- Juniper
- Juniper (Acer Chromebook Spin 311 (CP311-3H))
- Kappa
- Damu
- Damu (ASUS Chromebook Flip CM3 (CM3200))
- Cerise
- Stern
- Willow
- Esche
- Burnet
- Esche (HP Chromebook 11MK G9 EE)
- Burnet (HP Chromebook x360 11MK G3 EE)
- Fennel
- Cozmo
- Makomo
- Munna
- Pico
- Link (Google Chromebook Pixel (2013))
- Mancomb
- Mistral
- Nyan
- Nyan Big (Acer Chromebook 13 (CB5-311))
@@ -132,7 +170,7 @@
- Atlas (Google Pixelbook Go)
- Poppy
- Nami
- Nautilus (Samsung Chromebook Plus (V2 / LTE))
- Nautilus (Samsung Chromebook Plus V2, V2 LTE)
- Nocturne (Google Pixel Slate)
- Rammus (Asus Chromebook C425, Flip C433, Flip C434)
- Soraka (HP Chromebook x2)
@@ -156,10 +194,9 @@
- Pyro (Lenovo Thinkpad (Yoga) 11e Chromebook)
- Sand (Acer Chromebook 15 CB515-1HT/1H)
- Snappy (HP Chromebook x360 11 G1 EE)
- Nasher
- Coral
- Arcada
- Sarien
- Arcada (Latitude 5300 2-in-1 Chromebook Enterprise)
- Sarien (Dell Latitude 5400 Chromebook Enterprise)
- Falco (HP Chromebook 14)
- Leon (Toshiba Chromebook)
- Peppy (Acer C720/C720P Chromebook)
@@ -177,8 +214,8 @@
- Pazquel
- Pompom
- Quackingstick
- Trogdor
- Wormdingler
- Trogdor
- Veyron_Jaq (Haier Chromebook 11)
- Veyron_Jerry (Hisense Chromebook 11)
- Veyron_Mighty (Haier Chromebook 11(edu))
@@ -187,15 +224,15 @@
- Veyron_Mickey (Asus Chromebit CS10)
- Veyron_Rialto
- Dalboz
- Vilboz
- Ezkinil
- Morphius
- Vilboz (Lenovo 100e/300e Gen3 AMD)
- Ezkinil (Acer Chromebook Spin 514)
- Morphius (Lenovo ThinkPad C13 Yoga Chromebook)
- Trembyle
- Berknip
- Woomax
- Dirinboz
- Berknip (HP Pro c645 Chromebook Enterprise)
- Woomax (ASUS Chromebook Flip CM5)
- Dirinboz (HP Chromebook 14a-nd0097nr)
- Shuboz
- Gumboz
- Gumboz (HP Chromebook x360 14a)
## HP
- Z220 SFF Workstation
@@ -203,8 +240,11 @@
## Intel
- Alderlake-P RVP
- Alderlake-P RVP with Chrome EC
- Alderlake-P RVP with Microchip EC
- Alderlake-M RVP
- Alderlake-M RVP with Chrome EC
- Alderlake-N RVP
- Alderlake-N RVP with Chrome EC
- Basking Ridge CRB
- Coffeelake U SO-DIMM DDR4 RVP
- Coffeelake H SO-DIMM DDR4 RVP11

12
Documentation/soc/intel/fsp/index.md
View File

@@ -2,6 +2,18 @@
This section contains documentation about Intel-FSP in public domain.
## Integration Guidelines
Some guiding principles when working on the glue to integrate FSP into
coreboot, e.g. on how to configure a board in devicetree when that affects
the way FSP works:
* It should be possible to replace FSP based boot with a native coreboot
implementation for a given chipset without touching the mainboard code.
* The devicetree configures coreboot and part of what coreboot does with the
information is setting some FSP UPDs. The devicetree isn't supposed to
directly configure FSP.
## Bugs
As Intel doesn't even list known bugs, they are collected here until
those are fixed. If possible a workaround is described here as well.

6
Documentation/superio/nuvoton/nct5539d.md
View File

@@ -1,9 +1,9 @@
# NCT5539D SuperIO
# NCT5539D Super I/O
The SuperIO has the ID `0xd121` and the source can be found in
The Super I/O has the ID `0xd121` and the source can be found in
`src/superio/nuvoton/nct5539d/`.
## For developers
The SuperIO generates ACPI using the
The Super I/O generates ACPI using the
[SSDT generator for generic SuperIOs](../common/ssdt.md).

33
Documentation/tutorial/part2.md
View File

@@ -12,37 +12,24 @@ select **Google OAuth2** (gerrit-oauth-provider plugin). **Note:** Your
username for the account will be the username of the account you used to
sign-in with. (ex. your Google username).
## Step 2a: Set up RSA Private/Public Key
## Step 2a: Set up SSH keys
If you prefer to use an HTTP password instead, skip to Step 2b.
For the most up-to-date instructions on how to set up SSH keys with Gerrit go to
<https://gerrit-documentation.storage.googleapis.com/Documentation/2.14.2/user-upload.html#configure_ssh>
and follow the instructions there. Then, skip to Step 3.
Additionally, that section of the Web site provides explanation on starting
an ssh-agent, which may be particularly helpful for those who anticipate
frequently uploading changes.
If you instead prefer to have review.coreboot.org specific instructions,
follow the steps below. Note that this particular section may have the
most up-to-date instructions.
If you do not have an RSA key set up on your account already (as is the case
If you do not have an SSH key set up on your account already (as is the case
with a newly created account), follow the instructions below; otherwise,
doing so could overwrite an existing key.
In the upper right corner, select your name and click on **Settings**.
Select **SSH Public Keys** on the left-hand side.
In a terminal, run `ssh-keygen` and confirm the default path `.ssh/id_rsa`.
In a terminal, run `ssh-keygen -t ed25519` and confirm the default path
`.ssh/id_ed25519`.
Make a passphrase -- remember this phrase. It will be needed whenever you use
this RSA Public Key. **Note:** You might want to use a short password, or
this public key. **Note:** You might want to use a short password, or
forego the password altogether as you will be using it very often.
Open `id_rsa.pub`, copy all contents and paste into the textbox under
"Add SSH Public Key" in the https://review.coreboot.org webpage.
Copy the content of `.ssh/id_ed25519.pub` (notice the ".pub" suffix
as you need to send the public key) into the textbox "New SSH Key" at
https://review.coreboot.org/settings/#SSHKeys and save it.
## Step 2b: Set up an HTTP Password
@@ -173,7 +160,9 @@ When you are done with your commit, run `git push` to push your commit to
coreboot.org. **Note:** To submit as a private patch, use
`git push origin HEAD:refs/for/master%private`. Submitting as a private patch
means that your commit will be on review.coreboot.org, but is only visible to
yourself and those you add as reviewers.
yourself and those you add as reviewers. This mode isn't perfect: Somebody who
knows the commit ID can still fetch the change and everything it refers (e.g.
parent commits).
This has been a quick primer on how to submit a change to Gerrit for review
using git. You may wish to review the [Gerrit code review workflow

2
Documentation/util.md
View File

@@ -12,6 +12,8 @@ settings. `Perl`
* __apcb__ - AMD PSP Control Block tools
* _apcb_edit.py_ - This tool allows patching an existing APCB
binary with specific SPDs and GPIO selection pins. `Python3`
* _apcb_v3_edit.py_ - This tool allows patching an existing APCB V3
binary with specific SPDs. `Python3`
* __archive__ - Concatenate files and create an archive `C`
* __autoport__ - Automated porting coreboot to Sandy Bridge/Ivy Bridge
platforms `Go`