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Merge 4.16

Browse Source 
Change-Id: I11db70a8e25a6656c5ec640a703e7b06d5a3672e
This commit is contained in:
Jeremy Soller
2022-03-04 07:19:45 -07:00
parent af64e5d166
commit d97e25ac13
3138 changed files with 317025 additions and 23253 deletions
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14
util/inteltool/ahci.c
View File

@@ -93,7 +93,7 @@ int print_ahci(struct pci_dev *ahci)
size_t ahci_registers_size = 0, i;
size_t ahci_cfg_registers_size = 0;
const io_register_t *ahci_cfg_registers;
size_t ahci_sir_offset = 0;
size_t ahci_sir_index_offset = 0, ahci_sir_data_offset;
size_t ahci_sir_registers_size = 0;
const io_register_t *ahci_sir_registers;
@@ -107,7 +107,7 @@ int print_ahci(struct pci_dev *ahci)
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_SATA:
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SATA:
ahci_registers_size = 0x800;
ahci_sir_offset = 0xa0;
ahci_sir_index_offset = 0xa0;
ahci_cfg_registers = sunrise_ahci_cfg_registers;
ahci_cfg_registers_size = ARRAY_SIZE(sunrise_ahci_cfg_registers);
ahci_sir_registers = sunrise_ahci_sir_registers;
@@ -117,6 +117,8 @@ int print_ahci(struct pci_dev *ahci)
ahci_registers_size = 0x400;
}
ahci_sir_data_offset = ahci_sir_index_offset + 4;
printf("\n============= AHCI Configuration Registers ==============\n\n");
for (i = 0; i < ahci_cfg_registers_size; i++) {
switch (ahci_cfg_registers[i].size) {
@@ -143,24 +145,24 @@ int print_ahci(struct pci_dev *ahci)
printf("\n============= SATA Initialization Registers ==============\n\n");
for (i = 0; i < ahci_sir_registers_size; i++) {
pci_write_byte(ahci, ahci_sir_offset, ahci_sir_registers[i].addr);
pci_write_byte(ahci, ahci_sir_index_offset, ahci_sir_registers[i].addr);
switch (ahci_sir_registers[i].size) {
case 4:
printf("0x%02x: 0x%08x (%s)\n",
ahci_sir_registers[i].addr,
pci_read_long(ahci, ahci_sir_offset),
pci_read_long(ahci, ahci_sir_data_offset),
ahci_sir_registers[i].name);
break;
case 2:
printf("0x%02x: 0x%04x (%s)\n",
ahci_sir_registers[i].addr,
pci_read_word(ahci, ahci_sir_offset),
pci_read_word(ahci, ahci_sir_data_offset),
ahci_sir_registers[i].name);
break;
case 1:
printf("0x%02x: 0x%02x (%s)\n",
ahci_sir_registers[i].addr,
pci_read_byte(ahci, ahci_sir_offset),
pci_read_byte(ahci, ahci_sir_data_offset),
ahci_sir_registers[i].name);
break;
}

21
util/inteltool/gpio.c
View File

@@ -173,7 +173,7 @@ static const io_register_t ich10_gpio_registers[] = {
{ 0x3C, 4, "RESERVED" },
{ 0x40, 4, "GPIO_USE_SEL3" },
{ 0x44, 4, "GP_IO_SEL3" },
{ 0x48, 4, "GPIO_LVL3" },
{ 0x48, 4, "GP_LVL3" },
{ 0x4c, 4, "RESERVED" },
{ 0x50, 4, "RESERVED" },
{ 0x54, 4, "RESERVED" },
@@ -227,7 +227,7 @@ static const io_register_t pch_gpio_registers[] = {
{ 0x3c, 4, "RESERVED" },
{ 0x40, 4, "GPIO_USE_SEL3" },
{ 0x44, 4, "GP_IO_SEL3" },
{ 0x48, 4, "GPIO_LVL3" },
{ 0x48, 4, "GP_LVL3" },
{ 0x4c, 4, "RESERVED" },
{ 0x50, 4, "RESERVED" },
{ 0x54, 4, "RESERVED" },
@@ -943,6 +943,7 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs)
defaults_size = ARRAY_SIZE(pp_pch_mobile_defaults);
break;
case PCI_DEVICE_ID_INTEL_ICH10:
case PCI_DEVICE_ID_INTEL_ICH10D:
case PCI_DEVICE_ID_INTEL_ICH10DO:
case PCI_DEVICE_ID_INTEL_ICH10R:
gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
@@ -1039,6 +1040,11 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs)
case PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM:
case PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_PREM:
case PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_BASE:
case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_SUPER:
case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_PREM:
case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_BASE:
case PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_SUPER:
case PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_PREM:
case PCI_DEVICE_ID_INTEL_C621:
case PCI_DEVICE_ID_INTEL_C622:
case PCI_DEVICE_ID_INTEL_C624:
@@ -1076,6 +1082,17 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs)
case PCI_DEVICE_ID_INTEL_QM370:
case PCI_DEVICE_ID_INTEL_HM370:
case PCI_DEVICE_ID_INTEL_CM246:
case PCI_DEVICE_ID_INTEL_Q570:
case PCI_DEVICE_ID_INTEL_Z590:
case PCI_DEVICE_ID_INTEL_H570:
case PCI_DEVICE_ID_INTEL_B560:
case PCI_DEVICE_ID_INTEL_H510:
case PCI_DEVICE_ID_INTEL_WM590:
case PCI_DEVICE_ID_INTEL_QM580:
case PCI_DEVICE_ID_INTEL_HM570:
case PCI_DEVICE_ID_INTEL_C252:
case PCI_DEVICE_ID_INTEL_C256:
case PCI_DEVICE_ID_INTEL_W580:
case PCI_DEVICE_ID_INTEL_ICELAKE_LP_U:
print_gpio_groups(sb);
return 0;

23
util/inteltool/gpio_groups.c
View File

@@ -17,6 +17,7 @@
#include "gpio_names/icelake.h"
#include "gpio_names/lewisburg.h"
#include "gpio_names/sunrise.h"
#include "gpio_names/tigerlake.h"
#define SBBAR_SIZE (16 * MiB)
#define PCR_PORT_SIZE (64 * KiB)
@@ -174,6 +175,28 @@ const struct gpio_community *const *get_gpio_communities(struct pci_dev *const s
*community_count = ARRAY_SIZE(icelake_pch_h_communities);
*pad_stepping = 16;
return icelake_pch_h_communities;
case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_SUPER:
case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_PREM:
case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_BASE:
case PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_SUPER:
case PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_PREM:
*community_count = ARRAY_SIZE(tigerlake_pch_lp_communities);
*pad_stepping = 16;
return tigerlake_pch_lp_communities;
case PCI_DEVICE_ID_INTEL_Q570:
case PCI_DEVICE_ID_INTEL_Z590:
case PCI_DEVICE_ID_INTEL_H570:
case PCI_DEVICE_ID_INTEL_B560:
case PCI_DEVICE_ID_INTEL_H510:
case PCI_DEVICE_ID_INTEL_WM590:
case PCI_DEVICE_ID_INTEL_QM580:
case PCI_DEVICE_ID_INTEL_HM570:
case PCI_DEVICE_ID_INTEL_C252:
case PCI_DEVICE_ID_INTEL_C256:
case PCI_DEVICE_ID_INTEL_W580:
*community_count = ARRAY_SIZE(tigerlake_pch_h_communities);
*pad_stepping = 16;
return tigerlake_pch_h_communities;
default:
return NULL;
}

1371
util/inteltool/gpio_names/tigerlake.h Normal file
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File diff suppressed because it is too large Load Diff

48
util/inteltool/inteltool.c
View File

@@ -146,9 +146,24 @@ static const struct {
"Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D (Hewitt Lake)" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SAPPHIRERAPIDS_SP,
"Xeon Scalable Processor 4th generation (Sapphire Rapids SP)" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_TGL_ID_U_2,
"11th generation (Tiger Lake UP3 family) Core Processor (Mobile)" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_TGL_ID_U_4,
"11th generation (Tiger Lake UP3 family) Core Processor (Mobile)" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_TGL_ID_Y_2,
"11th generation (Tiger Lake UP4 family) Core Processor (Mobile)" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_TGL_ID_Y_4,
"11th generation (Tiger Lake UP4 family) Core Processor (Mobile)" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_TGL_ID_H_4,
"11th generation (Tiger Lake H family) Core Processor (Mobile)" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_TGL_ID_H_6,
"11th generation (Tiger Lake H family) Core Processor (Mobile)" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_TGL_ID_H_8,
"11th generation (Tiger Lake H family) Core Processor (Mobile)" },
/* Southbridges (LPC controllers) */
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "371AB/EB/MB" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10, "ICH10" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10D, "ICH10D" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10DO, "ICH10DO" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10R, "ICH10R" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9DH, "ICH9DH" },
@@ -266,6 +281,16 @@ static const struct {
"Comet Point-LP U Premium/Cometlake" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_BASE,
"Comet Point-LP U Base/Cometlake" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERPOINT_U_SUPER,
"Tiger Point U Engineering Sample" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERPOINT_U_PREM,
"Tiger Point U Premium/Tigerlake" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERPOINT_U_BASE,
"Tiger Point U Base/Tigerlake" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_SUPER,
"Tiger Point Y Engineering Sample" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_PREM,
"Tiger Point Y Premium/Tigerlake" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H110, "H110" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H170, "H170" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z170, "Z170" },
@@ -330,6 +355,17 @@ static const struct {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H81, "H81"},
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_APL_LPC, "Apollo Lake" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_LPC, "Denverton" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H510, "H510" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H570, "H570" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z590, "Z590" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q570, "Q570" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_B560, "B560" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_W580, "W580" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C256, "C256" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C252, "C252" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM570, "HM570" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QM580, "QM580" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WM590, "WM590" },
/* Intel GPUs */
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_G35_EXPRESS,
"Intel(R) G35 Express Chipset Family" },
@@ -463,6 +499,18 @@ static const struct {
"Intel(R) Iris Plus Graphics 655" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IRIS_PLUS_G7,
"Intel(R) Iris Plus Graphics G7" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGL_GT2_UY,
"Intel(R) Iris Xe Graphics" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGL_GT2_Y,
"Intel(R) Iris Xe Graphics" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGL_GT1,
"Intel(R) UHD Graphics for 11th Gen Intel(R) Processors" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGL_GT1_2,
"Intel(R) UHD Graphics for 11th Gen Intel(R) Processors" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGL_GT2_ULT_1,
"Intel(R) UHD Graphics for 11th Gen Intel(R) Processors" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGL_GT2_ULT_2,
"Intel(R) UHD Graphics for 11th Gen Intel(R) Processors" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_GRAPHICS,
"Intel(R) UHD Graphics" },
};

33
util/inteltool/inteltool.h
View File

@@ -76,7 +76,8 @@ static inline uint32_t inl(unsigned port)
#define PCI_DEVICE_ID_INTEL_ICH9ME 0x2917
#define PCI_DEVICE_ID_INTEL_ICH10DO 0x3a14
#define PCI_DEVICE_ID_INTEL_ICH10R 0x3a16
#define PCI_DEVICE_ID_INTEL_ICH10 0x3a18
#define PCI_DEVICE_ID_INTEL_ICH10 0x3a18
#define PCI_DEVICE_ID_INTEL_ICH10D 0x3a1a
#define PCI_DEVICE_ID_INTEL_3400_DESKTOP 0x3b00
#define PCI_DEVICE_ID_INTEL_3400_MOBILE 0x3b01
#define PCI_DEVICE_ID_INTEL_P55 0x3b02
@@ -148,6 +149,11 @@ static inline uint32_t inl(unsigned port)
#define PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM 0x9d84
#define PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_PREM 0x0284
#define PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_BASE 0x0285
#define PCI_DEVICE_ID_INTEL_TIGERPOINT_U_SUPER 0xa081
#define PCI_DEVICE_ID_INTEL_TIGERPOINT_U_PREM 0xa082
#define PCI_DEVICE_ID_INTEL_TIGERPOINT_U_BASE 0xa083
#define PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_SUPER 0xa086
#define PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_PREM 0xa087
#define PCI_DEVICE_ID_INTEL_H110 0xa143
#define PCI_DEVICE_ID_INTEL_H170 0xa144
#define PCI_DEVICE_ID_INTEL_Z170 0xa145
@@ -205,6 +211,18 @@ static inline uint32_t inl(unsigned port)
#define PCI_DEVICE_ID_INTEL_HM370 0xa30d
#define PCI_DEVICE_ID_INTEL_CM246 0xa30e
#define PCI_DEVICE_ID_INTEL_Q570 0x4384
#define PCI_DEVICE_ID_INTEL_Z590 0x4385
#define PCI_DEVICE_ID_INTEL_H570 0x4386
#define PCI_DEVICE_ID_INTEL_B560 0x4387
#define PCI_DEVICE_ID_INTEL_H510 0x4388
#define PCI_DEVICE_ID_INTEL_WM590 0x4389
#define PCI_DEVICE_ID_INTEL_QM580 0x438a
#define PCI_DEVICE_ID_INTEL_HM570 0x438b
#define PCI_DEVICE_ID_INTEL_C252 0x438c
#define PCI_DEVICE_ID_INTEL_C256 0x438d
#define PCI_DEVICE_ID_INTEL_W580 0x438f
#define PCI_DEVICE_ID_INTEL_82810 0x7120
#define PCI_DEVICE_ID_INTEL_82810_DC 0x7122
#define PCI_DEVICE_ID_INTEL_82810E_DC 0x7124
@@ -309,6 +327,13 @@ static inline uint32_t inl(unsigned port)
#define PCI_DEVICE_ID_INTEL_CORE_CML_U1 0x9b51 /* Cometlake U (Mobile) */
#define PCI_DEVICE_ID_INTEL_CORE_CML_U2 0x9b61 /* Cometlake U (Mobile) */
#define PCI_DEVICE_ID_INTEL_CORE_CML_U3 0x9b71 /* Cometlake U (Mobile) */
#define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_U_2 0x9a04 /* Tigerlake UP3 2 Cores */
#define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_U_4 0x9a14 /* Tigerlake UP3 4 Cores */
#define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_Y_2 0x9a02 /* Tigerlake UP4 2 Cores */
#define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_Y_4 0x9a12 /* Tigerlake UP4 4 Cores */
#define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_H_4 0x9a16 /* Tigerlake H 4 Cores */
#define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_H_6 0x9a26 /* Tigerlake H 6 Cores */
#define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_H_8 0x9a36 /* Tigerlake H 8 Cores */
#define PCI_DEVICE_ID_INTEL_HEWITTLAKE 0x6f00 /* Hewitt Lake */
#define PCI_DEVICE_ID_INTEL_SAPPHIRERAPIDS_SP 0x09a2 /* Sapphire Rapids SP */
@@ -381,6 +406,12 @@ static inline uint32_t inl(unsigned port)
#define PCI_DEVICE_ID_INTEL_IRIS_PLUS_655 0x3EA5
#define PCI_DEVICE_ID_INTEL_IRIS_PLUS_G7 0x8A52
#define PCI_DEVICE_ID_INTEL_UHD_GRAPHICS 0x9b41
#define PCI_DEVICE_ID_INTEL_TGL_GT2_Y 0x9A40
#define PCI_DEVICE_ID_INTEL_TGL_GT2_UY 0x9A49
#define PCI_DEVICE_ID_INTEL_TGL_GT1 0x9A60
#define PCI_DEVICE_ID_INTEL_TGL_GT1_2 0x9A68
#define PCI_DEVICE_ID_INTEL_TGL_GT2_ULT_1 0x9A78
#define PCI_DEVICE_ID_INTEL_TGL_GT2_ULT_2 0x9A70
#if !defined(__DARWIN__) && !defined(__FreeBSD__)
typedef struct { uint32_t hi, lo; } msr_t;

16
util/inteltool/pcr.c
View File

@@ -129,10 +129,26 @@ void pcr_init(struct pci_dev *const sb)
case PCI_DEVICE_ID_INTEL_QM370:
case PCI_DEVICE_ID_INTEL_HM370:
case PCI_DEVICE_ID_INTEL_CM246:
case PCI_DEVICE_ID_INTEL_Q570:
case PCI_DEVICE_ID_INTEL_Z590:
case PCI_DEVICE_ID_INTEL_H570:
case PCI_DEVICE_ID_INTEL_B560:
case PCI_DEVICE_ID_INTEL_H510:
case PCI_DEVICE_ID_INTEL_WM590:
case PCI_DEVICE_ID_INTEL_QM580:
case PCI_DEVICE_ID_INTEL_HM570:
case PCI_DEVICE_ID_INTEL_C252:
case PCI_DEVICE_ID_INTEL_C256:
case PCI_DEVICE_ID_INTEL_W580:
case PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM:
case PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_PREM:
case PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_BASE:
case PCI_DEVICE_ID_INTEL_ICELAKE_LP_U:
case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_SUPER:
case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_PREM:
case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_BASE:
case PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_SUPER:
case PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_PREM:
sbbar_phys = 0xfd000000;
use_p2sb = false;
break;

1
util/inteltool/powermgt.c
View File

@@ -780,6 +780,7 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc)
pm_registers_size = ARRAY_SIZE(lynxpoint_lp_pm_registers);
break;
case PCI_DEVICE_ID_INTEL_ICH10:
case PCI_DEVICE_ID_INTEL_ICH10D:
case PCI_DEVICE_ID_INTEL_ICH10DO:
case PCI_DEVICE_ID_INTEL_ICH10R:
pmbase = pci_read_word(sb, 0x40) & 0xff80;

1
util/inteltool/rootcmplx.c
View File

@@ -29,6 +29,7 @@ int print_rcba(struct pci_dev *sb)
case PCI_DEVICE_ID_INTEL_ICH9M:
case PCI_DEVICE_ID_INTEL_ICH9ME:
case PCI_DEVICE_ID_INTEL_ICH10:
case PCI_DEVICE_ID_INTEL_ICH10D:
case PCI_DEVICE_ID_INTEL_ICH10DO:
case PCI_DEVICE_ID_INTEL_ICH10R:
case PCI_DEVICE_ID_INTEL_NM10:

2
util/inteltool/spi.c
View File

@@ -107,6 +107,7 @@ static int print_bioscntl(struct pci_dev *sb)
case PCI_DEVICE_ID_INTEL_ICH9M:
case PCI_DEVICE_ID_INTEL_ICH9ME:
case PCI_DEVICE_ID_INTEL_ICH10:
case PCI_DEVICE_ID_INTEL_ICH10D:
case PCI_DEVICE_ID_INTEL_ICH10DO:
case PCI_DEVICE_ID_INTEL_ICH10R:
case PCI_DEVICE_ID_INTEL_NM10:
@@ -259,6 +260,7 @@ static int print_spibar(struct pci_dev *sb) {
case PCI_DEVICE_ID_INTEL_ICH9M:
case PCI_DEVICE_ID_INTEL_ICH9ME:
case PCI_DEVICE_ID_INTEL_ICH10:
case PCI_DEVICE_ID_INTEL_ICH10D:
case PCI_DEVICE_ID_INTEL_ICH10DO:
case PCI_DEVICE_ID_INTEL_ICH10R:
case PCI_DEVICE_ID_INTEL_NM10: