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soc/intel/adl: Move USB4 hotplug Kconfig to common

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This change adds a new Kconfig `SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES`
that can be selected by mainboard to reserve hotplug resources for
USB4 at the SoC level. `ADL_ENABLE_USB4_PCIE_RESOURCES` is dropped
from soc/intel/alderlake and instead the newly added Kconfig is now
used. This new Kconfig is added so that the same config can be used
across different platforms. In following changes, this Kconfig is
utilized by TGL as well.

Change-Id: Id7c359a0e255c43c2732f6cbe287bc7da14a46e3
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Furquan Shaikh
2021-08-24 13:53:43 -07:00
committed by Patrick Georgi
parent d00febc99b
commit d9f5d90ada
4 changed files with 14 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/mainboard/google/brya/Kconfig.name
View File

@@ -1,22 +1,22 @@
config BOARD_GOOGLE_BRYA0
bool "Brya 0"
select BOARD_GOOGLE_BASEBOARD_BRYA
select ADL_ENABLE_USB4_PCIE_RESOURCES
select DRIVERS_GENESYSLOGIC_GL9755
select DRIVERS_INTEL_MIPI_CAMERA
select SOC_INTEL_COMMON_BLOCK_IPU
select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
config BOARD_GOOGLE_BRASK
bool "Brask"
select BOARD_GOOGLE_BASEBOARD_BRASK
select ADL_ENABLE_USB4_PCIE_RESOURCES
select SOC_INTEL_CRASHLOG
select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
config BOARD_GOOGLE_PRIMUS
bool "-> Primus"
select BOARD_GOOGLE_BASEBOARD_BRYA
select ADL_ENABLE_USB4_PCIE_RESOURCES
select DRIVERS_GENESYSLOGIC_GL9755
select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
config BOARD_GOOGLE_GIMBLE
bool "-> Gimble"

2
src/mainboard/intel/adlrvp/Kconfig
View File

@@ -2,7 +2,6 @@ if BOARD_INTEL_ADLRVP_P || BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_M |
config BOARD_SPECIFIC_OPTIONS
def_bool y
select ADL_ENABLE_USB4_PCIE_RESOURCES
select BOARD_ROMSIZE_KB_32768
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
@@ -26,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS
select FW_CONFIG_SOURCE_CHROMEEC_CBI if BOARD_INTEL_ADLRVP_M_EXT_EC
select MAINBOARD_HAS_TPM2 if BOARD_INTEL_ADLRVP_M_EXT_EC
select MAINBOARD_HAS_SPI_TPM_CR50 if BOARD_INTEL_ADLRVP_M_EXT_EC
select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
select SPI_TPM if BOARD_INTEL_ADLRVP_M_EXT_EC
config CHROMEOS

8
src/soc/intel/alderlake/Kconfig
View File

@@ -148,11 +148,7 @@ config HEAP_SIZE
# - 42 buses
# - 194 MiB Non-prefetchable memory
# - 448 MiB Prefetchable memory
config ADL_ENABLE_USB4_PCIE_RESOURCES
def_bool n
select PCIEXP_HOTPLUG
if ADL_ENABLE_USB4_PCIE_RESOURCES
if SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
config PCIEXP_HOTPLUG_BUSES
int
@@ -166,7 +162,7 @@ config PCIEXP_HOTPLUG_PREFETCH_MEM
hex
default 0x1c000000
endif # ADL_ENABLE_USB4_PCIE_RESOURCES
endif # SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
config MAX_PCH_ROOT_PORTS
int

8
src/soc/intel/common/block/usb4/Kconfig
View File

@@ -18,3 +18,11 @@ config SOC_INTEL_COMMON_BLOCK_USB4_XHCI
help
Minimal PCI driver for adding PCI ops and SSDT generation for common
Intel USB4/Thunderbolt North XHCI ports.
config SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
bool
default n
depends on SOC_INTEL_COMMON_BLOCK_USB4
select PCIEXP_HOTPLUG
help
Enable USB4 PCIe resources for reserving hotplug busses and memory.