soc/intel/adl: Move USB4 hotplug Kconfig to common

This change adds a new Kconfig `SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES`
that can be selected by mainboard to reserve hotplug resources for
USB4 at the SoC level. `ADL_ENABLE_USB4_PCIE_RESOURCES` is dropped
from soc/intel/alderlake and instead the newly added Kconfig is now
used. This new Kconfig is added so that the same config can be used
across different platforms. In following changes, this Kconfig is
utilized by TGL as well.

Change-Id: Id7c359a0e255c43c2732f6cbe287bc7da14a46e3
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/soc/intel/alderlake/Kconfig

@@ -148,11 +148,7 @@ config HEAP_SIZE
 # - 42 buses
 # - 194 MiB Non-prefetchable memory
 # - 448 MiB Prefetchable memory
-config ADL_ENABLE_USB4_PCIE_RESOURCES
-	def_bool n
-	select PCIEXP_HOTPLUG
-
-if ADL_ENABLE_USB4_PCIE_RESOURCES
+if SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
 
 config PCIEXP_HOTPLUG_BUSES
 	int
@@ -166,7 +162,7 @@ config PCIEXP_HOTPLUG_PREFETCH_MEM
 	hex
 	default 0x1c000000
 
-endif # ADL_ENABLE_USB4_PCIE_RESOURCES
+endif # SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
 
 config MAX_PCH_ROOT_PORTS
 	int

src/soc/intel/common/block/usb4/Kconfig

@@ -18,3 +18,11 @@ config SOC_INTEL_COMMON_BLOCK_USB4_XHCI
 	help
 	  Minimal PCI driver for adding PCI ops and SSDT generation for common
 	  Intel USB4/Thunderbolt North XHCI ports.
+
+config SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
+	bool
+	default n
+	depends on SOC_INTEL_COMMON_BLOCK_USB4
+	select PCIEXP_HOTPLUG
+	help
+	  Enable USB4 PCIe resources for reserving hotplug busses and memory.