soc/intel/elkhartlake: Enable SMBus depending on dev state

Program the `SmbusEnable` FSP UPD according to the SMBus PCI device's
state in the devicetree. This avoids having to manually make sure the
SMBus PCI device and the `SmbusEnable` setting are in sync.

Change-Id: I275a981f914a55dc57a75e7d436912ff0255a293
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64402
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb

@@ -14,7 +14,6 @@ chip soc/intel/elkhartlake
 
 	# FSP configuration
 	register "SaGv" = "SaGv_Enabled"
-	register "SmbusEnable" = "1"
 	register "Heci2Enable" = "1"
 
 	# Display related UPDs

src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb

@@ -14,7 +14,6 @@ chip soc/intel/elkhartlake
 
 	# FSP configuration
 	register "SaGv" = "SaGv_Disabled"
-	register "SmbusEnable" = "1"
 
 	# Enable IBECC for the complete memory
 	register "ibecc" = "{

src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb

@@ -14,7 +14,6 @@ chip soc/intel/elkhartlake
 
 	# FSP configuration
 	register "SaGv" = "SaGv_Disabled"
-	register "SmbusEnable" = "1"
 
 	# Enable IBECC for the complete memory
 	register "ibecc" = "{

src/soc/intel/elkhartlake/chip.h

@@ -227,9 +227,6 @@ struct soc_intel_elkhartlake_config {
 	/* PCIe RP L1 substate */
 	enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS];
 
-	/* SMBus */
-	uint8_t SmbusEnable;
-
 	/* eMMC and SD */
 	uint8_t ScsEmmcHs400Enabled;
 	uint8_t ScsEmmcDdr50Enabled;

src/soc/intel/elkhartlake/romstage/fsp_params.c

@@ -64,8 +64,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 	m_cfg->PchMasterClockGating = 1;
 	m_cfg->PchMasterPowerGating = 1;
 
-	/* Enable SMBus controller based on config */
-	m_cfg->SmbusEnable = config->SmbusEnable;
+	m_cfg->SmbusEnable = is_devfn_enabled(PCH_DEVFN_SMBUS);
 
 	/* Set debug probe type */
 	m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ELKHARTLAKE_DEBUG_CONSENT;