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nb/amd/mct_ddr3: Fix RDIMM errors due to undefined number of slots

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The current code did not define the number of DIMM slots on the
mainboard, which lead to incorrect configuration values and
occassional training failure.

Add preliminary support for DIMM slot count configuration.

Change-Id: I488511d6262ffa8207c442d133314aed0f75acfb
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12016
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Timothy Pearson
2015-07-25 01:23:17 -05:00
committed by Martin Roth
parent 323a2af8e2
commit dc4cb05763
11 changed files with 27 additions and 61 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/northbridge/amd/amdmct/mct/mct_d.h
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@@ -687,6 +687,8 @@ struct DCTStatStruc { /* A per Node structure*/
xx0b = disable
yy1b = enable with DctSelIntLvAddr set to yyb */
#define NV_MAX_DIMMS_PER_CH 64 /* Maximum number of DIMMs per channel */
/*===============================================================================
CBMEM storage
===============================================================================*/

24
src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
View File

@@ -809,11 +809,7 @@ static uint32_t fam15h_phy_predriver_clk_calibration_code(struct DCTStatStruc *p
static uint32_t fam15h_output_driver_compensation_code(struct DCTStatStruc *pDCTstat, uint8_t dct)
{
/* FIXME
* Mainboards need to be able to specify the maximum number of DIMMs installable per channel
* For now assume a maximum of 2 DIMMs per channel can be installed
*/
uint8_t MaxDimmsInstallable = 2;
uint8_t MaxDimmsInstallable = mctGet_NVbits(NV_MAX_DIMMS_PER_CH);
uint8_t package_type;
uint32_t calibration_code = 0;
@@ -989,11 +985,7 @@ static uint32_t fam15h_output_driver_compensation_code(struct DCTStatStruc *pDCT
static uint32_t fam15h_address_timing_compensation_code(struct DCTStatStruc *pDCTstat, uint8_t dct)
{
/* FIXME
* Mainboards need to be able to specify the maximum number of DIMMs installable per channel
* For now assume a maximum of 2 DIMMs per channel can be installed
*/
uint8_t MaxDimmsInstallable = 2;
uint8_t MaxDimmsInstallable = mctGet_NVbits(NV_MAX_DIMMS_PER_CH);
uint8_t package_type;
uint32_t calibration_code = 0;
@@ -1171,11 +1163,7 @@ static uint32_t fam15h_address_timing_compensation_code(struct DCTStatStruc *pDC
static uint8_t fam15h_slow_access_mode(struct DCTStatStruc *pDCTstat, uint8_t dct)
{
/* FIXME
* Mainboards need to be able to specify the maximum number of DIMMs installable per channel
* For now assume a maximum of 2 DIMMs per channel can be installed
*/
uint8_t MaxDimmsInstallable = 2;
uint8_t MaxDimmsInstallable = mctGet_NVbits(NV_MAX_DIMMS_PER_CH);
uint8_t package_type;
uint32_t slow_access = 0;
@@ -5878,11 +5866,7 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
printk(BIOS_DEBUG, "%s: Start\n", __func__);
/* FIXME
* Mainboards need to be able to specify the maximum number of DIMMs installable per channel
* For now assume a maximum of 2 DIMMs per channel can be installed
*/
uint8_t MaxDimmsInstallable = 2;
uint8_t MaxDimmsInstallable = mctGet_NVbits(NV_MAX_DIMMS_PER_CH);
if (is_fam15h()) {
/* Obtain number of DIMMs on channel */

2
src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
View File

@@ -953,6 +953,8 @@ struct amd_s3_persistent_data {
xx0b = disable
yy1b = enable with DctSelIntLvAddr set to yyb */
#define NV_MAX_DIMMS_PER_CH 64 /* Maximum number of DIMMs per channel */
/*===============================================================================
CBMEM storage
===============================================================================*/

6
src/northbridge/amd/amdmct/mct_ddr3/mctproc.c
View File

@@ -19,11 +19,7 @@ u32 mct_SetDramConfigMisc2(struct DCTStatStruc *pDCTstat, u8 dct, u32 misc2)
{
u32 val;
/* FIXME
* Mainboards need to be able to specify the maximum number of DIMMs installable per channel
* For now assume a maximum of 2 DIMMs per channel can be installed
*/
uint8_t MaxDimmsInstallable = 2;
uint8_t MaxDimmsInstallable = mctGet_NVbits(NV_MAX_DIMMS_PER_CH);
if (pDCTstat->LogicalCPUID & AMD_FAM15_ALL) {
uint8_t cs_mux_45;

12
src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c
View File

@@ -47,11 +47,7 @@ static uint8_t fam15_rttwr(struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t d
else
frequency_index = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x94) & 0x7;
/* FIXME
* Mainboards need to be able to specify the maximum number of DIMMs installable per channel
* For now assume a maximum of 2 DIMMs per channel can be installed
*/
uint8_t MaxDimmsInstallable = 2;
uint8_t MaxDimmsInstallable = mctGet_NVbits(NV_MAX_DIMMS_PER_CH);
if (is_fam15h()) {
if (pDCTstat->Status & (1 << SB_LoadReduced)) {
@@ -180,11 +176,7 @@ static uint8_t fam15_rttnom(struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t
else
frequency_index = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x94) & 0x7;
/* FIXME
* Mainboards need to be able to specify the maximum number of DIMMs installable per channel
* For now assume a maximum of 2 DIMMs per channel can be installed
*/
uint8_t MaxDimmsInstallable = 2;
uint8_t MaxDimmsInstallable = mctGet_NVbits(NV_MAX_DIMMS_PER_CH);
if (is_fam15h()) {
if (pDCTstat->Status & (1 << SB_LoadReduced)) {

6
src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
View File

@@ -101,11 +101,7 @@ static uint16_t fam15_receiver_enable_training_seed(struct DCTStatStruc *pDCTsta
uint32_t dword;
uint16_t seed = 0;
/* FIXME
* Mainboards need to be able to specify the maximum number of DIMMs installable per channel
* For now assume a maximum of 2 DIMMs per channel can be installed
*/
uint8_t MaxDimmsInstallable = 2;
uint8_t MaxDimmsInstallable = mctGet_NVbits(NV_MAX_DIMMS_PER_CH);
uint8_t channel = dct;
if (package_type == PT_GR) {

2
src/northbridge/amd/amdmct/mct_ddr3/mctwl.c
View File

@@ -27,8 +27,6 @@ void PrepareC_MCT(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat)
{
pDCTstat->C_MCTPtr->AgesaDelay = AgesaDelay;
pDCTstat->C_MCTPtr->PlatMaxTotalDimms = mctGet_NVbits(NV_MAX_DIMMS);
pDCTstat->C_MCTPtr->PlatMaxDimmsDct = pDCTstat->C_MCTPtr->PlatMaxTotalDimms >> 1;
}
void PrepareC_DCT(struct MCTStatStruc *pMCTstat,

12
src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
View File

@@ -415,11 +415,7 @@ static uint16_t unbuffered_dimm_nominal_termination_emrs(uint8_t number_of_dimms
{
uint16_t term;
/* FIXME
* Mainboards need to be able to specify the maximum number of DIMMs installable per channel
* For now assume a maximum of 2 DIMMs per channel can be installed
*/
uint8_t MaxDimmsInstallable = 2;
uint8_t MaxDimmsInstallable = mctGet_NVbits(NV_MAX_DIMMS_PER_CH);
if (number_of_dimms == 1) {
if (MaxDimmsInstallable < 3) {
@@ -448,11 +444,7 @@ static uint16_t unbuffered_dimm_dynamic_termination_emrs(uint8_t number_of_dimms
{
uint16_t term;
/* FIXME
* Mainboards need to be able to specify the maximum number of DIMMs installable per channel
* For now assume a maximum of 2 DIMMs per channel can be installed
*/
uint8_t MaxDimmsInstallable = 2;
uint8_t MaxDimmsInstallable = mctGet_NVbits(NV_MAX_DIMMS_PER_CH);
if (number_of_dimms == 1) {
if (MaxDimmsInstallable < 3) {

11
src/northbridge/amd/amdmct/mct_ddr3/modtrdim.c
View File

@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -53,7 +54,7 @@ static u32 RttNomTargetRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 d
u32 tempW1;
tempW1 = 0;
if (wl) {
switch (pMCTData->PlatMaxDimmsDct) {
switch (mctGet_NVbits(NV_MAX_DIMMS_PER_CH)) {
case 2:
/* 2 dimms per channel */
if (pDCTData->MaxDimmsInstalled == 1) {
@@ -107,7 +108,7 @@ static u32 RttNomTargetRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 d
ASSERT (FALSE);
}
} else {
switch (pMCTData->PlatMaxDimmsDct) {
switch (mctGet_NVbits(NV_MAX_DIMMS_PER_CH)) {
case 2:
/* 2 dimms per channel */
if ((pDCTData->DimmRanks[dimm] == 4) && (rank == 1)) {
@@ -163,7 +164,7 @@ static u32 RttNomTargetRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 d
*/
static u32 RttNomNonTargetRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm, BOOL wl, u8 MemClkFreq, u8 rank)
{
if ((wl) && (pMCTData->PlatMaxDimmsDct == 2) && (pDCTData->DimmRanks[dimm] == 2) && (rank == 1)) {
if ((wl) && (mctGet_NVbits(NV_MAX_DIMMS_PER_CH) == 2) && (pDCTData->DimmRanks[dimm] == 2) && (rank == 1)) {
return 0x00; /* for non-target dimm during WL, the second rank of a DR dimm need to have Rtt_Nom = OFF */
} else {
return RttNomTargetRegDimm (pMCTData, pDCTData, dimm, FALSE, MemClkFreq, rank); /* otherwise, the same as target dimm in normal mode. */
@@ -193,7 +194,7 @@ static u32 RttWrRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm, BO
if (wl) {
tempW1 = 0x00; /* Rtt_WR = OFF */
} else {
switch (pMCTData->PlatMaxDimmsDct) {
switch (mctGet_NVbits(NV_MAX_DIMMS_PER_CH)) {
case 2:
if (pDCTData->MaxDimmsInstalled == 1) {
if (pDCTData->DimmRanks[dimm] != 4) {
@@ -258,7 +259,7 @@ static u8 WrLvOdtRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm)
}
i += 2;
}
if (pMCTData->PlatMaxDimmsDct == 2) {
if (mctGet_NVbits(NV_MAX_DIMMS_PER_CH) == 2) {
if ((pDCTData->DimmRanks[dimm] == 4) && (pDCTData->MaxDimmsInstalled != 1)) {
if (dimm >= 2) {
WrLvOdt1 = (u8)bitTestReset (WrLvOdt1, (dimm - 2));

4
src/northbridge/amd/amdmct/mct_ddr3/mwlc_d.h
View File

@@ -105,10 +105,6 @@
typedef struct _sMCTStruct
{
u8 PlatMaxTotalDimms; /* IBV defined total number of DIMMs */
/* on a particular node */
u8 PlatMaxDimmsDct; /* IBV defined maximum number of */
/* DIMMs on a DCT */
void (*AgesaDelay)(u32 delayval); /* IBV defined Delay Function */
} sMCTStruct;

7
src/northbridge/amd/amdmct/wrappers/mcti_d.c
View File

@@ -70,6 +70,13 @@ static u16 mctGet_NVbits(u8 index)
val = MAX_DIMMS_SUPPORTED;
//val = 8;
break;
case NV_MAX_DIMMS_PER_CH:
/* FIXME
* Mainboards need to be able to specify the maximum number of DIMMs installable per channel
* For now assume a maximum of 2 DIMMs per channel can be installed
*/
val = 2;
break;
case NV_MAX_MEMCLK:
/* Maximum platform supported memclk */
val = MEM_MAX_LOAD_FREQ;