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soc/amd/picasso: Add acp_i2s_use_external_48mhz_osc flag

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If we have use external clock source for I2S, we don't need to enable
internal one. Add acp_i2s_use_external_48mhz_osc flag for the project
which uses external clock source.

BUG=b:174121847
BRANCH=zork
TEST= build passed

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ica68ee2da5a05231eb6db0218bd0f19907507273
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Eric Lai 2020-12-15 14:51:50 +08:00 committed by Furquan Shaikh
parent 07462ef3d6
commit dd32e653cf
2 changed files with 9 additions and 1 deletions
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2
src/soc/amd/picasso/chip.h
View File

@ -219,6 +219,8 @@ struct soc_amd_picasso_config {
/* The array index is the general purpose PCIe clock output number. */
enum gpp_clk_req_setting gpp_clk_config[GPP_CLK_OUTPUT_COUNT];
/* If using an external 48MHz OSC for codec, will disable internal X48M_OSC */
bool acp_i2s_use_external_48mhz_osc;
};
#endif /* __PICASSO_CHIP_H__ */

8
src/soc/amd/picasso/fch.c
View File

@ -89,9 +89,15 @@ const struct irq_idx_name *sb_get_apic_reg_association(size_t *size)
void sb_clk_output_48Mhz(void)
{
u32 ctrl;
const struct soc_amd_picasso_config *cfg;
cfg = config_of_soc();
ctrl = misc_read32(MISC_CLK_CNTL1);
ctrl |= BP_X48M0_OUTPUT_EN;
/* If used external clock source for I2S, disable the internal clock output */
if (cfg->acp_i2s_use_external_48mhz_osc && cfg->acp_pin_cfg == I2S_PINS_I2S_TDM)
ctrl &= ~BP_X48M0_OUTPUT_EN;
else
ctrl |= BP_X48M0_OUTPUT_EN;
misc_write32(MISC_CLK_CNTL1, ctrl);
}