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amd/stoneyridge: Indicate STAPM units in their name

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STAPM devicetree registers do not indicate the unit, which causes confusion.
More importantly, the time was assumed to be in seconds when it's actually
milliseconds. This caused early STAPM configurations to fail.

BUG=b:117590953
TEST=Build grunt

Change-Id: I2a7e3d43601992d1f7b02456913c763d940fe9ee
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29035
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Richard Spiegel
2018-10-11 08:15:43 -07:00
committed by Martin Roth
parent f9735dc760
commit de5d04011c
4 changed files with 11 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/mainboard/google/kahlee/variants/careena/devicetree.cb
View File

@@ -21,8 +21,8 @@ chip soc/amd/stoneyridge
register "uma_mode" = "UMAMODE_SPECIFIED_SIZE"
register "uma_size" = "32 * MiB"
register "stapm_percent" = "68"
register "stapm_time" = "2500000"
register "stapm_power" = "7800"
register "stapm_time_ms" = "2500000"
register "stapm_power_mw" = "7800"
# Enable I2C0 for audio, USB3 hub at 400kHz
register "i2c[0]" = "{

4
src/mainboard/google/kahlee/variants/grunt/devicetree.cb
View File

@@ -21,8 +21,8 @@ chip soc/amd/stoneyridge
register "uma_mode" = "UMAMODE_SPECIFIED_SIZE"
register "uma_size" = "32 * MiB"
register "stapm_percent" = "80"
register "stapm_time" = "2500000"
register "stapm_power" = "7800"
register "stapm_time_ms" = "2500000"
register "stapm_power_mw" = "7800"
# Enable I2C0 for audio, USB3 hub at 400kHz
register "i2c[0]" = "{

4
src/soc/amd/stoneyridge/chip.h
View File

@@ -61,8 +61,8 @@ struct soc_amd_stoneyridge_config {
u8 i2c_scl_reset;
struct dw_i2c_bus_config i2c[STONEY_I2C_DEV_MAX];
u8 stapm_percent;
u32 stapm_time;
u32 stapm_power;
u32 stapm_time_ms;
u32 stapm_power_mw;
};
typedef struct soc_amd_stoneyridge_config config_t;

9
src/soc/amd/stoneyridge/romstage.c
View File

@@ -235,12 +235,13 @@ void soc_customize_init_early(AMD_EARLY_PARAMS *InitEarly)
}
cfg = dev->chip_info;
platform = &InitEarly->PlatformConfig;
if ((cfg->stapm_percent) && (cfg->stapm_time) && (cfg->stapm_power)) {
if ((cfg->stapm_percent) && (cfg->stapm_time_ms) &&
(cfg->stapm_power_mw)) {
platform->PlatStapmConfig.CfgStapmScalar = cfg->stapm_percent;
platform->PlatStapmConfig.CfgStapmTimeConstant =
cfg->stapm_time;
platform->PkgPwrLimitDC = cfg->stapm_power;
platform->PkgPwrLimitAC = cfg->stapm_power;
cfg->stapm_time_ms;
platform->PkgPwrLimitDC = cfg->stapm_power_mw;
platform->PkgPwrLimitAC = cfg->stapm_power_mw;
platform->PlatStapmConfig.CfgStapmBoost = StapmBoostEnabled;
}
}