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soc/intel/tigerlake: Fix setting HyperThreading

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The `HyperThreading` FSP UPD is set according to the `hyper_threading`
CMOS option using the value of the `FSP_HYPERTHREADING` Kconfig option
as fallback in case options are disabled or otherwise unavailable. The
`HyperThreadingDisable` devicetree setting isn't used by any mainboard
but it overwrites the value of the FSP UPD. Remove it so that the CMOS
and Kconfig options work as intended.

Change-Id: Iea60b89f6f970eb9aee8c7bec026ab5c2df30205
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69534
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2022-11-13 20:25:33 +01:00 committed by Felix Held
parent a3311b9f0f
commit def3c5ccab
2 changed files with 0 additions and 6 deletions
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3
src/soc/intel/tigerlake/chip.h
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@ -432,9 +432,6 @@ struct soc_intel_tigerlake_config {
*/
uint8_t cpu_ratio_override;
/* HyperThreadingDisable : Yes (1) / No (0) */
uint8_t HyperThreadingDisable;
/*
* Enable(0)/Disable(1) DMI Power Optimizer on PCH side.
* Default 0. Setting this to 1 disables the DMI Power Optimizer.

3
src/soc/intel/tigerlake/romstage/fsp_params.c
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@ -125,9 +125,6 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
m_cfg->TcssItbtPcie2En = is_devfn_enabled(SA_DEVFN_TBT2);
m_cfg->TcssItbtPcie3En = is_devfn_enabled(SA_DEVFN_TBT3);
/* Hyper Threading */
m_cfg->HyperThreading = !config->HyperThreadingDisable;
/* Disable Lock PCU Thermal Management registers */
m_cfg->LockPTMregs = 0;
/* Channel Hash Mask:0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum) */