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mb/intel/mtlrvp: Enable S0ix

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This patch enables S0ix for MTL-P RVP platform

BUG=None
TEST=Able to enter low power idle S0 on MTL-P RVP

Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: Id84f21d81197e44d6dd0dd8888c80848aa3679e0
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71994
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Harsha B R <harsha.b.r@intel.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
This commit is contained in:
Usha P
2023-01-16 15:03:13 +05:30
committed by Eric Lai
parent f8665f08fa
commit df6bc335f5
1 changed files with 3 additions and 0 deletions
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3
src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
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@@ -39,6 +39,9 @@ chip soc/intel/meteorlake
# Enable CNVi BT # Enable CNVi BT
register "cnvi_bt_core" = "true" register "cnvi_bt_core" = "true"
# Enable S0ix
register "s0ix_enable" = "1"
# Enable EDP in PortA # Enable EDP in PortA
register "ddi_port_A_config" = "1" register "ddi_port_A_config" = "1"
# Enable HDMI in Port B # Enable HDMI in Port B