soc/amd/common/*/Kconfig: remove unneeded default n for bool options
n is the default of bool Kconfig options, so no need to have that added to each option. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8775d84caee6fda95eb7749e96090fe05417e764 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50779 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
@@ -7,7 +7,6 @@ if SOC_AMD_COMMON
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config SOC_AMD_PI
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bool
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default n
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source "src/soc/amd/common/block/*/Kconfig"
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@@ -2,6 +2,5 @@ config SOC_AMD_COMMON_BLOCK_ACPI
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bool
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depends on SOC_AMD_COMMON_BLOCK_ACPIMMIO
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select ACPI_AMD_HARDWARE_SLEEP_VALUES
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default n
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help
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Select this option to use the AcpiMmio ACPI registers.
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@@ -1,6 +1,5 @@
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config SOC_AMD_COMMON_BLOCK_ACPIMMIO
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bool
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default n
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help
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Select this option to enable hardware blocks in the AcpiMmio
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address space (0xfed8xxxx).
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@@ -1,5 +1,4 @@
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config SOC_AMD_COMMON_BLOCK_ALINK
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bool
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default n
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help
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Select this option to access the FCH A-link configuration registers.
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@@ -1,6 +1,5 @@
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config SOC_AMD_COMMON_BLOCK_AOAC
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bool
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default n
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help
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Select this option to add the common functions for the AOAC (always
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on, always connected) block to the build.
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@@ -1,6 +1,5 @@
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config SOC_AMD_COMMON_BLOCK_CAR
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bool
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default n
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help
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This option allows the SOC to use a standard AMD cache-as-ram (CAR)
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implementation. CAR setup is built into bootblock and teardown is
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@@ -14,7 +13,6 @@ config SOC_AMD_COMMON_BLOCK_CAR
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config SOC_AMD_COMMON_BLOCK_NONCAR
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bool
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default n
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help
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From family 17h on AMD CPUs/APUs don't use cache as RAM (CAR) any
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more, since the RAM initialization is already done by the PSP when
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@@ -30,7 +28,6 @@ endif # SOC_AMD_COMMON_BLOCK_NONCAR
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config SOC_AMD_COMMON_BLOCK_SMM
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bool
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default n
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help
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Add common SMM relocation and handler functionality to the build.
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@@ -39,7 +36,6 @@ config SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H
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select COLLECT_TIMESTAMPS_NO_TSC # selected use SoC-specific timestamp function
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select TSC_SYNC_LFENCE
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select UDELAY_TSC
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default n
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help
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Select this option to add the common functions for getting the TSC
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frequency of AMD family 17h and 19h CPUs/APUs and to provide TSC-
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@@ -48,7 +44,6 @@ config SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H
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config SOC_AMD_COMMON_BLOCK_UCODE
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bool
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select SUPPORT_CPU_UCODE_IN_CBFS
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default n
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help
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Builds in support for loading uCode.
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@@ -1,7 +1,6 @@
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config SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
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bool
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depends on SOC_AMD_COMMON_BLOCK_ACPIMMIO
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default n
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help
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Select this option to use the newer style banks of GPIO signals.
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These are at offsets +0x1500, +0x1600, and +0x1700 from the AcpiMmio
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@@ -1,6 +1,5 @@
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config SOC_AMD_COMMON_BLOCK_GRAPHICS
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bool
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default n
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help
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Select this option to use AMD common graphics driver support.
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@@ -1,6 +1,5 @@
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config SOC_AMD_COMMON_BLOCK_HDA
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bool
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default n
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help
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Select this option to use AMD common High Definition Audio
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driver support.
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@@ -1,5 +1,4 @@
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config SOC_AMD_COMMON_BLOCK_IOMMU
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bool
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default n
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help
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Select this option to use AMD common IOMMU support.
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@@ -1,18 +1,15 @@
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config SOC_AMD_COMMON_BLOCK_LPC
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bool
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default n
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help
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Select this option to use the traditional LPC-ISA bridge at D14F3.
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config PROVIDES_ROM_SHARING
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bool
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default n
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help
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Select this option if the LPC bridge supports ROM sharing.
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config SOC_AMD_COMMON_BLOCK_HAS_ESPI
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bool
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default n
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help
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Select this option if platform supports eSPI using D14F3 configuration
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registers.
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@@ -20,7 +17,6 @@ config SOC_AMD_COMMON_BLOCK_HAS_ESPI
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config SOC_AMD_COMMON_BLOCK_USE_ESPI
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bool
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depends on SOC_AMD_COMMON_BLOCK_HAS_ESPI
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default n
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help
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Select this option if mainboard uses eSPI instead of LPC (if supported
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by platform).
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@@ -28,4 +24,3 @@ config SOC_AMD_COMMON_BLOCK_USE_ESPI
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config SOC_AMD_COMMON_BLOCK_HAS_ESPI_SUB_DECODE
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bool
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depends on SOC_AMD_COMMON_BLOCK_HAS_ESPI
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default n
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@@ -1,6 +1,5 @@
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config SOC_AMD_COMMON_BLOCK_PCI
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bool
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default n
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select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
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help
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This option builds functions used to program PCI interrupt
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@@ -8,7 +7,6 @@ config SOC_AMD_COMMON_BLOCK_PCI
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config SOC_AMD_COMMON_BLOCK_PCI_MMCONF
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bool
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default n
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help
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Selecting this option adds the AMD-common enable_pci_mmconf function
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to the build.
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@@ -1,7 +1,6 @@
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config SOC_AMD_COMMON_BLOCK_PI
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bool
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select HAVE_DEBUG_RAM_SETUP
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default n
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help
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This option builds functions that interface AMD's AGESA reference
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code packaged in the binaryPI form.
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@@ -1,6 +1,5 @@
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config SOC_AMD_COMMON_BLOCK_PSP
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bool
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default n
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help
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This option builds in the Platform Security Processor initialization
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functions. Do not select this directly in SoC code, select
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@@ -8,21 +7,18 @@ config SOC_AMD_COMMON_BLOCK_PSP
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config SOC_AMD_COMMON_BLOCK_PSP_GEN1
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bool
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default n
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select SOC_AMD_COMMON_BLOCK_PSP
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help
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Used by the PSP in AMD systems before family 17h, e.g. stoneyridge.
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config SOC_AMD_COMMON_BLOCK_PSP_GEN2
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bool
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default n
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select SOC_AMD_COMMON_BLOCK_PSP
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help
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Used by the PSP in AMD family 17h, 19h and possibly newer CPUs.
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config SOC_AMD_PSP_SELECTABLE_SMU_FW
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bool
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default n
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help
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Some PSP implementations allow storing SMU firmware into cbfs and
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calling the PSP to load the blobs at the proper time.
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@@ -1,6 +1,5 @@
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config SOC_AMD_COMMON_BLOCK_S3
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bool
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default n
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depends on SOC_AMD_COMMON_BLOCK_ACPI
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select CACHE_MRC_SETTINGS
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select MRC_WRITE_NV_LATE
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@@ -1,5 +1,4 @@
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config SOC_AMD_COMMON_BLOCK_SATA
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bool
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default n
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help
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Select this option to use AMD common SATA driver support.
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@@ -1,5 +1,4 @@
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config SOC_AMD_COMMON_BLOCK_SMBUS
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bool
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default n
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help
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Select this option to add FCH SMBus controller functions to the build.
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@@ -1,6 +1,5 @@
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config SOC_AMD_COMMON_BLOCK_SMI
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bool
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default n
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help
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Select this option to add the common functions for setting up the SMI
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configuration to the build.
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@@ -1,5 +1,4 @@
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config SOC_AMD_COMMON_BLOCK_SMU
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bool
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default n
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help
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Select this option to add functions to communicate with the SMU to the build.
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@@ -1,6 +1,5 @@
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config SOC_AMD_COMMON_BLOCK_SPI
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bool
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default n
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help
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Select this option to add FCH SPI controller functions to the build.
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This overwrites the structure spi_flash_ops to use FCH SPI code
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@@ -8,7 +7,6 @@ config SOC_AMD_COMMON_BLOCK_SPI
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config SOC_AMD_COMMON_BLOCK_SPI_DEBUG
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bool
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default n
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config EFS_SPI_READ_MODE
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int
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@@ -1,6 +1,5 @@
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config SOC_AMD_COMMON_BLOCK_UART
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bool
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default n
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help
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Select this option to add the common functions for setting up the
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UART configuration to the build.
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@@ -9,7 +8,6 @@ if SOC_AMD_COMMON_BLOCK_UART
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config AMD_SOC_CONSOLE_UART
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bool "Use integrated AMD SoC UART controller for console"
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default n
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select DRIVERS_UART_8250MEM
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select DRIVERS_UART_8250MEM_32
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select NO_UART_ON_SUPERIO
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