mb/siemens/mc_ehl2: Enable Marvell PHY interrupt
On this mainboard Marvell PHY INTn is routed to LED[2] pin. Change-Id: I28a78afdcf0599bb998f906ce8056a0586e24f33 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69434 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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committed by
Martin L Roth
parent
155cf5cd2e
commit
e19f403770
@@ -189,6 +189,8 @@ chip soc/intel/elkhartlake
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register "led_0_ctrl" = "7"
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# LED[1]: On - Link, Blink - Activity, Off - No Link
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register "led_1_ctrl" = "1"
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# INTn is routed to LED[2] pin
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register "enable_int" = "true"
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device mdio 0 on # PHY address
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ops m88e1512_ops
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end
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@@ -202,6 +204,8 @@ chip soc/intel/elkhartlake
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register "led_0_ctrl" = "7"
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# LED[1]: On - Link, Blink - Activity, Off - No Link
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register "led_1_ctrl" = "1"
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# INTn is routed to LED[2] pin
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register "enable_int" = "true"
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device mdio 1 on # PHY address
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ops m88e1512_ops
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end
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@@ -218,6 +222,8 @@ chip soc/intel/elkhartlake
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register "led_0_ctrl" = "7"
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# LED[1]: On - Link, Blink - Activity, Off - No Link
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register "led_1_ctrl" = "1"
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# INTn is routed to LED[2] pin
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register "enable_int" = "true"
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device mdio 1 on # PHY address
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ops m88e1512_ops
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end
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