cpu/x86: Introduce CPU_X86_CACHE_HELPER

There's no need for relative paths with Kconfig options.

Change-Id: Ib9b9b29a158c34a30480aaabf6d0b23819d28427
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

src/cpu/amd/agesa/family14/Kconfig

@@ -3,6 +3,7 @@
 config CPU_AMD_AGESA_FAMILY14
 	bool
 	select X86_AMD_FIXED_MTRRS
+	select CPU_X86_CACHE_HELPER
 
 if CPU_AMD_AGESA_FAMILY14
 

src/cpu/amd/agesa/family14/Makefile.inc

@@ -8,4 +8,3 @@ ramstage-y += model_14_init.c
 
 subdirs-y += ../../mtrr
 subdirs-y += ../../../x86/lapic
-subdirs-y += ../../../x86/cache

src/cpu/amd/agesa/family15tn/Kconfig

@@ -4,6 +4,7 @@ config CPU_AMD_AGESA_FAMILY15_TN
 	bool
 	select IDS_OPTIONS_HOOKED_UP
 	select X86_AMD_FIXED_MTRRS
+	select CPU_X86_CACHE_HELPER
 
 if CPU_AMD_AGESA_FAMILY15_TN
 

src/cpu/amd/agesa/family15tn/Makefile.inc

@@ -11,4 +11,3 @@ smm-y += udelay.c
 subdirs-y += ../../mtrr
 subdirs-y += ../../smm
 subdirs-y += ../../../x86/lapic
-subdirs-y += ../../../x86/cache

src/cpu/amd/agesa/family16kb/Kconfig

@@ -3,6 +3,7 @@
 config CPU_AMD_AGESA_FAMILY16_KB
 	bool
 	select X86_AMD_FIXED_MTRRS
+	select CPU_X86_CACHE_HELPER
 
 if CPU_AMD_AGESA_FAMILY16_KB
 

src/cpu/amd/agesa/family16kb/Makefile.inc

@@ -8,4 +8,3 @@ ramstage-y += model_16_init.c
 
 subdirs-y += ../../mtrr
 subdirs-y += ../../../x86/lapic
-subdirs-y += ../../../x86/cache

src/cpu/intel/slot_1/Kconfig

@@ -12,6 +12,7 @@ config SLOT_SPECIFIC_OPTIONS
 	select CPU_INTEL_MODEL_68X
 	select CPU_INTEL_MODEL_6BX
 	select CPU_INTEL_MODEL_6XX
+	select CPU_X86_CACHE_HELPER
 	select NO_SMM
 	select UDELAY_TSC
 	select TSC_MONOTONIC_TIMER

src/cpu/intel/slot_1/Makefile.inc

@@ -8,7 +8,6 @@ subdirs-y += ../model_67x
 subdirs-y += ../model_68x
 subdirs-y += ../model_6bx
 subdirs-y += ../../x86/lapic
-subdirs-y += ../../x86/cache
 subdirs-y += ../microcode
 
 bootblock-y += ../car/p3/cache_as_ram.S

src/cpu/intel/socket_441/Kconfig

@@ -6,6 +6,7 @@ if CPU_INTEL_SOCKET_441
 config SOCKET_SPECIFIC_OPTIONS
 	def_bool y
 	select CPU_INTEL_MODEL_106CX
+	select CPU_X86_CACHE_HELPER
 	select MMX
 	select SSE
 	select SETUP_XIP_CACHE

src/cpu/intel/socket_441/Makefile.inc

@@ -1,6 +1,5 @@
 subdirs-y += ../model_106cx
 subdirs-y += ../../x86/lapic
-subdirs-y += ../../x86/cache
 subdirs-y += ../microcode
 subdirs-y += ../speedstep
 

src/cpu/intel/socket_BGA956/Kconfig

@@ -1,6 +1,7 @@
 config CPU_INTEL_SOCKET_BGA956
 	bool
 	select CPU_INTEL_MODEL_1067X
+	select CPU_X86_CACHE_HELPER
 	select MMX
 	select SSE
 

src/cpu/intel/socket_BGA956/Makefile.inc

@@ -1,6 +1,5 @@
 subdirs-y += ../model_1067x
 subdirs-y += ../../x86/lapic
-subdirs-y += ../../x86/cache
 subdirs-y += ../microcode
 subdirs-y += ../speedstep
 

src/cpu/intel/socket_FCBGA559/Kconfig

@@ -8,6 +8,7 @@ if CPU_INTEL_SOCKET_FCBGA559
 config SOCKET_SPECIFIC_OPTIONS
 	def_bool y
 	select CPU_INTEL_MODEL_106CX
+	select CPU_X86_CACHE_HELPER
 	select MMX
 	select SSE
 	select CPU_HAS_L2_ENABLE_MSR

src/cpu/intel/socket_FCBGA559/Makefile.inc

@@ -1,6 +1,5 @@
 subdirs-y += ../model_106cx
 subdirs-y += ../../x86/lapic
-subdirs-y += ../../x86/cache
 subdirs-y += ../microcode
 subdirs-y += ../speedstep
 

src/cpu/intel/socket_LGA775/Kconfig

@@ -11,6 +11,7 @@ config SOCKET_SPECIFIC_OPTIONS
 #	select CPU_INTEL_MODEL_F6X
 #	select CPU_INTEL_MODEL_1066X
 	select CPU_INTEL_MODEL_1067X
+	select CPU_X86_CACHE_HELPER
 	select MMX
 	select SSE
 	select SIPI_VECTOR_IN_ROM

src/cpu/intel/socket_LGA775/Makefile.inc

@@ -5,7 +5,6 @@ subdirs-y += ../model_f4x
 #subdirs-y += ../model_1066x
 subdirs-y += ../model_1067x
 subdirs-y += ../../x86/lapic
-subdirs-y += ../../x86/cache
 subdirs-y += ../microcode
 subdirs-y += ../speedstep
 

src/cpu/intel/socket_m/Kconfig

@@ -7,6 +7,7 @@ config SOCKET_SPECIFIC_OPTIONS
 	def_bool y
 	select CPU_INTEL_MODEL_6EX
 	select CPU_INTEL_MODEL_6FX
+	select CPU_X86_CACHE_HELPER
 	select MMX
 	select SSE
 

src/cpu/intel/socket_m/Makefile.inc

@@ -1,7 +1,6 @@
 subdirs-y += ../model_6ex
 subdirs-y += ../model_6fx
 subdirs-y += ../../x86/lapic
-subdirs-y += ../../x86/cache
 subdirs-y += ../microcode
 subdirs-y += ../speedstep
 

src/cpu/intel/socket_mPGA604/Kconfig

@@ -6,6 +6,7 @@ if CPU_INTEL_SOCKET_MPGA604
 config SOCKET_SPECIFIC_OPTIONS
 	def_bool y
 	select CPU_INTEL_MODEL_F2X
+	select CPU_X86_CACHE_HELPER
 	select MMX
 	select SSE
 	select UDELAY_TSC

src/cpu/intel/socket_mPGA604/Makefile.inc

@@ -1,6 +1,5 @@
 subdirs-y += ../model_f2x
 subdirs-y += ../../x86/lapic
-subdirs-y += ../../x86/cache
 subdirs-y += ../microcode
 
 bootblock-y += ../car/p4-netburst/cache_as_ram.S

src/cpu/intel/socket_p/Kconfig

@@ -2,6 +2,7 @@ config CPU_INTEL_SOCKET_P
 	bool
 	select CPU_INTEL_MODEL_1067X
 	select CPU_INTEL_MODEL_6FX
+	select CPU_X86_CACHE_HELPER
 	select MMX
 	select SSE
 

src/cpu/intel/socket_p/Makefile.inc

@@ -1,7 +1,6 @@
 subdirs-y += ../model_6fx
 subdirs-y += ../model_1067x
 subdirs-y += ../../x86/lapic
-subdirs-y += ../../x86/cache
 subdirs-y += ../microcode
 subdirs-y += ../speedstep
 

src/cpu/x86/Kconfig

@@ -1,3 +1,9 @@
+config CPU_X86_CACHE_HELPER
+	bool
+	default n
+	help
+	  Add the x86_enable_cache ramstage helper function to the build.
+
 config PARALLEL_MP
 	def_bool y
 	depends on !LEGACY_SMP_INIT

src/cpu/x86/Makefile.inc

@@ -1,3 +1,4 @@
+subdirs-$(CONFIG_CPU_X86_CACHE_HELPER) += cache
 subdirs-y += mtrr
 subdirs-y += pae
 subdirs-$(CONFIG_HAVE_SMI_HANDLER) += smm