cpu/x86: Introduce CPU_X86_CACHE_HELPER

There's no need for relative paths with Kconfig options.

Change-Id: Ib9b9b29a158c34a30480aaabf6d0b23819d28427
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Felix Held
2021-10-22 23:54:53 +02:00
committed by Felix Held
parent 8023eabde1
commit e2783daa84
24 changed files with 18 additions and 11 deletions

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@@ -12,6 +12,7 @@ config SLOT_SPECIFIC_OPTIONS
select CPU_INTEL_MODEL_68X
select CPU_INTEL_MODEL_6BX
select CPU_INTEL_MODEL_6XX
select CPU_X86_CACHE_HELPER
select NO_SMM
select UDELAY_TSC
select TSC_MONOTONIC_TIMER

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@@ -8,7 +8,6 @@ subdirs-y += ../model_67x
subdirs-y += ../model_68x
subdirs-y += ../model_6bx
subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
subdirs-y += ../microcode
bootblock-y += ../car/p3/cache_as_ram.S

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@@ -6,6 +6,7 @@ if CPU_INTEL_SOCKET_441
config SOCKET_SPECIFIC_OPTIONS
def_bool y
select CPU_INTEL_MODEL_106CX
select CPU_X86_CACHE_HELPER
select MMX
select SSE
select SETUP_XIP_CACHE

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@@ -1,6 +1,5 @@
subdirs-y += ../model_106cx
subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
subdirs-y += ../microcode
subdirs-y += ../speedstep

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@@ -1,6 +1,7 @@
config CPU_INTEL_SOCKET_BGA956
bool
select CPU_INTEL_MODEL_1067X
select CPU_X86_CACHE_HELPER
select MMX
select SSE

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@@ -1,6 +1,5 @@
subdirs-y += ../model_1067x
subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
subdirs-y += ../microcode
subdirs-y += ../speedstep

View File

@@ -8,6 +8,7 @@ if CPU_INTEL_SOCKET_FCBGA559
config SOCKET_SPECIFIC_OPTIONS
def_bool y
select CPU_INTEL_MODEL_106CX
select CPU_X86_CACHE_HELPER
select MMX
select SSE
select CPU_HAS_L2_ENABLE_MSR

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@@ -1,6 +1,5 @@
subdirs-y += ../model_106cx
subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
subdirs-y += ../microcode
subdirs-y += ../speedstep

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@@ -11,6 +11,7 @@ config SOCKET_SPECIFIC_OPTIONS
# select CPU_INTEL_MODEL_F6X
# select CPU_INTEL_MODEL_1066X
select CPU_INTEL_MODEL_1067X
select CPU_X86_CACHE_HELPER
select MMX
select SSE
select SIPI_VECTOR_IN_ROM

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@@ -5,7 +5,6 @@ subdirs-y += ../model_f4x
#subdirs-y += ../model_1066x
subdirs-y += ../model_1067x
subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
subdirs-y += ../microcode
subdirs-y += ../speedstep

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@@ -7,6 +7,7 @@ config SOCKET_SPECIFIC_OPTIONS
def_bool y
select CPU_INTEL_MODEL_6EX
select CPU_INTEL_MODEL_6FX
select CPU_X86_CACHE_HELPER
select MMX
select SSE

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@@ -1,7 +1,6 @@
subdirs-y += ../model_6ex
subdirs-y += ../model_6fx
subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
subdirs-y += ../microcode
subdirs-y += ../speedstep

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@@ -6,6 +6,7 @@ if CPU_INTEL_SOCKET_MPGA604
config SOCKET_SPECIFIC_OPTIONS
def_bool y
select CPU_INTEL_MODEL_F2X
select CPU_X86_CACHE_HELPER
select MMX
select SSE
select UDELAY_TSC

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@@ -1,6 +1,5 @@
subdirs-y += ../model_f2x
subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
subdirs-y += ../microcode
bootblock-y += ../car/p4-netburst/cache_as_ram.S

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@@ -2,6 +2,7 @@ config CPU_INTEL_SOCKET_P
bool
select CPU_INTEL_MODEL_1067X
select CPU_INTEL_MODEL_6FX
select CPU_X86_CACHE_HELPER
select MMX
select SSE

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@@ -1,7 +1,6 @@
subdirs-y += ../model_6fx
subdirs-y += ../model_1067x
subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
subdirs-y += ../microcode
subdirs-y += ../speedstep