mb/google/corsola: Initialize USB port 0

The default MT8186 platform is to initialize USB3 port 1.
Use option bit 27 in fw_config to enable initialization of USB2 port 0
to support devices mounted on it.

BUG=b:335124437
TEST=boot to OS from USB-A
     boot to OS from SD Card
BRANCH=corsola

Change-Id: I725b80593f5fc498a204bf47f943c36ccbd78134
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82089
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
This commit is contained in:
Wentao Qin
2024-04-19 17:49:11 +08:00
committed by Yu-Ping Wu
parent b566ce4aea
commit e282422c68
7 changed files with 43 additions and 5 deletions

View File

@@ -1,5 +1,9 @@
## SPDX-License-Identifier: GPL-2.0-only
fw_config
field SECONDARY_USB 27
option DISABLED 0
option ENABLED 1
end
field AUDIO_AMP 28 29
option AMP_ALC1019 0
option AMP_ALC5645 1

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@@ -53,6 +53,11 @@ static void mainboard_init(struct device *dev)
setup_usb_host();
if (fw_config_probe(FW_CONFIG(SECONDARY_USB, ENABLED))) {
/* Change host to USB2 port0 for initialization */
setup_usb_secondary_host();
}
if (!fw_config_is_provisioned() ||
fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_ALC1019)))
configure_alc1019();

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@@ -4,6 +4,7 @@
#define SOC_MEDIATEK_USB_COMMON_H
#include <stddef.h>
#include <stdint.h>
/* ip_pw_ctrl0 */
#define CTRL0_IP_SW_RST (0x1 << 0)
@@ -162,5 +163,7 @@ void mtk_usb_prepare(void);
void mtk_usb_adjust_phy_shift(void);
void setup_usb_host(void);
void update_usb_base_regs(uintptr_t ippc_base, uintptr_t sif_base);
void setup_usb_secondary_host(void);
void setup_usb_host_controller(void);
#endif

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@@ -13,6 +13,12 @@
static struct ssusb_ippc_regs *ippc_regs = (void *)(SSUSB_IPPC_BASE);
static struct ssusb_sif_port *phy_ports = (void *)(SSUSB_SIF_BASE);
void update_usb_base_regs(uintptr_t ippc_base, uintptr_t sif_base)
{
ippc_regs = (void *)ippc_base;
phy_ports = (void *)sif_base;
}
static void phy_index_power_on(int index)
{
struct ssusb_sif_port *phy = phy_ports + index;
@@ -150,7 +156,7 @@ __weak void mtk_usb_adjust_phy_shift(void)
/* do nothing */
}
void setup_usb_host(void)
void setup_usb_host_controller(void)
{
u3p_msg("Setting up USB HOST controller...\n");
@@ -164,3 +170,9 @@ void setup_usb_host(void)
mtk_usb_adjust_phy_shift();
u3p_msg("phy power-on done.\n");
}
void setup_usb_host(void)
{
update_usb_base_regs(SSUSB_IPPC_BASE, SSUSB_SIF_BASE);
setup_usb_host_controller();
}

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@@ -0,0 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/addressmap.h>
#include <soc/usb.h>
void setup_usb_secondary_host(void)
{
/* We always consider USB2 port as the secondary UBS host regardless of the
register naming */
update_usb_base_regs(SSUSB_IPPC_BASE_P0, SSUSB_SIF_BASE_P0);
setup_usb_host_controller();
}

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@@ -51,7 +51,7 @@ ramstage-y += soc.c
ramstage-y += ../common/spm.c spm.c
ramstage-y += ../common/sspm.c
ramstage-y += ../common/tps65132s.c
ramstage-y += ../common/usb.c usb.c
ramstage-y += ../common/usb.c ../common/usb_secondary.c usb.c
CPPFLAGS_common += -Isrc/soc/mediatek/mt8186/include
CPPFLAGS_common += -Isrc/soc/mediatek/common/dp/include

View File

@@ -76,11 +76,13 @@ enum {
SPI5_BASE = IO_PHYS + 0x01015000,
I2C5_BASE = IO_PHYS + 0x01016000,
I2C9_BASE = IO_PHYS + 0x01019000,
/* Corsola uses USB2 port1 instead of USB2 port0. */
/* IPPC_BASE is for USB2 port1, IPPC_BASE_P0 is for USB2 port0 */
SSUSB_IPPC_BASE_P0 = IO_PHYS + 0x01203E00,
SSUSB_IPPC_BASE = IO_PHYS + 0x01283E00,
MSDC0_BASE = IO_PHYS + 0x01230000,
/* Corsola uses USB2 port1 instead of USB2 port0. */
/* SIF_BASE is for USB2 port1, SIF_BASE_P0 is for USB2 port0 */
SSUSB_SIF_BASE = IO_PHYS + 0x01C80300,
SSUSB_SIF_BASE_P0 = IO_PHYS + 0x01CA0300,
EFUSEC_BASE = IO_PHYS + 0x01CB0000,
MIPITX_BASE = IO_PHYS + 0x01CC0000,
MSDC0_TOP_BASE = IO_PHYS + 0x01CD0000,