Merge remote-tracking branch 'upstream/master' into galp5

Change-Id: I13cd0997db873191951e5c74c819b00acbbf1e89

src/acpi/acpi.c

@@ -468,7 +468,7 @@ void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id)
 	{
 		struct device *dev;
 		for (dev = all_devices; dev; dev = dev->next)
-			if (dev->ops && dev->ops->acpi_fill_ssdt)
+			if (dev->enabled && dev->ops && dev->ops->acpi_fill_ssdt)
 				dev->ops->acpi_fill_ssdt(dev);
 		current = (unsigned long) acpigen_get_current();
 	}

src/acpi/acpigen.c

@@ -10,6 +10,8 @@
 
 #define ACPIGEN_MAXLEN 0xfffff
 
+#define CPPC_PACKAGE_NAME "GCPC"
+
 #include <lib.h>
 #include <string.h>
 #include <acpi/acpigen.h>
@@ -340,7 +342,7 @@ void acpigen_write_scope(const char *name)
 
 void acpigen_get_package_op_element(uint8_t package_op, unsigned int element, uint8_t dest_op)
 {
-	/* <dest_op> = DeRefOf (<package_op>[<element]) */
+	/* <dest_op> = DeRefOf (<package_op>[<element>]) */
 	acpigen_write_store();
 	acpigen_emit_byte(DEREF_OP);
 	acpigen_emit_byte(INDEX_OP);
@@ -350,6 +352,52 @@ void acpigen_get_package_op_element(uint8_t package_op, unsigned int element, ui
 	acpigen_emit_byte(dest_op);
 }
 
+void acpigen_set_package_op_element_int(uint8_t package_op, unsigned int element, uint64_t src)
+{
+	/* DeRefOf (<package>[<element>]) = <src> */
+	acpigen_write_store();
+	acpigen_write_integer(src);
+	acpigen_emit_byte(DEREF_OP);
+	acpigen_emit_byte(INDEX_OP);
+	acpigen_emit_byte(package_op);
+	acpigen_write_integer(element);
+	acpigen_emit_byte(ZERO_OP); /* Ignore Index() Destination */
+}
+
+void acpigen_get_package_element(const char *package, unsigned int element, uint8_t dest_op)
+{
+	/* <dest_op> = <package>[<element>] */
+	acpigen_write_store();
+	acpigen_emit_byte(INDEX_OP);
+	acpigen_emit_namestring(package);
+	acpigen_write_integer(element);
+	acpigen_emit_byte(ZERO_OP); /* Ignore Index() Destination */
+	acpigen_emit_byte(dest_op);
+}
+
+void acpigen_set_package_element_int(const char *package, unsigned int element, uint64_t src)
+{
+	/* <package>[<element>] = <src> */
+	acpigen_write_store();
+	acpigen_write_integer(src);
+	acpigen_emit_byte(INDEX_OP);
+	acpigen_emit_namestring(package);
+	acpigen_write_integer(element);
+	acpigen_emit_byte(ZERO_OP); /* Ignore Index() Destination */
+}
+
+void acpigen_set_package_element_namestr(const char *package, unsigned int element,
+					 const char *src)
+{
+	/* <package>[<element>] = <src> */
+	acpigen_write_store();
+	acpigen_emit_namestring(src);
+	acpigen_emit_byte(INDEX_OP);
+	acpigen_emit_namestring(package);
+	acpigen_write_integer(element);
+	acpigen_emit_byte(ZERO_OP); /* Ignore Index() Destination */
+}
+
 void acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len)
 {
 /*
@@ -1318,6 +1366,14 @@ void acpigen_write_debug_op(uint8_t op)
 	acpigen_emit_ext_op(DEBUG_OP);
 }
 
+/* Store (str, DEBUG) */
+void acpigen_write_debug_namestr(const char *str)
+{
+	acpigen_write_store();
+	acpigen_emit_namestring(str);
+	acpigen_emit_ext_op(DEBUG_OP);
+}
+
 void acpigen_write_if(void)
 {
 	acpigen_emit_byte(IF_OP);
@@ -1453,6 +1509,12 @@ void acpigen_write_return_integer(uint64_t arg)
 	acpigen_write_integer(arg);
 }
 
+void acpigen_write_return_namestr(const char *arg)
+{
+	acpigen_emit_byte(RETURN_OP);
+	acpigen_emit_namestring(arg);
+}
+
 void acpigen_write_return_string(const char *arg)
 {
 	acpigen_emit_byte(RETURN_OP);
@@ -1578,8 +1640,6 @@ void acpigen_write_dsm_uuid_arr(struct dsm_uuid *ids, size_t count)
 	acpigen_pop_len();	/* Method _DSM */
 }
 
-#define CPPC_PACKAGE_NAME "\\GCPC"
-
 void acpigen_write_CPPC_package(const struct cppc_config *config)
 {
 	u32 i;
@@ -1621,9 +1681,12 @@ void acpigen_write_CPPC_package(const struct cppc_config *config)
 
 void acpigen_write_CPPC_method(void)
 {
+	char pscope[16];
+	snprintf(pscope, sizeof(pscope), CONFIG_ACPI_CPU_STRING "." CPPC_PACKAGE_NAME, 0);
+
 	acpigen_write_method("_CPC", 0);
 	acpigen_emit_byte(RETURN_OP);
-	acpigen_emit_namestring(CPPC_PACKAGE_NAME);
+	acpigen_emit_namestring(pscope);
 	acpigen_pop_len();
 }
 
@@ -2095,3 +2158,35 @@ void acpigen_write_xpss_object(const struct acpi_xpss_sw_pstate *pstate_values,
 
 	acpigen_pop_len();
 }
+
+/* Delay up to wait_ms until provided namestr matches expected value. */
+void acpigen_write_delay_until_namestr_int(uint32_t wait_ms, const char *name, uint64_t value)
+{
+	uint32_t wait_ms_segment = 1;
+	uint32_t segments = wait_ms;
+
+	/* Sleep in 16ms segments if delay is more than 32ms. */
+	if (wait_ms > 32) {
+		wait_ms_segment = 16;
+		segments = wait_ms / 16;
+	}
+
+	acpigen_write_store_int_to_op(segments, LOCAL7_OP);
+	acpigen_emit_byte(WHILE_OP);
+	acpigen_write_len_f();
+	acpigen_emit_byte(LGREATER_OP);
+	acpigen_emit_byte(LOCAL7_OP);
+	acpigen_emit_byte(ZERO_OP);
+
+	/* If name is not provided then just delay in a loop. */
+	if (name) {
+		acpigen_write_if_lequal_namestr_int(name, value);
+		acpigen_emit_byte(BREAK_OP);
+		acpigen_pop_len(); /* If */
+	}
+
+	acpigen_write_sleep(wait_ms_segment);
+	acpigen_emit_byte(DECREMENT_OP);
+	acpigen_emit_byte(LOCAL7_OP);
+	acpigen_pop_len(); /* While */
+}

src/console/Kconfig

@@ -58,6 +58,14 @@ if CONSOLE_SERIAL
 	comment "device-specific UART"
 	depends on HAVE_UART_SPECIAL
 
+config OVERRIDE_UART_FOR_CONSOLE
+	bool
+	help
+	  Set to "y" when the platform overrides the index of uart port by providing
+	  a get_uart_for_console routine.
+
+if !OVERRIDE_UART_FOR_CONSOLE
+
 config UART_FOR_CONSOLE
 	int
 	prompt "Index for UART port to use for console" if !FIXED_UART_FOR_CONSOLE
@@ -87,6 +95,8 @@ depends on DRIVERS_UART_8250IO && UART_FOR_CONSOLE = 2
 comment "Serial port base address = 0x2e8"
 depends on DRIVERS_UART_8250IO && UART_FOR_CONSOLE = 3
 
+endif
+
 config UART_OVERRIDE_BAUDRATE
 	bool
 	help

src/cpu/intel/fit/Kconfig

@@ -5,7 +5,7 @@ config CPU_INTEL_FIRMWARE_INTERFACE_TABLE
 
 config CPU_INTEL_NUM_FIT_ENTRIES
 	int
-	default 16 if INTEL_TXT
+	default 16 if INTEL_TXT || INTEL_CBNT_SUPPORT
 	default 4
 	depends on CPU_INTEL_FIRMWARE_INTERFACE_TABLE
 	help

src/cpu/intel/haswell/haswell.h

@@ -76,6 +76,26 @@
 #define MSR_CONFIG_TDP_CONTROL		0x64b
 #define MSR_TURBO_ACTIVATION_RATIO	0x64c
 
+#define SMM_MCA_CAP_MSR			0x17d
+#define   SMM_CPU_SVRSTR_BIT		57
+#define   SMM_CPU_SVRSTR_MASK		(1 << (SMM_CPU_SVRSTR_BIT - 32))
+
+#define MSR_PRMRR_PHYS_BASE		0x1f4
+#define MSR_PRMRR_PHYS_MASK		0x1f5
+#define MSR_UNCORE_PRMRR_PHYS_BASE	0x2f4
+#define MSR_UNCORE_PRMRR_PHYS_MASK	0x2f5
+
+#define SMM_FEATURE_CONTROL_MSR		0x4e0
+#define   SMM_CPU_SAVE_EN		(1 << 1)
+
+/* SMM save state MSRs */
+#define SMBASE_MSR			0xc20
+#define IEDBASE_MSR			0xc22
+
+/* MTRR_CAP_MSR bit definitions */
+#define SMRR_SUPPORTED			(1 << 11)
+#define PRMRR_SUPPORTED			(1 << 12)
+
 /* P-state configuration */
 #define PSS_MAX_ENTRIES			8
 #define PSS_RATIO_STEP			2

src/cpu/intel/haswell/smmrelocate.c

@@ -17,22 +17,6 @@
 #include <smp/node.h>
 #include "haswell.h"
 
-#define MSR_PRMRR_PHYS_BASE 0x1f4
-#define MSR_PRMRR_PHYS_MASK 0x1f5
-#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4
-#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5
-#define SMM_MCA_CAP_MSR 0x17d
-#define   SMM_CPU_SVRSTR_BIT 57
-#define   SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32))
-#define SMM_FEATURE_CONTROL_MSR 0x4e0
-#define   SMM_CPU_SAVE_EN (1 << 1)
-/* SMM save state MSRs */
-#define SMBASE_MSR 0xc20
-#define IEDBASE_MSR 0xc22
-
-#define SMRR_SUPPORTED (1 << 11)
-#define PRMRR_SUPPORTED (1 << 12)
-
 static void update_save_state(int cpu, uintptr_t curr_smbase,
 				uintptr_t staggered_smbase,
 				struct smm_relocation_params *relo_params)

src/cpu/intel/model_206ax/model_206ax_init.c

@@ -18,6 +18,7 @@
 #include "chip.h"
 #include <cpu/intel/smm_reloc.h>
 #include <cpu/intel/common/common.h>
+#include <smbios.h>
 
 /*
  * List of supported C-states in this processor
@@ -360,6 +361,25 @@ static void set_max_ratio(void)
 	       ((perf_ctl.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK);
 }
 
+unsigned int smbios_cpu_get_max_speed_mhz(void)
+{
+	msr_t msr;
+	msr = rdmsr(MSR_TURBO_RATIO_LIMIT);
+	return (msr.lo & 0xff) * SANDYBRIDGE_BCLK;
+}
+
+unsigned int smbios_cpu_get_current_speed_mhz(void)
+{
+	msr_t msr;
+	msr = rdmsr(MSR_PLATFORM_INFO);
+	return ((msr.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK;
+}
+
+unsigned int smbios_processor_external_clock(void)
+{
+	return SANDYBRIDGE_BCLK;
+}
+
 static void configure_mca(void)
 {
 	msr_t msr;

src/cpu/intel/smm/gen1/smmrelocate.c

@@ -59,8 +59,8 @@ static void write_smrr_alt(struct smm_relocation_params *relo_params)
 	printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
 	       relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
 
-	wrmsr(MSR_SMRR_PHYS_BASE, relo_params->smrr_base);
-	wrmsr(MSR_SMRR_PHYS_MASK, relo_params->smrr_mask);
+	wrmsr(CORE2_SMRR_PHYS_BASE, relo_params->smrr_base);
+	wrmsr(CORE2_SMRR_PHYS_MASK, relo_params->smrr_mask);
 }
 
 static void fill_in_relocation_params(struct smm_relocation_params *params)

src/cpu/x86/smm/Makefile.inc

@@ -32,6 +32,8 @@ ifeq ($(CONFIG_HAVE_SMI_HANDLER),y)
 ramstage-srcs += $(obj)/cpu/x86/smm/smm.manual
 endif
 
+smm-y += save_state.c
+
 ifeq ($(CONFIG_SMM_TSEG),y)
 
 ramstage-y += tseg_region.c

src/cpu/x86/smm/save_state.c

@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cpu/x86/smm.h>
+#include <cpu/x86/save_state.h>
+
+/* These are weakly linked such that platforms can link only the save state
+   ops they actually require. */
+const struct smm_save_state_ops *legacy_ops __weak = NULL;
+const struct smm_save_state_ops *em64t100_ops __weak = NULL;
+const struct smm_save_state_ops *em64t101_ops __weak = NULL;
+const struct smm_save_state_ops *amd64_ops __weak = NULL;
+
+static const struct smm_save_state_ops *save_state;
+
+/* Returns -1 on failure, 0 on success */
+static int init_save_state(void)
+{
+	const uint32_t revision = smm_revision();
+	int i;
+	static bool initialized = false;
+	const struct smm_save_state_ops *save_state_ops[] = {
+		legacy_ops,
+		em64t100_ops,
+		em64t101_ops,
+		amd64_ops,
+	};
+
+	if (initialized)
+		return 0;
+
+	for (i = 0; i < ARRAY_SIZE(save_state_ops); i++) {
+		const struct smm_save_state_ops *ops = save_state_ops[i];
+		const uint32_t *rev;
+
+		if (ops == NULL)
+			continue;
+
+		for (rev = ops->revision_table; *rev != SMM_REV_INVALID; rev++)
+			if (*rev == revision) {
+				save_state = ops;
+				initialized = true;
+				return 0;
+			}
+	}
+
+	return -1;
+}
+
+int get_apmc_node(u8 cmd)
+{
+	if (init_save_state())
+		return -1;
+
+	return save_state->apmc_node(cmd);
+}
+
+int get_save_state_reg(const enum cpu_reg reg, const int node, void *out, const uint8_t length)
+{
+	if (init_save_state())
+		return -1;
+
+	if (node > CONFIG_MAX_CPUS)
+		return -1;
+
+	return save_state->get_reg(reg, node, out, length);
+}
+
+int set_save_state_reg(const enum cpu_reg reg, const int node, void *in, const uint8_t length)
+{
+	if (init_save_state())
+		return -1;
+
+	if (node > CONFIG_MAX_CPUS)
+		return -1;
+
+	return save_state->set_reg(reg, node, in, length);
+}

src/cpu/x86/smm/smihandler.c

@@ -14,23 +14,6 @@
 #include <spi-generic.h>
 #endif
 
-typedef enum {
-	AMD64,
-	EM64T100,
-	EM64T101,
-	LEGACY
-} save_state_type_t;
-
-typedef struct {
-	save_state_type_t type;
-	union {
-	amd64_smm_state_save_area_t *amd64_state_save;
-	em64t100_smm_state_save_area_t *em64t100_state_save;
-	em64t101_smm_state_save_area_t *em64t101_state_save;
-	legacy_smm_state_save_area_t *legacy_state_save;
-	};
-} smm_state_save_area_t;
-
 static int do_driver_init = 1;
 
 typedef enum { SMI_LOCKED, SMI_UNLOCKED } smi_semaphore;
@@ -162,9 +145,6 @@ bool smm_region_overlaps_handler(const struct region *r)
 void smi_handler(void)
 {
 	unsigned int node;
-	const uint32_t smm_rev = smm_revision();
-	smm_state_save_area_t state_save;
-	u32 smm_base = SMM_BASE; /* ASEG */
 
 	/* Are we ok to execute the handler? */
 	if (!smi_obtain_lock()) {
@@ -190,36 +170,10 @@ void smi_handler(void)
 
 	printk(BIOS_SPEW, "\nSMI# #%d\n", node);
 
-	switch (smm_rev) {
-	case 0x00030002:
-	case 0x00030007:
-		state_save.type = LEGACY;
-		state_save.legacy_state_save =
-			smm_save_state(smm_base,
-				       SMM_LEGACY_ARCH_OFFSET, node);
-		break;
-	case 0x00030100:
-		state_save.type = EM64T100;
-		state_save.em64t100_state_save =
-			smm_save_state(smm_base,
-				       SMM_EM64T100_ARCH_OFFSET, node);
-		break;
-	case 0x00030101: /* SandyBridge, IvyBridge, and Haswell */
-		state_save.type = EM64T101;
-		state_save.em64t101_state_save =
-			smm_save_state(smm_base,
-				       SMM_EM64T101_ARCH_OFFSET, node);
-		break;
-	case 0x00020064:
-	case 0x00030064:
-		state_save.type = AMD64;
-		state_save.amd64_state_save =
-			smm_save_state(smm_base,
-				       SMM_AMD64_ARCH_OFFSET, node);
-		break;
-	default:
-		printk(BIOS_DEBUG, "smm_revision: 0x%08x\n", smm_rev);
-		printk(BIOS_DEBUG, "SMI# not supported on your CPU\n");
+	/* Use smm_get_save_state() to see if the smm revision is supported */
+	if (smm_get_save_state(node) == NULL) {
+		printk(BIOS_WARNING, "smm_revision: 0x%08x\n", smm_revision());
+		printk(BIOS_WARNING, "SMI# not supported on your CPU\n");
 		/* Don't release lock, so no further SMI will happen,
 		 * if we don't handle it anyways.
 		 */

src/cpu/x86/smm/smm.ld

@@ -2,6 +2,9 @@
 
 /* Maximum number of CPUs/cores */
 CPUS = 4;
+
+_ = ASSERT(CPUS >= CONFIG_MAX_CPUS, "The ASEG SMM code only supports up to 4 CPUS");
+
 ENTRY(smm_handler_start);
 
 SECTIONS

src/device/pci_device.c

@@ -1648,21 +1648,3 @@ void pci_dev_disable_bus_master(const struct device *dev)
 	pci_update_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MASTER, 0x0);
 }
 #endif
-
-bool pci_dev_is_wake_source(const struct device *dev)
-{
-	unsigned int pm_cap;
-	uint16_t pmcs;
-
-	if (dev->path.type != DEVICE_PATH_PCI)
-		return false;
-
-	pm_cap = pci_find_capability(dev, PCI_CAP_ID_PM);
-	if (!pm_cap)
-		return false;
-
-	pmcs = pci_read_config16(dev, pm_cap + PCI_PM_CTRL);
-
-	/* PCI Device is a wake source if PME_ENABLE and PME_STATUS are set in PMCS register. */
-	return (pmcs & PCI_PM_CTRL_PME_ENABLE) && (pmcs & PCI_PM_CTRL_PME_STATUS);
-}

src/device/pci_ops.c

@@ -78,3 +78,21 @@ void __noreturn pcidev_die(void)
 {
 	die("PCI: dev is NULL!\n");
 }
+
+bool pci_dev_is_wake_source(const struct device *dev)
+{
+	unsigned int pm_cap;
+	uint16_t pmcs;
+
+	if (dev->path.type != DEVICE_PATH_PCI)
+		return false;
+
+	pm_cap = pci_find_capability(dev, PCI_CAP_ID_PM);
+	if (!pm_cap)
+		return false;
+
+	pmcs = pci_s_read_config16(PCI_BDF(dev), pm_cap + PCI_PM_CTRL);
+
+	/* PCI Device is a wake source if PME_ENABLE and PME_STATUS are set in PMCS register. */
+	return (pmcs & PCI_PM_CTRL_PME_ENABLE) && (pmcs & PCI_PM_CTRL_PME_STATUS);
+}

src/drivers/generic/adau7002/adau7002.c

@@ -17,7 +17,7 @@ static void adau7002_fill_ssdt(const struct device *dev)
 	struct drivers_generic_adau7002_config *config;
 	struct acpi_dp *dp;
 
-	if (!dev || !dev->enabled)
+	if (!dev)
 		return;
 
 	const char *scope = acpi_device_scope(dev);

src/drivers/generic/gpio_keys/gpio_keys.c

@@ -57,7 +57,7 @@ static void gpio_keys_fill_ssdt_generator(const struct device *dev)
 	const char *drv_string = config->is_polled ? "gpio-keys-polled"
 				: "gpio-keys";
 
-	if (!dev->enabled || !scope || !path || !config->gpio.pin_count)
+	if (!scope || !path || !config->gpio.pin_count)
 		return;
 
 	/* Device */

src/drivers/generic/max98357a/max98357a.c

@@ -18,7 +18,7 @@ static void max98357a_fill_ssdt(const struct device *dev)
 	const char *path;
 	struct acpi_dp *dp;
 
-	if (!dev->enabled || !config)
+	if (!config)
 		return;
 
 	const char *scope = acpi_device_scope(dev);

src/drivers/gfx/generic/generic.c

@@ -106,7 +106,7 @@ static void gfx_fill_ssdt_generator(const struct device *dev)
 
 	const char *scope = acpi_device_scope(dev);
 
-	if (!scope || !dev->enabled)
+	if (!scope)
 		return;
 
 	acpigen_write_scope(scope);

src/drivers/i2c/da7219/da7219.c

@@ -27,7 +27,7 @@ static void da7219_fill_ssdt(const struct device *dev)
 	};
 	struct acpi_dp *dsd, *aad;
 
-	if (!dev->enabled || !scope)
+	if (!scope)
 		return;
 
 	/* Device */

src/drivers/i2c/designware/dw_i2c.c

@@ -824,9 +824,6 @@ void dw_i2c_acpi_fill_ssdt(const struct device *dev)
 	const char *path;
 	unsigned int speed;
 
-	if (!dev->enabled)
-		return;
-
 	bus = dw_i2c_soc_dev_to_bus(dev);
 
 	if (bus < 0)

src/drivers/i2c/generic/generic.c

@@ -57,7 +57,7 @@ void i2c_generic_fill_ssdt(const struct device *dev,
 	int reset_gpio_index = -1, enable_gpio_index = -1, irq_gpio_index = -1;
 	const char *path = acpi_device_path(dev);
 
-	if (!dev->enabled || !scope)
+	if (!scope)
 		return;
 
 	if (!config->hid) {

src/drivers/i2c/gpiomux/bus/bus.c

@@ -22,7 +22,7 @@ static void i2c_gpiomux_bus_fill_ssdt(const struct device *dev)
 	const char *scope = acpi_device_scope(dev);
 	const char *path = acpi_device_path(dev);
 
-	if (!dev || !dev->enabled || !scope || !path)
+	if (!dev || !scope || !path)
 		return;
 
 	/* Device */

src/drivers/i2c/gpiomux/mux/mux.c

@@ -27,7 +27,7 @@ static void i2c_gpiomux_mux_fill_ssdt(const struct device *dev)
 	struct acpi_gpio_res_params param[MAX_NUM_MUX_GPIOS];
 	int i;
 
-	if (!dev->enabled || !scope || !path)
+	if (!scope || !path)
 		return;
 
 	/* Device */

src/drivers/i2c/max98373/max98373.c

@@ -24,7 +24,7 @@ static void max98373_fill_ssdt(const struct device *dev)
 	};
 	struct acpi_dp *dp;
 
-	if (!dev->enabled || !scope) {
+	if (!scope) {
 		printk(BIOS_ERR, "%s: dev not enabled\n", __func__);
 		return;
 	}

src/drivers/i2c/max98390/max98390.c

@@ -28,7 +28,7 @@ static void max98390_fill_ssdt(const struct device *dev)
 	struct acpi_dp *dp;
 	uint64_t r0_value, temp_value;
 
-	if (!dev->enabled || !scope)
+	if (!scope)
 		return;
 
 	/* Device */

src/drivers/i2c/max98927/max98927.c

@@ -24,7 +24,7 @@ static void max98927_fill_ssdt(const struct device *dev)
 	};
 	struct acpi_dp *dp;
 
-	if (!dev->enabled || !scope)
+	if (!scope)
 		return;
 
 	/* Device */

src/drivers/i2c/nau8825/nau8825.c

@@ -30,7 +30,7 @@ static void nau8825_fill_ssdt(const struct device *dev)
 	};
 	struct acpi_dp *dp = NULL;
 
-	if (!dev->enabled || !scope)
+	if (!scope)
 		return;
 	if (config->sar_threshold_num > NAU8825_MAX_BUTTONS)
 		return;

src/drivers/i2c/rt1011/rt1011.c

@@ -28,7 +28,7 @@ static void rt1011_fill_ssdt(const struct device *dev)
 	struct acpi_dp *dp;
 	uint64_t r0_value, temp_value;
 
-	if (!dev->enabled || !scope)
+	if (!scope)
 		return;
 
 	/* Device */

src/drivers/i2c/rt5663/rt5663.c

@@ -27,7 +27,7 @@ static void rt5663_fill_ssdt(const struct device *dev)
 	};
 	struct acpi_dp *dp;
 
-	if (!dev->enabled || !scope)
+	if (!scope)
 		return;
 
 	/* Device */

src/drivers/i2c/rx6110sa/chip.h

@@ -3,6 +3,7 @@
 #include "rx6110sa.h"
 
 struct drivers_i2c_rx6110sa_config {
+	unsigned int bus_speed;		/* Bus clock in Hz (default 400 kHz)*/
 	/* The day (of the week) is indicated by 7 bits, bit 0 to bit 6. */
 	unsigned char user_weekday;	/* User day of the week to set */
 	unsigned char user_day;		/* User day to set */

src/drivers/i2c/rx6110sa/rx6110sa.c

@@ -1,7 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <device/i2c_bus.h>
+#include <acpi/acpi_device.h>
+#include <acpi/acpigen.h>
 #include <device/device.h>
+#include <device/i2c.h>
+#include <device/i2c_bus.h>
 #include <version.h>
 #include <console/console.h>
 #include <bcd.h>
@@ -163,11 +166,71 @@ static void rx6110sa_init(struct device *dev)
 	rx6110sa_write(dev, CTRL_REG, reg);
 }
 
+#if CONFIG(HAVE_ACPI_TABLES)
+static void rx6110sa_fill_ssdt(const struct device *dev)
+{
+	struct drivers_i2c_rx6110sa_config *config = dev->chip_info;
+	const char *scope = acpi_device_scope(dev);
+	enum i2c_speed bus_speed;
+
+	if (!scope)
+		return;
+
+	switch (config->bus_speed) {
+	case I2C_SPEED_STANDARD:
+	case I2C_SPEED_FAST:
+		bus_speed = config->bus_speed;
+		break;
+	default:
+		printk(BIOS_INFO, "%s: Bus speed unsupported, fall back to %d kHz!\n",
+			dev_path(dev), I2C_SPEED_STANDARD / 1000);
+		bus_speed = I2C_SPEED_STANDARD;
+		break;
+	}
+
+	struct acpi_i2c i2c = {
+		.address = dev->path.i2c.device,
+		.mode_10bit = dev->path.i2c.mode_10bit,
+		.speed = bus_speed,
+		.resource = scope,
+	};
+
+	/* Device */
+	acpigen_write_scope(scope);
+	acpigen_write_device(acpi_device_name(dev));
+	acpigen_write_name_string("_HID", RX6110SA_HID_NAME);
+	acpigen_write_name_string("_DDN", RX6110SA_HID_DESC);
+	acpigen_write_STA(acpi_device_status(dev));
+
+	/* Resources */
+	acpigen_write_name("_CRS");
+	acpigen_write_resourcetemplate_header();
+	acpi_device_write_i2c(&i2c);
+
+	acpigen_write_resourcetemplate_footer();
+
+	acpigen_pop_len(); /* Device */
+	acpigen_pop_len(); /* Scope */
+
+	printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev),
+			dev->chip_ops->name, dev_path(dev));
+}
+
+static const char *rx6110sa_acpi_name(const struct device *dev)
+{
+	return RX6110SA_ACPI_NAME;
+}
+#endif
+
 static struct device_operations rx6110sa_ops = {
 	.read_resources		= noop_read_resources,
 	.set_resources		= noop_set_resources,
 	.init			= rx6110sa_init,
-	.final			= rx6110sa_final
+	.final			= rx6110sa_final,
+#if CONFIG(HAVE_ACPI_TABLES)
+	.acpi_name		= rx6110sa_acpi_name,
+	.acpi_fill_ssdt		= rx6110sa_fill_ssdt,
+#endif
 };
 
 static void rx6110sa_enable(struct device *dev)

src/drivers/i2c/rx6110sa/rx6110sa.h

@@ -3,9 +3,9 @@
 #ifndef _I2C_RX6110SA_H_
 #define _I2C_RX6110SA_H_
 
-/* The address of this RTC is fixed. */
-#define RX6110SA_SLAVE_ADR		0x32
-#define RX6110SA_I2C_CONTROLLER		0
+#define RX6110SA_ACPI_NAME		"ERX6"
+#define RX6110SA_HID_NAME		"RX6110SA"
+#define RX6110SA_HID_DESC		"Real Time Clock"
 
 /* Register layout */
 #define SECOND_REG			0x10

src/drivers/i2c/sx9310/sx9310.c

@@ -28,7 +28,7 @@ static void i2c_sx9310_fill_ssdt(const struct device *dev)
 	};
 	struct acpi_dp *dsd;
 
-	if (!dev->enabled || !scope || !config)
+	if (!scope || !config)
 		return;
 
 	if (config->speed)

src/drivers/i2c/tpm/chip.c

@@ -20,7 +20,7 @@ static void i2c_tpm_fill_ssdt(const struct device *dev)
 		.resource = scope,
 	};
 
-	if (!dev->enabled || !scope)
+	if (!scope)
 		return;
 
 	if (!config->hid) {

src/drivers/intel/fsp1_1/romstage.c

@@ -41,35 +41,29 @@ static void raminit_common(struct romstage_params *params)
 	params->saved_data_size = 0;
 	params->saved_data = NULL;
 	if (!params->disable_saved_data) {
-		if (vboot_recovery_mode_enabled()) {
-			/* Recovery mode does not use MRC cache */
+		/* Assume boot device is memory mapped. */
+		assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
+
+		params->saved_data = NULL;
+		if (CONFIG(CACHE_MRC_SETTINGS))
+			params->saved_data =
+				mrc_cache_current_mmap_leak(MRC_TRAINING_DATA,
+							    params->fsp_version,
+							    &mrc_size);
+		if (params->saved_data) {
+			/* MRC cache found */
+			params->saved_data_size = mrc_size;
+
+		} else if (s3wake) {
+			/* Waking from S3 and no cache. */
 			printk(BIOS_DEBUG,
-			       "Recovery mode: not using MRC cache.\n");
+			       "No MRC cache "
+			       "found in S3 resume path.\n");
+			post_code(POST_RESUME_FAILURE);
+			/* FIXME: A "system" reset is likely enough: */
+			full_reset();
 		} else {
-			/* Assume boot device is memory mapped. */
-			assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
-
-			params->saved_data = NULL;
-			if (CONFIG(CACHE_MRC_SETTINGS))
-				params->saved_data =
-					mrc_cache_current_mmap_leak(MRC_TRAINING_DATA,
-								    params->fsp_version,
-								    &mrc_size);
-			if (params->saved_data) {
-				/* MRC cache found */
-				params->saved_data_size = mrc_size;
-
-			} else if (s3wake) {
-				/* Waking from S3 and no cache. */
-				printk(BIOS_DEBUG,
-				       "No MRC cache "
-				       "found in S3 resume path.\n");
-				post_code(POST_RESUME_FAILURE);
-				/* FIXME: A "system" reset is likely enough: */
-				full_reset();
-			} else {
-				printk(BIOS_DEBUG, "No MRC cache found.\n");
-			}
+			printk(BIOS_DEBUG, "No MRC cache found.\n");
 		}
 	}
 

src/drivers/intel/fsp2_0/memory_init.c

@@ -92,18 +92,6 @@ static void fsp_fill_mrc_cache(FSPM_ARCH_UPD *arch_upd, uint32_t fsp_version)
 	if (!CONFIG(CACHE_MRC_SETTINGS))
 		return;
 
-	/*
-	 * In recovery mode, force retraining:
-	 * 1. Recovery cache is not supported, or
-	 * 2. Memory retrain switch is set.
-	 */
-	if (vboot_recovery_mode_enabled()) {
-		if (!CONFIG(HAS_RECOVERY_MRC_CACHE))
-			return;
-		if (get_recovery_mode_retrain_switch())
-			return;
-	}
-
 	/* Assume boot device is memory mapped. */
 	assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
 

src/drivers/intel/gma/Kconfig

@@ -59,6 +59,10 @@ config INTEL_GMA_SWSMISCI
 config INTEL_GMA_LIBGFXINIT_EDID
 	bool
 
+config VBT_DATA_SIZE_KB
+	int
+	default 8
+
 config GFX_GMA_ANALOG_I2C_HDMI_B
 	bool
 

src/drivers/intel/gma/opregion.c

@@ -19,7 +19,7 @@ const char *mainboard_vbt_filename(void)
 	return "vbt.bin";
 }
 
-static char vbt_data[9 * KiB];
+static char vbt_data[CONFIG_VBT_DATA_SIZE_KB * KiB];
 static size_t vbt_data_sz;
 
 void *locate_vbt(size_t *vbt_size)

src/drivers/intel/ish/ish.c

@@ -13,7 +13,7 @@ static void ish_fill_ssdt_generator(const struct device *dev)
 	struct device *root = dev->bus->dev;
 	struct acpi_dp *dsd;
 
-	if (!dev->enabled || !config || !config->firmware_name)
+	if (!config || !config->firmware_name)
 		return;
 
 	acpigen_write_scope(acpi_device_path(root));

src/drivers/intel/mipi_camera/camera.c

@@ -909,9 +909,6 @@ static void camera_fill_ssdt(const struct device *dev)
 	const char *scope = NULL;
 	const struct device *pdev;
 
-	if (!dev->enabled)
-		return;
-
 	if (config->has_power_resource) {
 		pdev = dev->bus->dev;
 		if (!pdev || !pdev->enabled)

src/drivers/intel/pmc_mux/conn/conn.c

@@ -32,9 +32,6 @@ static void conn_fill_ssdt(const struct device *dev)
 	const char *scope;
 	const char *name;
 
-	if (!dev->enabled)
-		return;
-
 	/* Reference the existing scope and write CONx device */
 	scope = acpi_device_scope(dev);
 	name = acpi_device_name(dev);

src/drivers/intel/soundwire/soundwire.c

@@ -50,7 +50,7 @@ static void intel_soundwire_fill_ssdt(const struct device *dev)
 	struct intel_soundwire_controller *controller;
 	const char *scope = acpi_device_scope(dev);
 
-	if (!dev->enabled || !scope)
+	if (!scope)
 		return;
 
 	if (soc_fill_soundwire_controller(&controller) < 0 || !controller)

src/drivers/intel/usb4/retimer/retimer.c

@@ -101,7 +101,7 @@ static void usb4_retimer_fill_ssdt(const struct device *dev)
 	const struct drivers_intel_usb4_retimer_config *config = dev->chip_info;
 	const char *scope = acpi_device_scope(dev);
 
-	if (!dev->enabled || !scope || !config)
+	if (!scope || !config)
 		return;
 
 	if (!config->power_gpio.pin_count) {

src/drivers/mrc_cache/Kconfig

@@ -17,11 +17,6 @@ config HAS_RECOVERY_MRC_CACHE
 	bool
 	default n
 
-config MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
-	bool
-	depends on VBOOT_STARTS_IN_BOOTBLOCK
-	default n
-
 config MRC_SETTINGS_VARIABLE_DATA
 	bool
 	default n

src/drivers/mrc_cache/mrc_cache.c

@@ -69,7 +69,20 @@ static const struct cache_region normal_training = {
 	.type = MRC_TRAINING_DATA,
 	.elog_slot = ELOG_MEM_CACHE_UPDATE_SLOT_NORMAL,
 	.tpm_hash_index = MRC_RW_HASH_NV_INDEX,
+#if CONFIG(VBOOT_STARTS_IN_ROMSTAGE)
+	/*
+	 * If VBOOT_STARTS_IN_ROMSTAGE is selected, this means that
+	 * memory training happens before vboot (in RO) and the
+	 * mrc_cache data is always safe to use.
+	 */
 	.flags = NORMAL_FLAG | RECOVERY_FLAG,
+#else
+	/*
+	 * If !VBOOT_STARTS_IN_ROMSTAGE, this means that memory training happens after
+	 * vboot (in RW code) and is never safe to use in recovery.
+	 */
+	.flags = NORMAL_FLAG,
+#endif
 };
 
 static const struct cache_region variable_data = {
@@ -78,7 +91,20 @@ static const struct cache_region variable_data = {
 	.type = MRC_VARIABLE_DATA,
 	.elog_slot = ELOG_MEM_CACHE_UPDATE_SLOT_VARIABLE,
 	.tpm_hash_index = 0,
+#if CONFIG(VBOOT_STARTS_IN_ROMSTAGE)
+	/*
+	 * If VBOOT_STARTS_IN_ROMSTAGE is selected, this means that
+	 * memory training happens before vboot (in RO) and the
+	 * mrc_cache data is always safe to use.
+	 */
 	.flags = NORMAL_FLAG | RECOVERY_FLAG,
+#else
+	/*
+	 * If !VBOOT_STARTS_IN_ROMSTAGE, this means that memory training happens after
+	 * vboot (in RW code) and is never safe to use in recovery.
+	 */
+	.flags = NORMAL_FLAG,
+#endif
 };
 
 /* Order matters here for priority in matching. */
@@ -255,6 +281,13 @@ static int mrc_cache_find_current(int type, uint32_t version,
 	const size_t md_size = sizeof(*md);
 	const bool fail_bad_data = true;
 
+	/*
+	 * In recovery mode, force retraining if the memory retrain
+	 * switch is set.
+	 */
+	if (vboot_recovery_mode_enabled() && get_recovery_mode_retrain_switch())
+		return -1;
+
 	cr = lookup_region(&region, type);
 
 	if (cr == NULL)
@@ -566,10 +599,24 @@ static void invalidate_normal_cache(void)
 	const char *name = DEFAULT_MRC_CACHE;
 	const uint32_t invalid = ~MRC_DATA_SIGNATURE;
 
-	/* Invalidate only on recovery mode with retraining enabled. */
+	/*
+	 * If !HAS_RECOVERY_MRC_CACHE and VBOOT_STARTS_IN_ROMSTAGE is
+	 * selected, this means that memory training occurs before
+	 * verified boot (in RO), so normal mode cache does not need
+	 * to be invalidated.
+	 */
+	if (!CONFIG(HAS_RECOVERY_MRC_CACHE) && CONFIG(VBOOT_STARTS_IN_ROMSTAGE))
+		return;
+
+	/* We only invalidate the normal cache in recovery mode. */
 	if (!vboot_recovery_mode_enabled())
 		return;
-	if (!get_recovery_mode_retrain_switch())
+
+	/*
+	 * For platforms with a recovery mrc_cache, no need to
+	 * invalidate when retrain switch is not set.
+	 */
+	if (CONFIG(HAS_RECOVERY_MRC_CACHE) && !get_recovery_mode_retrain_switch())
 		return;
 
 	if (fmap_locate_area_as_rdev_rw(name, &rdev) < 0) {
@@ -599,7 +646,7 @@ static void update_mrc_cache_from_cbmem(int type)
 	cr = lookup_region(&region, type);
 
 	if (cr == NULL) {
-		printk(BIOS_ERR, "MRC: could not find cache_region type %d\n", type);
+		printk(BIOS_INFO, "MRC: could not find cache_region type %d\n", type);
 		return;
 	}
 
@@ -631,8 +678,7 @@ static void finalize_mrc_cache(void *unused)
 			update_mrc_cache_from_cbmem(MRC_VARIABLE_DATA);
 	}
 
-	if (CONFIG(MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN))
-		invalidate_normal_cache();
+	invalidate_normal_cache();
 
 	protect_mrc_region();
 }
@@ -642,13 +688,6 @@ int mrc_cache_stash_data(int type, uint32_t version, const void *data,
 {
 	const struct cache_region *cr;
 
-	cr = lookup_region_type(type);
-	if (cr == NULL) {
-		printk(BIOS_ERR, "MRC: failed to add to cbmem for type %d.\n",
-			type);
-		return -1;
-	}
-
 	struct mrc_metadata md = {
 		.signature = MRC_DATA_SIGNATURE,
 		.data_size = size,
@@ -664,6 +703,13 @@ int mrc_cache_stash_data(int type, uint32_t version, const void *data,
 		size_t cbmem_size;
 		cbmem_size = sizeof(*cbmem_md) + size;
 
+		cr = lookup_region_type(type);
+		if (cr == NULL) {
+			printk(BIOS_INFO, "MRC: No region type found. Skip adding to cbmem for type %d.\n",
+				type);
+			return 0;
+		}
+
 		cbmem_md = cbmem_add(cr->cbmem_id, cbmem_size);
 
 		if (cbmem_md == NULL) {

src/drivers/soundwire/alc5682/alc5682.c

@@ -128,7 +128,7 @@ static void soundwire_alc5682_fill_ssdt(const struct device *dev)
 	const char *scope = acpi_device_scope(dev);
 	struct acpi_dp *dsd;
 
-	if (!dev->enabled || !scope)
+	if (!scope)
 		return;
 
 	acpigen_write_scope(scope);

src/drivers/soundwire/alc711/alc711.c

@@ -105,7 +105,7 @@ static void soundwire_alc711_fill_ssdt(const struct device *dev)
 	const char *scope = acpi_device_scope(dev);
 	struct acpi_dp *dsd;
 
-	if (!dev->enabled || !scope)
+	if (!scope)
 		return;
 
 	acpigen_write_scope(scope);

src/drivers/soundwire/max98373/max98373.c

@@ -114,7 +114,7 @@ static void soundwire_max98373_fill_ssdt(const struct device *dev)
 	const char *scope = acpi_device_scope(dev);
 	struct acpi_dp *dsd;
 
-	if (!dev->enabled || !scope)
+	if (!scope)
 		return;
 
 	acpigen_write_scope(scope);

src/drivers/spi/acpi/acpi.c

@@ -77,7 +77,7 @@ static void spi_acpi_fill_ssdt_generator(const struct device *dev)
 	int reset_gpio_index = -1;
 	int enable_gpio_index = -1;
 
-	if (!dev->enabled || !scope)
+	if (!scope)
 		return;
 
 	if (spi_acpi_get_bus(dev) == -1) {

src/drivers/uart/acpi/acpi.c

@@ -46,7 +46,7 @@ static void uart_acpi_fill_ssdt(const struct device *dev)
 	int reset_gpio_index = -1;
 	int enable_gpio_index = -1;
 
-	if (!dev->enabled || !scope)
+	if (!scope)
 		return;
 
 	if (!config->hid) {

src/drivers/usb/acpi/chip.h

@@ -44,7 +44,28 @@ struct drivers_usb_acpi_config {
 	bool use_custom_pld;
 	struct acpi_pld custom_pld;
 
+	/* Does the device have a power resource? */
+	bool has_power_resource;
+
+	/* GPIO used to take device out of reset or to put it into reset. */
 	struct acpi_gpio reset_gpio;
+	/* Delay to be inserted after device is taken out of reset. */
+	unsigned int reset_delay_ms;
+	/* Delay to be inserted after device is put into reset. */
+	unsigned int reset_off_delay_ms;
+	/* GPIO used to enable device. */
+	struct acpi_gpio enable_gpio;
+	/* Delay to be inserted after device is enabled. */
+	unsigned int enable_delay_ms;
+	/* Delay to be inserted after device is disabled. */
+	unsigned int enable_off_delay_ms;
+
+	/*
+	 * Define a GPIO that shows the privacy status of the USB device.
+	 * E.g. On a camera: if it is one, it is recording black frames.
+	 * E.g. On a mic: if it is one, it is recording white-noise.
+	 */
+	struct acpi_gpio privacy_gpio;
 };
 
 #endif /* __USB_ACPI_CHIP_H__ */

src/drivers/usb/acpi/usb_acpi.c

@@ -10,13 +10,27 @@
 
 static bool usb_acpi_add_gpios_to_crs(struct drivers_usb_acpi_config *cfg)
 {
-	/*
-	 * Return false if reset GPIO is not provided.
-	 */
-	if (cfg->reset_gpio.pin_count == 0)
-		return false;
+	if (cfg->privacy_gpio.pin_count)
+		return true;
 
-	return true;
+	if (cfg->reset_gpio.pin_count && !cfg->has_power_resource)
+		return true;
+
+	return false;
+}
+
+static int usb_acpi_write_gpio(struct acpi_gpio *gpio, int *curr_index)
+{
+	int ret = -1;
+
+	if (gpio->pin_count == 0)
+		return ret;
+
+	acpi_device_write_gpio(gpio);
+	ret = *curr_index;
+	(*curr_index)++;
+
+	return ret;
 }
 
 static void usb_acpi_fill_ssdt_generator(const struct device *dev)
@@ -24,7 +38,7 @@ static void usb_acpi_fill_ssdt_generator(const struct device *dev)
 	struct drivers_usb_acpi_config *config = dev->chip_info;
 	const char *path = acpi_device_path(dev);
 
-	if (!dev->enabled || !path || !config)
+	if (!path || !config)
 		return;
 
 	/* Don't generate output for hubs, only ports */
@@ -49,18 +63,47 @@ static void usb_acpi_fill_ssdt_generator(const struct device *dev)
 	/* Resources */
 	if (usb_acpi_add_gpios_to_crs(config) == true) {
 		struct acpi_dp *dsd;
+		int idx = 0;
+		int reset_gpio_index = -1;
+		int privacy_gpio_index;
 
 		acpigen_write_name("_CRS");
 		acpigen_write_resourcetemplate_header();
-		acpi_device_write_gpio(&config->reset_gpio);
+		if (!config->has_power_resource) {
+			reset_gpio_index = usb_acpi_write_gpio(
+						&config->reset_gpio, &idx);
+		}
+		privacy_gpio_index = usb_acpi_write_gpio(&config->privacy_gpio,
+							 &idx);
 		acpigen_write_resourcetemplate_footer();
 
 		dsd = acpi_dp_new_table("_DSD");
-		acpi_dp_add_gpio(dsd, "reset-gpio", path, 0, 0,
-				config->reset_gpio.active_low);
+		if (reset_gpio_index >= 0)
+			acpi_dp_add_gpio(dsd, "reset-gpio", path,
+					 reset_gpio_index, 0,
+					 config->reset_gpio.active_low);
+		if (privacy_gpio_index >= 0)
+			acpi_dp_add_gpio(dsd, "privacy-gpio", path,
+					 privacy_gpio_index, 0,
+					 config->privacy_gpio.active_low);
 		acpi_dp_write(dsd);
 	}
 
+	if (config->has_power_resource) {
+		const struct acpi_power_res_params power_res_params = {
+			&config->reset_gpio,
+			config->reset_delay_ms,
+			config->reset_off_delay_ms,
+			&config->enable_gpio,
+			config->enable_delay_ms,
+			config->enable_off_delay_ms,
+			NULL,
+			0,
+			0
+		};
+		acpi_device_add_power_res(&power_res_params);
+	}
+
 	acpigen_pop_len();
 
 	printk(BIOS_INFO, "%s: %s at %s\n", path,

src/drivers/wifi/generic/acpi.c

@@ -44,8 +44,11 @@ static void emit_sar_acpi_structures(const struct device *dev)
 	struct wifi_sar_limits sar_limits;
 	struct wifi_sar_delta_table *wgds;
 
-	/* CBFS SAR and SAR ACPI tables are currently used only by Intel WiFi devices. */
-	if (dev->vendor != PCI_VENDOR_ID_INTEL)
+	/*
+	 * If device type is PCI, ensure that the device has Intel vendor ID. CBFS SAR and SAR
+	 * ACPI tables are currently used only by Intel WiFi devices.
+	 */
+	if (dev->path.type == DEVICE_PATH_PCI && dev->vendor != PCI_VENDOR_ID_INTEL)
 		return;
 
 	/* Retrieve the sar limits data */
@@ -222,9 +225,6 @@ void wifi_pcie_fill_ssdt(const struct device *dev)
 {
 	const char *path;
 
-	if (!is_dev_enabled(dev))
-		return;
-
 	path = acpi_device_path(dev);
 	if (!path)
 		return;
@@ -247,9 +247,6 @@ void wifi_cnvi_fill_ssdt(const struct device *dev)
 {
 	const char *path;
 
-	if (!is_dev_enabled(dev))
-		return;
-
 	path = acpi_device_path(dev->bus->dev);
 	if (!path)
 		return;

src/ec/google/chromeec/audio_codec/audio_codec.c

@@ -15,7 +15,7 @@ static void crosec_audio_codec_fill_ssdt(const struct device *dev)
 	const char *scope = acpi_device_scope(dev);
 	struct ec_google_chromeec_audio_codec_config *cfg = dev->chip_info;
 
-	if (!dev->enabled || !scope || !cfg)
+	if (!scope || !cfg)
 		return;
 
 	acpigen_write_scope(scope);

src/ec/google/chromeec/ec_acpi.c

@@ -140,10 +140,6 @@ static void fill_ssdt_typec_device(const struct device *dev)
 		if (rv)
 			continue;
 
-		if (!config->mux_conn[i])
-			printk(BIOS_ERR, "ERROR: Mux connector info missing for Type-C port "
-			       "#%d\n", i);
-
 		usb2_port = NULL;
 		usb3_port = NULL;
 		usb4_port = NULL;
@@ -227,9 +223,6 @@ void google_chromeec_fill_ssdt_generator(const struct device *dev)
 	struct device_path path;
 	struct device *ec;
 
-	if (!dev->enabled)
-		return;
-
 	/* Set up a minimal EC0 device to pass to the DPTF helpers */
 	path.type = DEVICE_PATH_GENERIC;
 	path.generic.id = 0;

src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c

@@ -17,7 +17,7 @@ static void crosec_i2c_tunnel_fill_ssdt(const struct device *dev)
 	struct ec_google_chromeec_i2c_tunnel_config *cfg = dev->chip_info;
 	struct acpi_dp *dsd;
 
-	if (!dev->enabled || !scope || !cfg)
+	if (!scope || !cfg)
 		return;
 
 	acpigen_write_scope(scope);

src/ec/google/wilco/chip.c

@@ -184,9 +184,6 @@ static void wilco_ec_fill_ssdt_generator(const struct device *dev)
 	void *region_ptr;
 	size_t ucsi_alloc_region_len;
 
-	if (!dev->enabled)
-		return;
-
 	ucsi_alloc_region_len = ucsi_region_len < UCSI_MIN_ALLOC_REGION_LEN ?
 		UCSI_MIN_ALLOC_REGION_LEN : ucsi_region_len;
 	region_ptr = cbmem_add(CBMEM_ID_ACPI_UCSI, ucsi_alloc_region_len);

src/ec/purism/librem/acpi/battery.asl

@@ -65,13 +65,13 @@ Device (BAT)
 	/* Method to enable full battery workaround */
 	Method (BFWE)
 	{
-		Store (One, BFWK)
+		BFWK = 1
 	}
 
 	/* Method to disable full battery workaround */
 	Method (BFWD)
 	{
-		Store (Zero, BFWK)
+		BFWK = 0
 	}
 
 	Method (_STA, 0, Serialized)
@@ -86,22 +86,22 @@ Device (BAT)
 	Method (_BIF, 0, Serialized)
 	{
 		/* Last Full Charge Capacity */
-		Store (BTDF, Index (PBIF, 2))
+		PBIF [2] = BTDF
 
 		/* Design Voltage */
-		Store (BTDV, Index (PBIF, 4))
+		PBIF [4] = BTDV
 
 		/* Design Capacity */
-		Store (BTDA, Local0)
-		Store (Local0, Index (PBIF, 1))
+		Local0 = BTDA
+		PBIF [1] = Local0
 
 		/* Design Capacity of Warning */
-		Divide (Multiply (Local0, DWRN), 100, , Local2)
-		Store (Local2, Index (PBIF, 5))
+		Local2 = (Local0 * DWRN) / 100
+		PBIF [5] = Local2
 
 		/* Design Capacity of Low */
-		Divide (Multiply (Local0, DLOW), 100, , Local2)
-		Store (Local2, Index (PBIF, 6))
+		Local2 = (Local0 * DLOW) / 100
+		PBIF [6] = Local2
 
 		Return (PBIF)
 	}
@@ -109,22 +109,22 @@ Device (BAT)
 	Method (_BIX, 0, Serialized)
 	{
 		/* Last Full Charge Capacity */
-		Store (BTDF, Index (PBIX, 3))
+		PBIX [3] = BTDF
 
 		/* Design Voltage */
-		Store (BTDV, Index (PBIX, 5))
+		PBIX [5] = BTDV
 
 		/* Design Capacity */
-		Store (BTDA, Local0)
-		Store (Local0, Index (PBIX, 2))
+		Local0 = BTDA
+		PBIX [2] = Local0
 
 		/* Design Capacity of Warning */
-		Divide (Multiply (Local0, DWRN), 100, , Local2)
-		Store (Local2, Index (PBIX, 6))
+		Local2 = (Local0 * DWRN) / 100
+		PBIX [6] = Local2
 
 		/* Design Capacity of Low */
-		Divide (Multiply (Local0, DLOW), 100, , Local2)
-		Store (Local2, Index (PBIX, 7))
+		Local2 = (Local0 * DLOW) / 100
+		PBIX [7] = Local2
 
 		Return (PBIX)
 	}
@@ -142,61 +142,60 @@ Device (BAT)
 		/* Check if AC is present */
 		If (ACEX) {
 			/* Read battery status from EC */
-			Store (BSTS, Local0)
+			Local0 = BSTS
 		} Else {
 			/* Always discharging when on battery power */
-			Store (0x01, Local0)
+			Local0 = 0x01
 		}
 
 		/* Check for critical battery level */
 		If (BFCR) {
-			Or (Local0, 0x04, Local0)
+			Local0 |= 0x04
 		}
-		Store (Local0, Index (PBST, 0))
+		PBST [0] = Local0
 
 		/* Notify if battery state has changed since last time */
-		If (LNotEqual (Local0, BSTP)) {
-			Store (Local0, BSTP)
+		If (Local0 != BSTP) {
+			BSTP = Local0
 			Notify (BAT, 0x80)
 		}
 
 		/*
 		 * 1: BATTERY PRESENT RATE
 		 */
-		Store (BTPR, Local1)
-		If (And (Local1, 0x8000)) {
-			And (Not (Local1), 0x7FFF, Local0)
-			Increment (Local0)
+		Local1 = BTPR
+		If (Local1 & 0x8000) {
+			Local0 = ~Local1 & 0x7FFF
+			Local0++
 		} Else {
-			And (Local1, 0x7FFF, Local0)
+			Local0 = Local1 & 0x7FFF
 		}
-		If(LLess(Local0, 0x0352))
+		If(Local0 < 0x0352)
 		{
-			Store(0x0352, Local0)
+			Local0 = 0x0352
 		}
-		Store (Local0, Index (PBST, 1))
+		PBST [1] = Local0
 
 		/*
 		 * 2: BATTERY REMAINING CAPACITY
 		 */
-		Store (BTRA, Local0)
-		If (LAnd (BFWK, LAnd (ACEX, LNot (BSTS)))) {
-			Store (BTDF, Local1)
+		Local0 = BTRA
+		If (BFWK && ACEX && !BSTS) {
+			Local1 = BTDF
 
 			/* See if within ~6% of full */
-			ShiftRight (Local1, 4, Local2)
-			If (LAnd (LGreater (Local0, Subtract (Local1, Local2)),
-			          LLess (Local0, Add (Local1, Local2))))
+			Local2 = Local1 >> 4
+			If ((Local0 > (Local1 - Local2)) && (Local0 < (Local1 + Local2)))
 			{
-				Store (Local1, Local0)
+				Local0 = Local1
 			}
 		}
-		Store (Local0, Index (PBST, 2))
+		PBST [2] = Local0
 
 		/*
 		 * 3: BATTERY PRESENT VOLTAGE
 		 */
-		Store (BTVO, Index (PBST, 3))
+		PBST [3] = BTVO
 
 		Return (PBST)
 	}

src/ec/purism/librem/acpi/ec.asl

@@ -15,12 +15,12 @@ Device (TPSD)
 
 	Method (FNCX, 1, NotSerialized)
 	{
-		If (LEqual (Arg0, 0x86)) {
+		If (Arg0 == 0x86) {
 			/* Enable topstar-laptop kernel driver handling */
-			Store (One, ^^EC.TPSE)
-		} ElseIf (LEqual (Arg0, 0x87)) {
+			^^EC.TPSE = 1
+		} ElseIf (Arg0 == 0x87) {
 			/* Disable topstar-laptop kernel driver handling */
-			Store (Zero, ^^EC.TPSE)
+			^^EC.TPSE = 0
 		}
 	}
 }
@@ -80,10 +80,10 @@ Device (EC)
 	Method (_REG, 2, NotSerialized)
 	{
 		/* Initialize AC power state */
-		Store (ACEX, \PWRS)
+		\PWRS = ACEX
 
 		/* Initialize LID switch state */
-		Store (LIDS, \LIDS)
+		\LIDS = LIDS
 	}
 
 	/* Notify topstar-laptop kernel driver */
@@ -115,7 +115,7 @@ Device (EC)
 	/* AC Status Changed */
 	Method (_Q20)
 	{
-		Store (ACEX, \PWRS)
+		\PWRS = ACEX
 		Notify (AC, 0x80)
 		Notify (BAT, 0x80)
 		PNOT ()
@@ -124,7 +124,7 @@ Device (EC)
 	/* Lid Event */
 	Method (_Q21)
 	{
-		Store (LIDS, \LIDS)
+		\LIDS = LIDS
 		Notify (LID0, 0x80)
 	}
 
@@ -176,7 +176,7 @@ Device (EC)
 		Notify (\_SB.SLPB, 0x80)
 	}
 
-	/* KEY_F13 (Touchpad Enable/Disable)
+	/* KEY_F13 (Touchpad Enable/Disable) */
 	Method (_Q34)
 	{
 		TPSN (0x87)
@@ -193,7 +193,7 @@ Device (EC)
 	/* KEY_BLUETOOTH */
 	Method (_Q37)
 	{
-		XOr (^BTLE, One, ^BTLE)
+		^BTLE ^= 1
 	}
 
 	/* Turbo Enable/Disable */
@@ -208,13 +208,13 @@ Device (EC)
 		 * when the system is charging.
 		 */
 		If (TURB) {
-			Store (PPCM_TURBO, PPCM)
+			PPCM = PPCM_TURBO
 			PPCN ()
-			Store (One, EDTB)
+			EDTB = 1
 		} Else {
-			Store (PPCM_NOTURBO, PPCM)
+			PPCM = PPCM_NOTURBO
 			PPCN ()
-			Store (Zero, EDTB)
+			EDTB = 0
 		}
 	}
 

src/include/acpi/acpi.h

@@ -99,19 +99,24 @@ typedef struct acpi_gen_regaddr {
 	u32 addrh;		/* Register address, high 32 bits */
 } __packed acpi_addr_t;
 
-#define ACPI_ADDRESS_SPACE_MEMORY	   0	/* System memory */
-#define ACPI_ADDRESS_SPACE_IO		   1	/* System I/O */
-#define ACPI_ADDRESS_SPACE_PCI		   2	/* PCI config space */
-#define ACPI_ADDRESS_SPACE_EC		   3	/* Embedded controller */
-#define ACPI_ADDRESS_SPACE_SMBUS	   4	/* SMBus */
-#define ACPI_ADDRESS_SPACE_PCC		0x0A	/* Platform Comm. Channel */
-#define ACPI_ADDRESS_SPACE_FIXED	0x7f	/* Functional fixed hardware */
-#define  ACPI_FFIXEDHW_VENDOR_INTEL	   1	/* Intel */
-#define  ACPI_FFIXEDHW_CLASS_HLT	   0	/* C1 Halt */
-#define  ACPI_FFIXEDHW_CLASS_IO_HLT	   1	/* C1 I/O then Halt */
-#define  ACPI_FFIXEDHW_CLASS_MWAIT	   2	/* MWAIT Native C-state */
-#define  ACPI_FFIXEDHW_FLAG_HW_COORD	   1	/* Hardware Coordination bit */
-#define  ACPI_FFIXEDHW_FLAG_BM_STS	   2	/* BM_STS avoidance bit */
+#define ACPI_ADDRESS_SPACE_MEMORY		0	/* System memory */
+#define ACPI_ADDRESS_SPACE_IO			1	/* System I/O */
+#define ACPI_ADDRESS_SPACE_PCI			2	/* PCI config space */
+#define ACPI_ADDRESS_SPACE_EC			3	/* Embedded controller */
+#define ACPI_ADDRESS_SPACE_SMBUS		4	/* SMBus */
+#define ACPI_ADDRESS_SPACE_CMOS			5	/* SystemCMOS */
+#define ACPI_ADDRESS_SPACE_PCI_BAR_TARGET	6	/* PciBarTarget */
+#define ACPI_ADDRESS_SPACE_IPMI			7	/* IPMI */
+#define ACPI_ADDRESS_SPACE_GENERAL_PURPOSE_IO	8	/* GeneralPurposeIO */
+#define ACPI_ADDRESS_SPACE_GENERIC_SERIAL_BUS	9	/* GenericSerialBus  */
+#define ACPI_ADDRESS_SPACE_PCC			0x0A	/* Platform Comm. Channel */
+#define ACPI_ADDRESS_SPACE_FIXED		0x7f	/* Functional fixed hardware */
+#define  ACPI_FFIXEDHW_VENDOR_INTEL		1	/* Intel */
+#define  ACPI_FFIXEDHW_CLASS_HLT		0	/* C1 Halt */
+#define  ACPI_FFIXEDHW_CLASS_IO_HLT		1	/* C1 I/O then Halt */
+#define  ACPI_FFIXEDHW_CLASS_MWAIT		2	/* MWAIT Native C-state */
+#define  ACPI_FFIXEDHW_FLAG_HW_COORD		1	/* Hardware Coordination bit */
+#define  ACPI_FFIXEDHW_FLAG_BM_STS		2	/* BM_STS avoidance bit */
 /* 0x80-0xbf: Reserved */
 /* 0xc0-0xff: OEM defined */
 

src/include/acpi/acpigen.h

@@ -286,6 +286,7 @@ struct cppc_config {
 };
 
 void acpigen_write_return_integer(uint64_t arg);
+void acpigen_write_return_namestr(const char *arg);
 void acpigen_write_return_string(const char *arg);
 void acpigen_write_len_f(void);
 void acpigen_pop_len(void);
@@ -374,6 +375,7 @@ void acpigen_write_xor(uint8_t arg1, uint8_t arg2, uint8_t res);
 void acpigen_write_and(uint8_t arg1, uint8_t arg2, uint8_t res);
 void acpigen_write_not(uint8_t arg, uint8_t res);
 void acpigen_write_debug_string(const char *str);
+void acpigen_write_debug_namestr(const char *str);
 void acpigen_write_debug_integer(uint64_t val);
 void acpigen_write_debug_op(uint8_t op);
 void acpigen_write_if(void);
@@ -466,7 +468,7 @@ int get_cst_entries(acpi_cstate_t **);
 
 /*
  * Get element from package into specified destination op:
- *   <dest_op> = DeRefOf (<package_op>[<element])
+ *   <dest_op> = DeRefOf (<package_op>[<element>])
  *
  * Example:
  *  acpigen_get_package_op_element(ARG0_OP, 0, LOCAL0_OP)
@@ -474,6 +476,25 @@ int get_cst_entries(acpi_cstate_t **);
  */
 void acpigen_get_package_op_element(uint8_t package_op, unsigned int element, uint8_t dest_op);
 
+/* Set element of package op to specified op:  DeRefOf (<package>[<element>]) = <src> */
+void acpigen_set_package_op_element_int(uint8_t package_op, unsigned int element, uint64_t src);
+
+/* Get element from package to specified op:  <dest_op> = <package>[<element>] */
+void acpigen_get_package_element(const char *package, unsigned int element, uint8_t dest_op);
+
+/* Set element of package to specified op:  <package>[<element>] = <src> */
+void acpigen_set_package_element_int(const char *package, unsigned int element, uint64_t src);
+
+/* Set element of package to specified namestr:  <package>[<element>] = <src> */
+void acpigen_set_package_element_namestr(const char *package, unsigned int element,
+					 const char *src);
+
+/*
+ * Delay up to wait_ms milliseconds until the provided name matches the expected value.
+ * If wait_ms is >= 32ms then it will wait in 16ms chunks.  This function uses LOCAL7_OP.
+ */
+void acpigen_write_delay_until_namestr_int(uint32_t wait_ms, const char *name, uint64_t value);
+
 /*
  * Soc-implemented functions for generating ACPI AML code for GPIO handling. All
  * these functions are expected to use only Local5, Local6 and Local7

src/include/console/uart.h

@@ -20,6 +20,18 @@ static inline unsigned int get_uart_baudrate(void)
 }
 #endif
 
+#if CONFIG(OVERRIDE_UART_FOR_CONSOLE)
+/* Return the index of uart port, define this in your platform
+ * when need to use variables to override the index.
+ */
+unsigned int get_uart_for_console(void);
+#else
+static inline unsigned int get_uart_for_console(void)
+{
+	return CONFIG_UART_FOR_CONSOLE;
+}
+#endif
+
 /* Returns the divisor value for a given baudrate.
  * The formula to satisfy is:
  *    refclk / divisor = baudrate * oversample
@@ -56,15 +68,15 @@ void oxford_remap(unsigned int new_base);
 #if __CONSOLE_SERIAL_ENABLE__
 static inline void __uart_init(void)
 {
-	uart_init(CONFIG_UART_FOR_CONSOLE);
+	uart_init(get_uart_for_console());
 }
 static inline void __uart_tx_byte(u8 data)
 {
-	uart_tx_byte(CONFIG_UART_FOR_CONSOLE, data);
+	uart_tx_byte(get_uart_for_console(), data);
 }
 static inline void __uart_tx_flush(void)
 {
-	uart_tx_flush(CONFIG_UART_FOR_CONSOLE);
+	uart_tx_flush(get_uart_for_console());
 }
 #else
 static inline void __uart_init(void)		{}

src/include/cpu/x86/mtrr.h

@@ -31,9 +31,10 @@
 #define IA32_SMRR_PHYS_MASK		0x1f3
 #define SMRR_PHYS_MASK_LOCK		(1 << 10)
 
-/* Specific to model_6fx and model_1067x */
-#define MSR_SMRR_PHYS_BASE		0xa0
-#define MSR_SMRR_PHYS_MASK		0xa1
+/* Specific to model_6fx and model_1067x.
+   These are named MSR_SMRR_PHYSBASE in the SDM. */
+#define CORE2_SMRR_PHYS_BASE		0xa0
+#define CORE2_SMRR_PHYS_MASK		0xa1
 
 #define MTRR_PHYS_BASE(reg)		(0x200 + 2 * (reg))
 #define MTRR_PHYS_MASK(reg)		(MTRR_PHYS_BASE(reg) + 1)

src/include/cpu/x86/save_state.h

@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __CPU_X86_SAVE_STATE_H__
+#define __CPU_X86_SAVE_STATE_H__
+
+#include <stdint.h>
+
+enum cpu_reg {
+	RAX,
+	RBX,
+	RCX,
+	RDX
+};
+
+#define SMM_REV_INVALID 0xffffffff
+
+struct smm_save_state_ops {
+	const uint32_t *revision_table;
+	/* Accessors for CPU registers in the SMM save state
+	   Returns -1 on failure, 0 on success */
+	int (*get_reg)(const enum cpu_reg reg, const int node, void *out, const uint8_t length);
+	int (*set_reg)(const enum cpu_reg reg, const int node, void *in, const uint8_t length);
+	/* Returns -1 on failure, the node on which the 'cmd' was send on success */
+	int (*apmc_node)(u8 cmd);
+};
+
+/* Return -1 on failure, otherwise returns which CPU node issued an APMC IO write */
+int get_apmc_node(u8 cmd);
+/* Return -1 on failure, 0 on succes.
+   Accessors for the SMM save state CPU registers RAX, RBX, RCX and RDX */
+int get_save_state_reg(const enum cpu_reg reg, const int node, void *out, const uint8_t length);
+int set_save_state_reg(const enum cpu_reg reg, const int node, void *in, const uint8_t length);
+
+#endif /* __CPU_X86_SAVE_STATE_H__ */

src/include/cpu/x86/smm.h

@@ -197,5 +197,8 @@ void smm_list_regions(void);
 /* Return the SMM save state revision. The revision can be fetched from the smm savestate
    which is always at the same offset downward from the top of the save state. */
 uint32_t smm_revision(void);
+/* Returns the PM ACPI SMI port. On Intel systems this typically not configurable (APM_CNT, 0xb2).
+   On AMD systems it is sometimes configurable. */
+uint16_t pm_acpi_smi_cmd_port(void);
 
 #endif /* CPU_X86_SMM_H */

src/include/device/pci.h

@@ -79,15 +79,6 @@ void pci_bus_enable_resources(struct device *dev);
 void pci_bus_reset(struct bus *bus);
 struct device *pci_probe_dev(struct device *dev, struct bus *bus,
 				unsigned int devfn);
-
-/*
- * Determine if the given PCI device is the source of wake from sleep by checking PME_STATUS and
- * PME_ENABLE bits in PM control and status register.
- *
- * Returns true if PCI device is wake source, false otherwise.
- */
-bool pci_dev_is_wake_source(const struct device *dev);
-
 void do_pci_scan_bridge(struct device *dev,
 	void (*do_scan_bus)(struct bus *bus,
 		unsigned int min_devfn, unsigned int max_devfn));

src/include/device/pci_ids.h

@@ -2926,6 +2926,7 @@
 #define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_29		0x7a1d
 #define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_30		0x7a1e
 #define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_31		0x7a1f
+#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_32		0x5181
 #define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_0		0x7a80
 #define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_1		0x7a81
 #define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_2		0x7a82

src/include/device/pci_ops.h

@@ -209,4 +209,12 @@ u16 pci_find_capability(const struct device *dev, u16 cap)
 	return pci_s_find_capability(PCI_BDF(dev), cap);
 }
 
+/*
+ * Determine if the given PCI device is the source of wake from sleep by checking PME_STATUS and
+ * PME_ENABLE bits in PM control and status register.
+ *
+ * Returns true if PCI device is wake source, false otherwise.
+ */
+bool pci_dev_is_wake_source(const struct device *dev);
+
 #endif /* PCI_OPS_H */

src/mainboard/51nb/x210/devicetree.cb

@@ -55,7 +55,6 @@ chip soc/intel/skylake
 	register "PmConfigSlpS4MinAssert" = "1"		# 1s
 	register "PmConfigSlpSusMinAssert" = "3"	# 500ms
 	register "PmConfigSlpAMinAssert" = "3"		# 2s
-	register "PmTimerDisabled" = "0"
 
 	register "serirq_mode" = "SERIRQ_CONTINUOUS"
 

src/mainboard/amd/mandolin/Kconfig

@@ -24,10 +24,10 @@ config AMD_LPC_DEBUG_CARD
 	select PICASSO_LPC_IOMUX
 	select SUPERIO_SMSC_SIO1036
 	help
-	  AMD's debug card contains an SMSC SIO1036 device which provides
-	  an I/O-based UART in the system.  This feature is not compatible with
-	  CONFIG_HUDSON_UART enabling the memory-mapped UART in the chipset.
-	  Note that Kconfig does not currently enforce this restriction.
+	  AMD's debug card contains an SMSC SIO1036 device which provides an
+	  I/O-mapped UART in the system. This is mutually exclusive with
+	  PICASSO_CONSOLE_UART which selects the SoC's integrated memory-mapped
+	  UART for coreboot console output.
 
 config CBFS_SIZE
 	hex
@@ -52,10 +52,6 @@ config DEVICETREE
 	string
 	default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"
 
-config MAX_CPUS
-	int
-	default 8
-
 config ONBOARD_VGA_IS_PRIMARY
 	bool
 	default y
@@ -76,6 +72,9 @@ config MANDOLIN_MCHP_FW_FILE
 	depends on MANDOLIN_HAVE_MCHP_FW
 	default "3rdparty/blobs/mainboard/amd/mandolin/EC_mandolin.bin" if BOARD_AMD_MANDOLIN
 	default "3rdparty/blobs/mainboard/amd/mandolin/EC_cereme.bin" if BOARD_AMD_CEREME
+	help
+	  The EC firmware blob is usually the first 128kByte of the stock
+	  firmware image.
 
 if !AMD_LPC_DEBUG_CARD
 choice

src/mainboard/asrock/b85m_pro4/devicetree.cb

@@ -27,7 +27,6 @@ chip northbridge/intel/haswell
 
 		chip southbridge/intel/lynxpoint
 			register "gen1_dec"      = "0x000c0291"	# Super I/O HWM
-			register "sata_ahci"     = "1"
 			register "sata_port_map" = "0x3f"
 
 			device pci 14.0 on  end		# xHCI controller

src/mainboard/asrock/b85m_pro4/dsdt.asl

@@ -20,7 +20,7 @@ DefinitionBlock(
 
 	Device (\_SB.PCI0)
 	{
-		#include <northbridge/intel/haswell/acpi/haswell.asl>
+		#include <northbridge/intel/haswell/acpi/hostbridge.asl>
 		#include <southbridge/intel/lynxpoint/acpi/pch.asl>
 		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 	}

src/mainboard/asrock/h110m/devicetree.cb

@@ -24,7 +24,6 @@ chip soc/intel/skylake
 	# FSP Configuration
 	register "PrimaryDisplay" = "Display_PEG"
 	register "SaGv" = "SaGv_Enabled"
-	register "PmTimerDisabled" = "0"
 
 	# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
 	# SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s

src/mainboard/asrock/h81m-hds/devicetree.cb

@@ -35,7 +35,6 @@ chip northbridge/intel/haswell
 		end
 
 		chip southbridge/intel/lynxpoint
-			register "sata_ahci" = "1"
 			register "sata_port_map" = "0x33"
 
 			register "gen1_dec" = "0x00000295" # Super I/O HWM

src/mainboard/asrock/h81m-hds/dsdt.asl

@@ -20,7 +20,7 @@ DefinitionBlock(
 	{
 		Device (PCI0)
 		{
-		#include <northbridge/intel/haswell/acpi/haswell.asl>
+		#include <northbridge/intel/haswell/acpi/hostbridge.asl>
 		#include <southbridge/intel/lynxpoint/acpi/pch.asl>
 		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}

src/mainboard/asus/f2a85-m/Kconfig

@@ -84,7 +84,7 @@ config VGA_BIOS_ID
 
 config HUDSON_LEGACY_FREE
 	bool
-	default y
+	default n
 
 config POST_IO
 	bool

src/mainboard/clevo/Kconfig

@@ -12,4 +12,4 @@ source "src/mainboard/clevo/*/Kconfig"
 config MAINBOARD_VENDOR
 	default "Clevo"
 
-endif
+endif # VENDOR_CLEVO

src/mainboard/clevo/cml-u/Kconfig

@@ -9,6 +9,8 @@ config BOARD_SPECIFIC_OPTIONS
 	select HAVE_ACPI_TABLES
 	select HAVE_SMI_HANDLER
 	select HAVE_SPD_IN_CBFS
+	select HAVE_OPTION_TABLE
+	select HAVE_CMOS_DEFAULT
 	select INTEL_GMA_HAVE_VBT
 	select INTEL_LPSS_UART_FOR_CONSOLE
 	select MAINBOARD_HAS_LPC_TPM

src/mainboard/clevo/cml-u/cmos.default

@@ -0,0 +1,3 @@
+boot_option=Fallback
+debug_level=Debug
+power_on_after_fail=Disable

src/mainboard/clevo/cml-u/cmos.layout

@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# start-bit	length	config	config-ID	name
+0		120	r	0		reserved_memory
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384		  1	e	4		boot_option
+388		  4	h	0		reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395		  4    e	6		debug_level
+
+# -----------------------------------------------------------------
+# coreboot config options: cpu
+400		  1    e	2		hyper_threading
+
+# -----------------------------------------------------------------
+# coreboot config options: southbridge
+410		  2	e	7		power_on_after_fail
+
+# -----------------------------------------------------------------
+# vboot nv area
+800		128	r	0		vbnv
+
+# -----------------------------------------------------------------
+# coreboot config options: check sums
+984		 16	h	0		check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+6     0     Emergency
+6     1     Alert
+6     2     Critical
+6     3     Error
+6     4     Warning
+6     5     Notice
+6     6     Info
+6     7     Debug
+6     8     Spew
+7     0     Disable
+7     1     Enable
+7     2     Keep
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 799 984

src/mainboard/clevo/cml-u/variants/l140cu/ramstage.c

@@ -6,6 +6,6 @@
 void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 {
 	/* Configure pads prior to SiliconInit() in case there's any
-	 * dependencies during hardware initialization. */
+	   dependencies during hardware initialization. */
 	cnl_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
 }

src/mainboard/emulation/qemu-aarch64/memlayout.ld

@@ -21,7 +21,8 @@ SECTIONS
 	BOOTBLOCK(0x60010000, 64K)
 	STACK(0x60020000, 62K)
 	FMAP_CACHE(0x6002F800, 2K)
-	ROMSTAGE(0x60030000, 128K)
+        TIMESTAMP(0x60030000, 1K)
+	ROMSTAGE(0x60031000, 128K)
 	TTB(0x60070000, 128K)
 	RAMSTAGE(0x600b0000, 16M)
 

src/mainboard/emulation/qemu-q35/Makefile.inc

@@ -14,3 +14,5 @@ ramstage-y += ../qemu-i440fx/northbridge.c
 verstage-$(CONFIG_CHROMEOS) += chromeos.c
 verstage-$(CONFIG_CHROMEOS) += ../qemu-i440fx/fw_cfg.c
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += smi.c

src/mainboard/emulation/qemu-q35/smi.c

@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cpu/x86/smm.h>
+
+/* The X86 qemu target uses AMD64 save states but the APM port is not configurable. */
+uint16_t pm_acpi_smi_cmd_port(void)
+{
+	return APM_CNT;
+}

src/mainboard/facebook/monolith/Kconfig

@@ -92,4 +92,7 @@ config VBOOT_ALWAYS_ALLOW_UDC
 	def_bool y
 	depends on VBOOT && !CHROMEOS
 
+config USE_PM_ACPI_TIMER
+	default n
+
 endif

src/mainboard/facebook/monolith/devicetree.cb

@@ -36,7 +36,6 @@ chip soc/intel/skylake
 	register "ScsEmmcHs400Enabled" = "1"
 	register "SkipExtGfxScan" = "1"
 	register "SaGv" = "SaGv_Enabled"
-	register "PmTimerDisabled" = "1"
 	register "HeciEnabled" = "0"
 
 	register "SataSalpSupport" = "1"

src/mainboard/getac/p470/acpi/ec.asl

@@ -87,16 +87,16 @@ Device(EC0)
 	Method (_Q01, 0)
 	{
 		Notify (\_SB.CP00, 0x80)
-		If(ADP) {
-			Store(1, \_SB.AC.ACST)
-			TRAP(0xe3)
-			Store(1, PWRS)
-			TRAP(0x2b)
+		If (ADP) {
+			\_SB.AC.ACST = 1
+			TRAP (0xe3)
+			PWRS = 1
+			TRAP (0x2b)
 		} Else {
-			Store(0, \_SB.AC.ACST)
-			Notify(\_SB.AC, 0x80)
-			Notify(\_SB.BAT0, 0x80)
-			Store(0, PWRS)
+			\_SB.AC.ACST = 0
+			Notify (\_SB.AC, 0x80)
+			Notify (\_SB.BAT0, 0x80)
+			PWRS = 0
 			TRAP(0x2b)
 		}
 
@@ -107,7 +107,7 @@ Device(EC0)
 
 	Method (_Q02, 0)
 	{
-		If(BAT) {
+		If (BAT) {
 			Notify(\_SB.BAT0, 0x00)
 			Notify(\_SB.AC, 0x80)
 		} Else {
@@ -132,7 +132,7 @@ Device(EC0)
 	{
 		TRAP(0xe0)
 
-		If (LEqual(RTCF, 0x00)) {
+		If (RTCF == 0x00) {
 			Notify(LID0, 0x80)
 		} else {
 			TRAP(0xc1)
@@ -172,25 +172,25 @@ Device(EC0)
 
 	Method (_Q24, 0)
 	{
-		Store(0x3f, HOTK)
-		If(IGDS) {
+		HOTK = 0x3f
+		If (IGDS) {
 			Notify (\_SB.PCI0.GFX0, 0x82)
 		} Else {
-			TRAP(0xE1)
+			TRAP (0xE1)
 		}
 		Notify (\_SB.ECO, 0x85)
 	}
 
 	Method (_Q25, 0)
 	{
-		Store(0x40, HOTK)
+		HOTK = 0x40
 		TRAP(0xe1)
 		Notify(\_SB.ECO, 0x86)
 	}
 
 	Method (_Q26, 0)
 	{
-		Store(0x41, HOTK)
+		HOTK = 0x41
 		TRAP(0xe1)
 		Notify(\_SB.ECO, 0x87)
 	}
@@ -212,7 +212,7 @@ Device(EC0)
 
 	Method (_Q2A, 0)
 	{
-		Store(0x57, HOTK)
+		HOTK = 0x57
 		TRAP(0xe1)
 		Notify(\_SB.ECO, 0x8b)
 	}
@@ -225,7 +225,7 @@ Device(EC0)
 
 	Method (_Q2C, 0)
 	{
-		Store(0x59, HOTK)
+		HOTK = 0x59
 		TRAP(0xe1)
 	}
 
@@ -241,25 +241,25 @@ Device(EC0)
 
 	Method (_Q3A, 0)
 	{
-		Store(1, BRTL)
+		BRTL = 1
 		Notify(\_SB.ECO, 0x93)
 	}
 
 	Method (_Q3B, 0)
 	{
-		Store(0, BRTL)
+		BRTL = 0
 		Notify(\_SB.ECO, 0x93)
 	}
 
 	Method (_Q3C, 0)
 	{
-		Store(1, SUN)
+		SUN = 1
 		Notify(\_SB.ECO, 0x92)
 	}
 
 	Method (_Q3D, 0)
 	{
-		Store(0, SUN)
+		SUN = 0
 		Notify(\_SB.ECO, 0x92)
 	}
 
@@ -302,14 +302,14 @@ Device(EC0)
 	Method (_Q48, 0)
 	{
 		TRAP(0xd2) // Check AC Status
-		Store (1, ODDS)
+		ODDS = 1
 		Notify(\_SB.ECO, 0x90)
 	}
 
 	Method (_Q49, 0)
 	{
 		TRAP(0xd2) // Check AC Status
-		Store (0, ODDS)
+		ODDS = 0
 		Notify(\_SB.ECO, 0x90)
 	}
 
@@ -337,7 +337,7 @@ Device(EC0)
 
 	Method (_Q5C, 0)
 	{
-		// Store(2, IGPS)
+		// IGPS = 2
 		Notify(\_SB.ECO, 0x94)
 	}
 
@@ -364,26 +364,26 @@ Scope(\_SB)
 		Method (GDPD, 0, Serialized)
 		{
 			// Set flag byte to zero
-			Store (0, Local0)
+			Local0 = 0
 
-			If (And(BRTL, 0x01)) {
-				Or(Local0, 0x01, Local0)
+			If (BRTL & 0x01) {
+				Local0 |= 0x01
 			}
 
-			If (And(BRTL, 0x02)) {
-				Or(Local0, 0x04, Local0)
+			If (BRTL & 0x02) {
+				Local0 |= 0x04
 			}
 
-			If (And(BRTL, 0x04)) {
-				Or(Local0, 0x02, Local0)
+			If (BRTL & 0x04) {
+				Local0 |= 0x02
 			}
 
-			If (And(BRTL, 0x30)) {
-				Or(Local0, 0x10, Local0)
+			If (BRTL & 0x30) {
+				Local0 |= 0x10
 			}
 
-			If (And(BRTL, 0x40)) {
-				Or(Local0, 0x40, Local0)
+			If (BRTL & 0x40) {
+				Local0 |= 0x40
 			}
 
 			Return (Local0)
@@ -391,18 +391,18 @@ Scope(\_SB)
 
 		Method (GDPC, 0, Serialized)
 		{
-			Store (0, Local0)
+			Local0 = 0
 
-			If (And(BRTL, 0x10)) {
-				Or(Local0, 0x04, Local0)
+			If (BRTL & 0x10) {
+				Local0 |= 0x04
 			}
 
-			If (And( BRTL, 0x20)) {
-				Or(Local0, 0x01, Local0)
+			If (BRTL & 0x20) {
+				Local0 |= 0x01
 			}
 
-			If (And(BRTL, 0x40)) {
-				Or(Local0, 0x02, Local0)
+			If (BRTL & 0x40) {
+				Local0 |= 0x02
 			}
 
 			Return (Local0)
@@ -411,7 +411,7 @@ Scope(\_SB)
 		/* Set Brightness Level */
 		Method(SBLL, 1, Serialized)
 		{
-			Store (Arg0, BRTL)
+			BRTL = Arg0
 			TRAP(0xd5)	// See mainboard's smihandler.c
 			Return (0)
 		}
@@ -426,7 +426,7 @@ Scope(\_SB)
 		/* Get Brightness Level Medium? */
 		Method(GBLM, 0, Serialized)
 		{
-			Store(0x3f, BRTL)
+			BRTL = 0x3f
 			// XXX don't we have to set the brightness?
 			Return(BRTL)
 		}
@@ -434,7 +434,7 @@ Scope(\_SB)
 		/* ??? */
 		Method(SUTE, 1, Serialized)
 		{
-			If (And(Arg0, 0x01)) {
+			If (Arg0 & 0x01) {
 				TRAP(0xf5)
 			} Else {
 				TRAP(0xf6)
@@ -462,33 +462,30 @@ Scope(\_SB)
 			/* Let coreboot update the flags */
 			TRAP(0xe5)
 
-			Store (0, Local0)
-			If(And(RFDV, 0x01)) {
-				Or(Local0, 0x01, Local0)
+			Local0 = 0
+			If (RFDV & 0x01) {
+				Local0 |= 0x01
 			}
-			If(And(RFDV, 0x02)) {
-				Or(Local0, 0x02, Local0)
+			If (RFDV & 0x02) {
+				Local0 |= 0x02
 			}
-			If(And(RFDV, 0x02)) {
-				Or(Local0, 0x02, Local0)
+			If (RFDV & 0x04) {
+				Local0 |= 0x04
 			}
-			If(And(RFDV, 0x04)) {
-				Or(Local0, 0x04, Local0)
+			If (RFDV & 0x08) {
+				Local0 |= 0x08
 			}
-			If(And(RFDV, 0x08)) {
-				Or(Local0, 0x08, Local0)
+			If (GP15 & 0x01) {		// GDIS
+				Local0 |= 0x10
 			}
-			If(And(GP15, 0x01)) {		// GDIS
-				Or(Local0, 0x10, Local0)
+			If (GP12 & 0x01) {		// WIFI Led (WLED)
+				Local0 |= 0x20
 			}
-			If(And(GP12, 0x01)) {		// WIFI Led (WLED)
-				Or(Local0, 0x20, Local0)
+			If (BTEN & 0x01) {		// BlueTooth Enable
+				Local0 |= 0x40
 			}
-			If(And(BTEN, 0x01)) {		// BlueTooth Enable
-				Or(Local0, 0x40, Local0)
-			}
-			If(And(GP10, 0x01)) {		// GPS Enable
-				Or(Local0, 0x80, Local0)
+			If (GP10 & 0x01) {		// GPS Enable
+				Local0 |= 0x80
 			}
 
 			Return (Local0)
@@ -497,30 +494,30 @@ Scope(\_SB)
 		/* Set RFD */
 		Method(SRFD, 1, Serialized)
 		{
-			If (And(Arg0, 0x01)) {
-				Store (1, GP14)		// GLED
-				Store (1, GP15)		// GDIS
+			If (Arg0 & 0x01) {
+				GP14 = 1		// GLED
+				GP15 = 1		// GDIS
 			} Else {
-				Store (0, GP14)
-				Store (0, GP15)
+				GP14 = 0
+				GP15 = 0
 			}
 
 			/* WIFI */
-			If (And(Arg0, 0x02)) {
-				Store (1, GP12)		// WLED
-				Store (1, GP25)		// WLAN
+			If (Arg0 & 0x02) {
+				GP12 = 1		// WLED
+				GP25 = 1		// WLAN
 			} Else {
-				Store (0, GP12)
-				Store (0, GP25)
+				GP12 = 0
+				GP25 = 0
 			}
 
 			/* Bluetooth */
-			If (And(Arg0, 0x04)) {
-				Store (1, GP13)		// BLED
-				Store (1, BTEN)
+			If (Arg0 & 0x04) {
+				GP13 = 1		// BLED
+				BTEN = 1
 			} Else {
-				Store (0, GP13)		// BLED
-				Store (0, BTEN)
+				GP13 = 0		// BLED
+				BTEN = 0
 			}
 			Return (0)
 		}
@@ -542,7 +539,7 @@ Scope(\_SB)
 		/* Set IGD (Graphics) */
 		Method(SIGD, 1, Serialized)
 		{
-			If (And(Arg0, 0x01)) {
+			If (Arg0 & 0x01) {
 				TRAP(0xf7)
 			} Else {
 				TRAP(0xf8)
@@ -553,7 +550,7 @@ Scope(\_SB)
 		/* SMI-C? Set Mic? */
 		Method (SMIC, 1, Serialized)
 		{
-			If (And(Arg0, 0x01)) {
+			If (Arg0 & 0x01) {
 				TRAP(0xeb)
 			} Else {
 				TRAP(0xec)
@@ -570,7 +567,7 @@ Scope(\_SB)
 		/* Not even decent function names anymore? */
 		Method(S024, 1, Serialized)
 		{
-			If (And(Arg0, 0x01)) {
+			If (Arg0 & 0x01) {
 				TRAP(0xf1)
 			} Else {
 				TRAP(0xf2)
@@ -588,13 +585,13 @@ Scope(\_SB)
 		/* ??? Something with PATA */
 		Method(S025, 1, Serialized)
 		{
-			If(And(Arg0, 0x01)) {
+			If (Arg0 & 0x01) {
 				TRAP(0xfc)
 
-				Store (1, GP33)		// CREN
+				GP33 = 1		// CREN
 				Sleep(1500)
 
-				Store (1, GP34)		// CRRS
+				GP34 = 1		// CRRS
 				Sleep(500)
 
 				Notify(^^PCI0.PATA, 0)
@@ -602,7 +599,7 @@ Scope(\_SB)
 			} Else {
 				TRAP(0xfb)
 				Sleep(1500)
-				Store(0, GP33)		// CREN
+				GP33 = 0		// CREN
 				Sleep(1500)
 				Notify(^^PCI0.PATA, 0)
 				Notify(^^PCI0.PATA.PRID, 0)
@@ -616,16 +613,16 @@ Scope(\_SB)
 		Method(G021, 0, Serialized)
 		{
 			TRAP(0xfe)
-			If (LEqual(ACIN, 0)) {
+			If (ACIN == 0) {
 				TRAP(0xfa)
 				TRAP(0xfd)
-				If (LEqual(ODDS, 1)) {
+				If (ODDS == 1) {
 					TRAP(0xfb)
 					Notify(^^PCI0.PATA, 0)
 					Notify(^^PCI0.PATA.PRID.DSK1, 1)
 					Notify(^^PCI0.PATA.PRID.DSK0, 1)
 					Sleep (1500)
-					Store (0, GP33)		// CREN
+					GP33 = 0		// CREN
 					Sleep (1500)
 					Notify(^^PCI0.PATA, 0)
 					Notify(^^PCI0.PATA.PRID.DSK1, 1)
@@ -648,7 +645,7 @@ Scope(\_SB)
 		/* ??? */
 		Method(S00B, 1, Serialized)
 		{
-			If (And(Arg0, 1)) {
+			If (Arg0 & 1) {
 				TRAP(0xdc)
 			} Else {
 				TRAP(0xdd)

src/mainboard/getac/p470/acpi/platform.asl

@@ -9,23 +9,23 @@ Method(_PTS,1)
 	TRAP(0xed)
 	Sleep(1000)
 
-	Store(0, \_SB.ACFG)
+	\_SB.ACFG = 0
 
 	// Are we going to S4?
-	If (Lequal(Arg0, 4)) {
+	If (Arg0 == 4) {
 		TRAP(0xe7)
 		TRAP(0xea)
 	}
 
 	// Are we going to S5?
-	If (Lequal(Arg0, 5)) {
+	If (Arg0 == 5) {
 		TRAP(0xde)
 	}
 
 	// The 2.6.12.5 ACPI engine seems to optimize the
-	// If(LEqual(Arg0, 5)) path away. This keeps it from doing so:
+	// If(Arg0 == 5) path away. This keeps it from doing so:
 	TRAP(Arg0)
-	Store(Arg0, DBG0)
+	DBG0 = Arg0
 	// End of ugly OS bug workaround
 }
 
@@ -34,12 +34,12 @@ Method(_PTS,1)
 Method(_WAK,1)
 {
 	// Enable GPS
-	Store (1, GP11) // GPSE
+	GP11 = 1 // GPSE
 
 	// Wake from S3 or S4?
-	If (LOr(LEqual(Arg0, 3), LEqual(Arg0, 4))) {
-		If (And(CFGD, 0x01000000)) {
-			If (LAnd(And(CFGD, 0xf0), LEqual(OSYS, 2001))) {
+	If ((Arg0 == 0x03) || (Arg0 == 0x04)) {
+		If (CFGD & 0x01000000) {
+			If ((CFGD & 0xF0) && (OSYS == 2001)) {
 				TRAP(0x3d)
 			}
 		}
@@ -48,26 +48,26 @@ Method(_WAK,1)
 	// Notify PCI Express slots in case a card
 	// was inserted while a sleep state was active.
 
-	If (LEqual(RP1D, 0)) {
+	If (RP1D == 0) {
 		Notify(\_SB.PCI0.RP01, 0)
 	}
 
-	If (LEqual(RP3D, 0)) {
+	If (RP3D == 0) {
 		Notify(\_SB.PCI0.RP03, 0)
 	}
 
-	If (LEqual(RP4D, 0)) {
+	If (RP4D == 0) {
 		Notify(\_SB.PCI0.RP04, 0)
 	}
 
 	// Are we coming from S3?
-	If (LEqual(Arg0, 3)) {
+	If (Arg0 == 3) {
 		TRAP(0xeb)
 		TRAP(0x46)
 	}
 
 	// Are we coming from S4?
-	If (LEqual(Arg0, 4)) {
+	If (Arg0 == 4) {
 		Notify(SLPB, 0x02)
 		If (DTSE) {
 			TRAP(0x47)
@@ -75,16 +75,16 @@ Method(_WAK,1)
 	}
 
 	// Windows XP SP2 P-State restore
-	If (LAnd(LEqual(OSYS, 2002), And(CFGD, 1))) {
-		If (LGreater(\_SB.CP00._PPC, 0)) {
-			Subtract(\_SB.CP00._PPC, 1, \_SB.CP00._PPC)
+	If ((OSYS == 2002) && (CFGD & 0x01)) {
+		If (\_SB.CP00._PPC > 0) {
+			\_SB.CP00._PPC -= 1
 			PNOT()
-			Add(\_SB.CP00._PPC, 1, \_SB.CP00._PPC)
+			\_SB.CP00._PPC += 1
 			PNOT()
 		} Else {
-			Add(\_SB.CP00._PPC, 1, \_SB.CP00._PPC)
+			\_SB.CP00._PPC += 1
 			PNOT()
-			Subtract(\_SB.CP00._PPC, 1, \_SB.CP00._PPC)
+			\_SB.CP00._PPC -= 1
 			PNOT()
 		}
 	}
@@ -118,7 +118,7 @@ Scope(\_SB)
 		 * running: Windows XP SP1 needs to have C-State coordination
 		 * enabled in SMM.
 		 */
-		If (LAnd(LEqual(OSYS, 2001), MPEN)) {
+		If ((OSYS == 2001) && MPEN) {
 			TRAP(0x3d)
 		}
 

src/mainboard/getac/p470/acpi/superio.asl

@@ -19,13 +19,13 @@ Device (SIO1)
 	Method (READ, 3)
 	{
 		Acquire (SIOM, 0xffff)
-		If (LEqual(Arg0, 0)) {
-			Store (0x55, INDX)
-			Store (Arg1, INDX)
-			Store (DATA, Local1)
-			Store (0xaa, INDX)
+		If (Arg0 == 0) {
+			INDX = 0x55
+			INDX = Arg1
+			Local1 = DATA
+			INDX = 0xaa
 		}
-		And (Local1, Arg2, Local1)
+		Local1 &= Arg2
 		Release(SIOM)
 		Return(Local1)
 	}
@@ -33,11 +33,11 @@ Device (SIO1)
 	Method (WRIT, 3)
 	{
 		Acquire (SIOM, 0xffff)
-		If (LEqual(Arg0, 0)) {
-			Store (0x55, INDX)
-			Store (Arg1, INDX)
-			Store (Arg2, DATA)
-			Store (0xaa, INDX)
+		If (Arg0 == 0) {
+			INDX = 0x55
+			INDX = Arg1
+			DATA = Arg2
+			INDX = 0xaa
 		}
 		Release(SIOM)
 	}
@@ -55,13 +55,13 @@ Device (SIO1)
 			Acquire (SIOM, 0xffff)
 
 			// Is the hardware enabled?
-			Store (READ(0, 0x24, 0xff), Local0)
-			If (LEqual(Local0, 0)) {
+			Local0 = READ (0, 0x24, 0xff)
+			If (Local0 == 0) {
 				Return (0xd)
 			} Else {
 				// Power Enabled?
-				Store (READ(0, 0x02, 0x08), Local0)
-				If (LEqual(Local0, 0)) {
+				Local0 = READ (0, 0x02, 0x08)
+				If (Local0 == 0) {
 					Return (0x0d)
 				} Else {
 					Return (0x0f)
@@ -74,12 +74,12 @@ Device (SIO1)
 		{
 			WRIT(0, 0x24, 0x00)
 
-			Store(READ(0, 0x28, 0x0f), Local0)
+			Local0 = READ (0, 0x28, 0x0f)
 			WRIT(0, 0x28, Local0)
 
-			Store(READ(0, 0x02, 0xff), Local0)
-			Not(0x08, Local1)
-			And(Local0, Local1, Local0)
+			Local0 = READ (0, 0x02, 0xff)
+			Local1 = ~0x08
+			Local0 &= Local1
 			WRIT(0, 0x02, Local0)
 		}
 
@@ -104,8 +104,8 @@ Device (SIO1)
 				IRQNoFlags(_IRA) { 4 }
 			})
 
-			And (_STA(), 0x02, Local0)
-			If (LEqual(Local0, 0)) {
+			Local0 = (_STA () & 0x02)
+			If (Local0 == 0) {
 				Return(NONE)
 			}
 
@@ -117,15 +117,15 @@ Device (SIO1)
 				\_SB.PCI0.LPCB.SIO1.UAR1._CRS._IRA._INT, IRQ)
 
 			/* I/O Base */
-			Store (READ(0, 0x24, 0xfe), Local0)
-			ShiftLeft(Local0, 0x02, Local0)
-			Store(Local0, IOMN)
-			Store(Local0, IOMX)
+			Local0 = READ (0, 0x24, 0xfe)
+			Local0 <<= 2
+			IOMN = Local0
+			IOMX = Local0
 
 			/* Interrupt */
-			Store(READ(0, 0x28, 0xf0), Local0)
-			ShiftRight(Local0, 4, Local0)
-			ShiftLeft(1, Local0, IRQ)
+			Local0 = READ (0, 0x28, 0xf0)
+			Local0 >>= 4
+			IRQ = 1 << Local0
 			Return(RSRC)
 		}
 
@@ -138,29 +138,29 @@ Device (SIO1)
 
 			WRIT(0, 0x24, 0)
 			FindSetRightBit(IRQL, Local0)
-			Decrement(Local0)
-			ShiftLeft(Local0, 4, Local0)
+			Local0--
+			Local0 <<= 4
 
-			Store(READ(0, 0x28, 0x0f), Local1)
-			Or(Local0, Local1, Local0)
+			Local1 = READ (0, 0x28, 0x0f)
+			Local0 |= Local1
 			WRIT(0, 0x28, Local0)
 
-			Store(IOLO, Local0)
-			ShiftRight(Local0, 2, Local0)
-			And(Local0, 0xfe, Local0)
+			Local0 = IOLO
+			Local0 >>= 2
+			Local0 &= 0xfe
 
-			Store(IOHI, Local1)
-			ShiftLeft(Local1, 6, Local1)
-			Or (Local0, Local1, Local0)
+			Local1 = IOHI
+			Local1 <<= 6
+			Local0 |= Local1
 			WRIT(0, 0x24, Local0)
 
-			Store(READ(0, 0x02, 0xff), Local0)
-			Or(Local0, 0x08, Local0)
+			Local0 = READ (0, 0x02, 0xff)
+			Local0 |= 0x08
 			WRIT(0, 0x02, Local0)
 
-			Store(READ(0, 0x07, 0xff), Local0)
-			Not(0x40, Local1)
-			And (Local0, Local1, Local0)
+			Local0 = READ (0, 0x07, 0xff)
+			Local1 = ~0x40
+			Local0 &= Local1
 			WRIT(0, 0x07, Local0)
 		}
 
@@ -168,22 +168,22 @@ Device (SIO1)
 		/* D0 state - Line drivers are on */
 		Method (_PS0, 0)
 		{
-			Store(READ(0, 0x02, 0xff), Local0)
-			Or(Local0, 0x08, Local0)
+			Local0 = READ (0, 0x02, 0xff)
+			Local0 |= 0x08
 			WRIT(0, 0x02, Local0)
 
-			Store (READ(0, 0x07, 0xff), Local0)
-			Not(0x40, Local1)
-			And(Local0, Local1, Local0)
+			Local0 = READ (0, 0x07, 0xff)
+			Local1 = ~0x40
+			Local0 &= Local1
 			WRIT(0, 0x07, Local0)
 		}
 
 		/* D3 State - Line drivers are off */
 		Method(_PS3, 0)
 		{
-			Store(READ(0, 0x02, 0xff), Local0)
-			Not(0x08, Local1)
-			And(Local0, Local1, Local0)
+			Local0 = READ (0, 0x02, 0xff)
+			Local1 = ~0x08
+			Local0 &= Local1
 			WRIT(0, 0x02, Local0)
 		}
 	}
@@ -199,19 +199,19 @@ Device (SIO1)
 		Method (_STA, 0)
 		{
 			/* IRDA? */
-			Store(READ(0, 0x0c, 0x38), Local0)
-			If (LNotEqual(Local0, Zero)) {
+			Local0 = READ(0, 0x0c, 0x38)
+			If (Local0 != 0) {
 				Return (0)
 			}
 
 			// Is the hardware enabled?
-			Store (READ(0, 0x25, 0xff), Local0)
-			If (LEqual(Local0, 0)) {
+			Local0 = READ (0, 0x25, 0xff)
+			If (Local0 == 0) {
 				Return (0xd)
 			} Else {
 				// Power Enabled?
-				Store (READ(0, 0x02, 0x80), Local0)
-				If (LEqual(Local0, 0)) {
+				Local0 = READ (0, 0x02, 0x80)
+				If (Local0 == 0) {
 					Return (0x0d)
 				} Else {
 					Return (0x0f)
@@ -224,12 +224,12 @@ Device (SIO1)
 		{
 			WRIT(0, 0x25, 0x00)
 
-			Store(READ(0, 0x28, 0xf0), Local0)
+			Local0 = READ (0, 0x28, 0xf0)
 			WRIT(0, 0x28, Local0)
 
-			Store(READ(0, 0x02, 0xff), Local0)
-			Not(0x80, Local1)
-			And(Local0, Local1, Local0)
+			Local0 = READ (0, 0x02, 0xff)
+			Local1 = ~0x80
+			Local0 &= Local1
 			WRIT(0, 0x02, Local0)
 		}
 
@@ -254,8 +254,8 @@ Device (SIO1)
 				IRQNoFlags(_IRB) { 3 }
 			})
 
-			And (_STA(), 0x02, Local0)
-			If (LEqual(Local0, 0)) {
+			Local0 = _STA () & 0x02
+			If (Local0 == 0) {
 				Return(NONE)
 			}
 
@@ -267,15 +267,15 @@ Device (SIO1)
 				\_SB.PCI0.LPCB.SIO1.UAR2._CRS._IRB._INT, IRQ)
 
 			/* I/O Base */
-			Store (READ(0, 0x25, 0xfe), Local0)
-			ShiftLeft(Local0, 0x02, Local0)
-			Store(Local0, IOMN)
-			Store(Local0, IOMX)
+			Local0 = READ (0, 0x25, 0xfe)
+			Local0 <<= 2
+			IOMN = Local0
+			IOMX = Local0
 
 			/* Interrupt */
-			Store(READ(0, 0x28, 0x0f), Local0)
-			ShiftRight(Local0, 4, Local0)
-			ShiftLeft(1, Local0, IRQ)
+			Local0 = READ (0, 0x28, 0x0f)
+			Local0 >>= 4
+			IRQ = 1 << Local0
 			Return(RSRC)
 		}
 
@@ -288,55 +288,55 @@ Device (SIO1)
 
 			WRIT(0, 0x25, 0)
 			FindSetRightBit(IRQL, Local0)
-			Decrement(Local0)
+			Local0--
 
-			Store(READ(0, 0x28, 0xf0), Local1)
-			Or(Local0, Local1, Local0)
+			Local1 = READ (0x00, 0x28, 0xf0)
+			Local0 |= Local1
 			WRIT(0, 0x28, Local0)
 
-			Store(IOLO, Local0)
-			ShiftRight(Local0, 2, Local0)
-			And(Local0, 0xfe, Local0)
+			Local0 = IOLO
+			Local0 >>= 2
+			Local0 &= 0xfe
 
-			Store(IOHI, Local1)
-			ShiftLeft(Local1, 6, Local1)
-			Or (Local0, Local1, Local0)
+			Local1 = IOHI
+			Local1 <<= 6
+			Local0 |= Local1
 			WRIT(0, 0x25, Local0)
 
-			Store(READ(0, 0x0c, 0xff), Local0)
-			Not(0x38, Local1)
-			And(Local0, Local1, Local0)
+			Local0 = READ (0, 0x0c, 0xff)
+			Local1 = ~0x38
+			Local0 &= Local1
 			WRIT(0, 0x0c, Local0)
 
-			Store(READ(0, 0x02, 0xff), Local0)
-			Or(Local0, 0x80, Local0)
+			Local0 = READ (0, 0x02, 0xff)
+			Local0 |= 0x80
 			WRIT(0, 0x02, Local0)
 
-			Store(READ(0, 0x07, 0xff), Local0)
-			Not(0x20, Local1)
-			And (Local0, Local1, Local0)
+			Local0 = READ (0, 0x07, 0xff)
+			Local1 = ~0x20
+			Local0 &= Local1
 			WRIT(0, 0x07, Local0)
 		}
 
 		/* D0 state - Line drivers are on */
 		Method (_PS0, 0)
 		{
-			Store(READ(0, 0x02, 0xff), Local0)
-			Or(Local0, 0x80, Local0)
+			Local0 = READ (0, 0x02, 0xff)
+			Local0 |= 0x80
 			WRIT(0, 0x02, Local0)
 
-			Store (READ(0, 0x07, 0xff), Local0)
-			Not(0x20, Local1)
-			And(Local0, Local1, Local0)
+			Local0 = READ (0, 0x07, 0xff)
+			Local1 = ~0x20
+			Local0 &= Local1
 			WRIT(0, 0x07, Local0)
 		}
 
 		/* D3 State - Line drivers are off */
 		Method(_PS3, 0)
 		{
-			Store(READ(0, 0x02, 0xff), Local0)
-			Not(0x80, Local1)
-			And(Local0, Local1, Local0)
+			Local0 = READ (0, 0x02, 0xff)
+			Local1 = ~0x80
+			Local0 &= Local1
 			WRIT(0, 0x02, Local0)
 		}
 	}
@@ -354,13 +354,13 @@ Device (SIO1)
 			Acquire (SIOM, 0xffff)
 
 			// Is the hardware enabled?
-			Store (READ(0, 0x1b, 0xff), Local0)
-			If (LEqual(Local0, 0)) {
+			Local0 = READ (0, 0x1b, 0xff)
+			If (Local0 == 0) {
 				Return (0xd)
 			} Else {
 				// Power Enabled?
-				Store (READ(0, 0x02, 0x02), Local0)
-				If (LEqual(Local0, 0)) {
+				Local0 = READ (0, 0x02, 0x02)
+				If (Local0 == 0) {
 					Return (0x0d)
 				} Else {
 					Return (0x0f)
@@ -373,12 +373,12 @@ Device (SIO1)
 		{
 			WRIT(0, 0x1b, 0x00)
 
-			Store(READ(0, 0x1d, 0x0f), Local0)
+			Local0 = READ (0, 0x1d, 0x0f)
 			WRIT(0, 0x1d, Local0)
 
-			Store(READ(0, 0x02, 0xff), Local0)
-			Not(0x02, Local1)
-			And(Local0, Local1, Local0)
+			Local0 = READ (0, 0x02, 0xff)
+			Local1 = ~0x02
+			Local0 &= Local1
 			WRIT(0, 0x02, Local0)
 		}
 
@@ -403,8 +403,8 @@ Device (SIO1)
 				IRQNoFlags(_IRA) { 5 }
 			})
 
-			And (_STA(), 0x02, Local0)
-			If (LEqual(Local0, 0)) {
+			Local0 = _STA () & 0x02
+			If (Local0 == 0) {
 				Return(NONE)
 			}
 
@@ -416,15 +416,15 @@ Device (SIO1)
 				\_SB.PCI0.LPCB.SIO1.UAR3._CRS._IRA._INT, IRQ)
 
 			/* I/O Base */
-			Store (READ(0, 0x1b, 0xfe), Local0)
-			ShiftLeft(Local0, 0x02, Local0)
-			Store(Local0, IOMN)
-			Store(Local0, IOMX)
+			Local0 = READ (0x00, 0x1b, 0xfe)
+			Local0 <<= 2
+			IOMN = Local0
+			IOMX = Local0
 
 			/* Interrupt */
-			Store(READ(0, 0x1d, 0xf0), Local0)
-			ShiftRight(Local0, 4, Local0)
-			ShiftLeft(1, Local0, IRQ)
+			Local0 = READ (0, 0x1d, 0xf0)
+			Local0 >>= 4
+			IRQ = 1 << Local0
 			Return(RSRC)
 		}
 
@@ -437,29 +437,29 @@ Device (SIO1)
 
 			WRIT(0, 0x1b, 0)
 			FindSetRightBit(IRQL, Local0)
-			Decrement(Local0)
-			ShiftLeft(Local0, 4, Local0)
+			Local0--
+			Local0 <<= 4
 
-			Store(READ(0, 0x1d, 0x0f), Local1)
-			Or(Local0, Local1, Local0)
+			Local1 = READ (0, 0x1d, 0x0f)
+			Local0 |= Local1
 			WRIT(0, 0x1d, Local0)
 
-			Store(IOLO, Local0)
-			ShiftRight(Local0, 2, Local0)
-			And(Local0, 0xfe, Local0)
+			Local0 = IOLO
+			Local0 >>= 2
+			Local0 &= 0xfe
 
-			Store(IOHI, Local1)
-			ShiftLeft(Local1, 6, Local1)
-			Or (Local0, Local1, Local0)
+			Local1 = IOHI
+			Local1 <<= 6
+			Local0 |= Local1
 			WRIT(0, 0x1b, Local0)
 
-			Store(READ(0, 0x02, 0xff), Local0)
-			Or(Local0, 0x02, Local0)
+			Local0 = READ (0, 0x02, 0xff)
+			Local0 |= 0x02
 			WRIT(0, 0x02, Local0)
 
-			Store(READ(0, 0x07, 0xff), Local0)
-			Not(0x04, Local1)
-			And (Local0, Local1, Local0)
+			Local0 = READ (0, 0x07, 0xff)
+			Local1 = ~0x04
+			Local0 &= Local1
 			WRIT(0, 0x07, Local0)
 		}
 
@@ -467,22 +467,22 @@ Device (SIO1)
 		/* D0 state - Line drivers are on */
 		Method (_PS0, 0)
 		{
-			Store(READ(0, 0x02, 0xff), Local0)
-			Or(Local0, 0x02, Local0)
+			Local0 = READ (0, 0x02, 0xff)
+			Local0 |= 0x02
 			WRIT(0, 0x02, Local0)
 
-			Store (READ(0, 0x07, 0xff), Local0)
-			Not(0x04, Local1)
-			And(Local0, Local1, Local0)
+			Local0 = READ (0, 0x07, 0xff)
+			Local1 = ~0x04
+			Local0 &= Local1
 			WRIT(0, 0x07, Local0)
 		}
 
 		/* D3 State - Line drivers are off */
 		Method(_PS3, 0)
 		{
-			Store(READ(0, 0x02, 0xff), Local0)
-			Not(0x02, Local1)
-			And(Local0, Local1, Local0)
+			Local0 = READ (0, 0x02, 0xff)
+			Local1 = ~0x02
+			Local0 &= Local1
 			WRIT(0, 0x02, Local0)
 		}
 	}
@@ -501,13 +501,13 @@ Device (SIO1)
 			Acquire (SIOM, 0xffff)
 
 			// Is the hardware enabled?
-			Store (READ(0, 0x1c, 0xff), Local0)
-			If (LEqual(Local0, 0)) {
+			Local0 = READ (0, 0x1c, 0xff)
+			If (Local0 == 0) {
 				Return (0xd)
 			} Else {
 				// Power Enabled?
-				Store (READ(0, 0x02, 0x04), Local0)
-				If (LEqual(Local0, 0)) {
+				Local0 = READ (0, 0x02, 0x04)
+				If (Local0 == 0) {
 					Return (0x0d)
 				} Else {
 					Return (0x0f)
@@ -520,12 +520,12 @@ Device (SIO1)
 		{
 			WRIT(0, 0x1c, 0x00)
 
-			Store(READ(0, 0x1d, 0x0f), Local0)
+			Local0 = READ (0, 0x1d, 0x0f)
 			WRIT(0, 0x1d, Local0)
 
-			Store(READ(0, 0x02, 0xff), Local0)
-			Not(0x04, Local1)
-			And(Local0, Local1, Local0)
+			Local0 = READ (0, 0x02, 0xff)
+			Local1 = ~0x04
+			Local0 &= Local1
 			WRIT(0, 0x02, Local0)
 		}
 
@@ -550,8 +550,8 @@ Device (SIO1)
 				IRQNoFlags(_IRA) { 11 }
 			})
 
-			And (_STA(), 0x02, Local0)
-			If (LEqual(Local0, 0)) {
+			Local0 = _STA () & 0x02
+			If (Local0 == 0) {
 				Return(NONE)
 			}
 
@@ -563,15 +563,15 @@ Device (SIO1)
 				\_SB.PCI0.LPCB.SIO1.UAR4._CRS._IRA._INT, IRQ)
 
 			/* I/O Base */
-			Store (READ(0, 0x1c, 0xfe), Local0)
-			ShiftLeft(Local0, 0x02, Local0)
-			Store(Local0, IOMN)
-			Store(Local0, IOMX)
+			Local0 = READ (0, 0x1c, 0xfe)
+			Local0 <<= 2
+			IOMN = Local0
+			IOMX = Local0
 
 			/* Interrupt */
-			Store(READ(0, 0x1d, 0xf0), Local0)
-			ShiftRight(Local0, 4, Local0)
-			ShiftLeft(1, Local0, IRQ)
+			Local0 = READ (0, 0x1d, 0xf0)
+			Local0 >>= 4
+			IRQ = 1 << Local0
 			Return(RSRC)
 		}
 
@@ -584,29 +584,29 @@ Device (SIO1)
 
 			WRIT(0, 0x1c, 0)
 			FindSetRightBit(IRQL, Local0)
-			Decrement(Local0)
-			ShiftLeft(Local0, 4, Local0)
+			Local0--
+			Local0 <<= 4
 
-			Store(READ(0, 0x1d, 0x0f), Local1)
-			Or(Local0, Local1, Local0)
+			Local1 = READ (0x00, 0x1d, 0x0f)
+			Local0 |= Local1
 			WRIT(0, 0x1d, Local0)
 
-			Store(IOLO, Local0)
-			ShiftRight(Local0, 2, Local0)
-			And(Local0, 0xfe, Local0)
+			Local0 = IOLO
+			Local0 >>= 2
+			Local0 &= 0xfe
 
-			Store(IOHI, Local1)
-			ShiftLeft(Local1, 6, Local1)
-			Or (Local0, Local1, Local0)
+			Local1 = IOHI
+			Local1 <<= 6
+			Local0 |= Local1
 			WRIT(0, 0x1c, Local0)
 
-			Store(READ(0, 0x02, 0xff), Local0)
-			Or(Local0, 0x04, Local0)
+			Local0 = READ (0, 0x02, 0xff)
+			Local0 |= 0x04
 			WRIT(0, 0x02, Local0)
 
-			Store(READ(0, 0x07, 0xff), Local0)
-			Not(0x08, Local1)
-			And (Local0, Local1, Local0)
+			Local0 = READ (0, 0x07, 0xff)
+			Local1 = ~0x08
+			Local0 &= Local1
 			WRIT(0, 0x07, Local0)
 		}
 
@@ -614,22 +614,22 @@ Device (SIO1)
 		/* D0 state - Line drivers are on */
 		Method (_PS0, 0)
 		{
-			Store(READ(0, 0x02, 0xff), Local0)
-			Or(Local0, 0x04, Local0)
+			Local0 = READ (0, 0x02, 0xff)
+			Local0 |= 0x04
 			WRIT(0, 0x02, Local0)
 
-			Store (READ(0, 0x07, 0xff), Local0)
-			Not(0x08, Local1)
-			And(Local0, Local1, Local0)
+			Local0 = READ (0, 0x07, 0xff)
+			Local1 = ~0x08
+			Local0 &= Local1
 			WRIT(0, 0x07, Local0)
 		}
 
 		/* D3 State - Line drivers are off */
 		Method(_PS3, 0)
 		{
-			Store(READ(0, 0x02, 0xff), Local0)
-			Not(0x04, Local1)
-			And(Local0, Local1, Local0)
+			Local0 = READ (0, 0x02, 0xff)
+			Local1 = ~0x04
+			Local0 &= Local1
 			WRIT(0, 0x02, Local0)
 		}
 	}

src/mainboard/getac/p470/acpi/thermal.asl

@@ -17,11 +17,11 @@ Scope (\_TZ)
 		// Convert from °C to 1/10 Kelvin
 		Method(DEGR, 1, NotSerialized)
 		{
-			Store(Arg0, Local0)
+			Local0 = Arg0
 			// 10ths of degrees
-			Multiply(Local0, 10, Local0)
+			Local0 *= 10
 			// 0°C is 273.15 K, we need to round it.
-			Add(Local0, 2732, Local0)
+			Local0 += 2732
 			Return(Local0)
 		}
 
@@ -35,24 +35,24 @@ Scope (\_TZ)
 		// Critical shutdown temperature
 		Method (_CRT, 0, Serialized)
 		{
-			Store(\_SB.PCI0.LPCB.EC0.CRTT, Local0)
-			Store(DEGR(Local0), Local0)
+			Local0 = \_SB.PCI0.LPCB.EC0.CRTT
+			Local0 = DEGR (Local0)
 			Return(Local0)
 		}
 
 		// CPU throttling start temperature
 		Method (_PSV, 0, Serialized)
 		{
-			Store(\_SB.PCI0.LPCB.EC0.CTRO, Local0)
-			Store(DEGR(Local0), Local0)
+			Local0 = \_SB.PCI0.LPCB.EC0.CTRO
+			Local0 = DEGR (Local0)
 			Return(Local0)
 		}
 
 		// Get DTS Temperature
 		Method (_TMP, 0, Serialized)
 		{
-			Store(\_SB.PCI0.LPCB.EC0.CTMP, Local0)
-			Store(DEGR(Local0), Local0)
+			Local0 = \_SB.PCI0.LPCB.EC0.CTMP
+			Local0 = DEGR (Local0)
 			Return(Local0)
 		}
 

src/mainboard/google/auron/acpi_tables.c

@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <arch/ioapic.h>
 #include <acpi/acpi.h>
 #include <acpi/acpi_gnvs.h>
 #include <soc/acpi.h>
@@ -9,8 +8,6 @@
 
 void acpi_create_gnvs(struct global_nvs *gnvs)
 {
-	acpi_init_gnvs(gnvs);
-
 	/* Enable USB ports in S3 */
 	gnvs->s3u0 = 1;
 
@@ -24,18 +21,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs)
 	gnvs->flvl = 1;
 }
 
-unsigned long acpi_fill_madt(unsigned long current)
-{
-	/* Local APICs */
-	current = acpi_create_madt_lapics(current);
-
-	/* IOAPIC */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
-				2, IO_APIC_ADDR, 0);
-
-	return acpi_madt_irq_overrides(current);
-}
-
 void mainboard_fill_fadt(acpi_fadt_t *fadt)
 {
 	fadt->preferred_pm_profile = PM_MOBILE;

src/mainboard/google/auron/dsdt.asl

@@ -16,7 +16,7 @@ DefinitionBlock(
 	#include "acpi/thermal.asl"
 
 	// global NVS and variables
-	#include <soc/intel/broadwell/acpi/globalnvs.asl>
+	#include <soc/intel/broadwell/pch/acpi/globalnvs.asl>
 
 	// CPU
 	#include <cpu/intel/common/acpi/cpu.asl>
@@ -24,8 +24,8 @@ DefinitionBlock(
 	Scope (\_SB) {
 		Device (PCI0)
 		{
-			#include <soc/intel/broadwell/acpi/systemagent.asl>
-			#include <soc/intel/broadwell/acpi/pch.asl>
+			#include <soc/intel/broadwell/acpi/hostbridge.asl>
+			#include <soc/intel/broadwell/pch/acpi/pch.asl>
 			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}

src/mainboard/google/beltino/acpi/mainboard.asl

@@ -14,11 +14,11 @@ Scope (\_SB.PCI0.RP01)
 
 		Method (_DSW, 3, NotSerialized)
 		{
-			Store (NIC_WAKE_GPIO, Local0)
+			Local0 = NIC_WAKE_GPIO
 
-			If (LEqual (Arg0, 1)) {
+			If (Arg0 == 1) {
 				// Enable GPIO as wake source
-				\_SB.PCI0.LPCB.GWAK (Local0)
+				\_SB.PCI0.LPCB.GPIO.GWAK (Local0)
 			}
 		}
 	}
@@ -36,11 +36,11 @@ Scope (\_SB.PCI0.RP02)
 
 		Method (_DSW, 3, NotSerialized)
 		{
-			Store (WLAN_WAKE_GPIO, Local0)
+			Local0 = WLAN_WAKE_GPIO
 
-			If (LEqual (Arg0, 1)) {
+			If (Arg0 == 1) {
 				// Enable GPIO as wake source
-				\_SB.PCI0.LPCB.GWAK (Local0)
+				\_SB.PCI0.LPCB.GPIO.GWAK (Local0)
 			}
 		}
 	}

src/mainboard/google/beltino/acpi/thermal.asl

@@ -23,10 +23,10 @@ Scope (\_TZ)
 		// Convert from Degrees C to 1/10 Kelvin for ACPI
 		Method (CTOK, 1) {
 			// 10th of Degrees C
-			Multiply (Arg0, 10, Local0)
+			Local0 = Arg0 * 10
 
 			// Convert to Kelvin
-			Add (Local0, 2732, Local0)
+			Local0 += 2732
 
 			Return (Local0)
 		}
@@ -52,66 +52,66 @@ Scope (\_TZ)
 		// Start fan at state 4 = lowest temp state
 		Method (_INI)
 		{
-			Store (4, \FLVL)
-			Store (FAN4_PWM, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+			\FLVL = 4
+			\_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN4_PWM
 			Notify (\_TZ.THRM, 0x81)
 		}
 
 		Method (TCHK, 0, Serialized)
 		{
 			// Get CPU Temperature from PECI via SuperIO TMPIN3
-			Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN3, Local0)
+			Local0 = \_SB.PCI0.LPCB.SIO.ENVC.TIN3
 
 			// Check for "no reading available"
-			If (LEqual (Local0, 0x80)) {
+			If (Local0 == 0x80) {
 				Return (CTOK (FAN0_THRESHOLD_ON))
 			}
 
 			// Check for invalid readings
-			If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) {
+			If ((Local0 == 255) || (Local0 == 0)) {
 				Return (CTOK (FAN0_THRESHOLD_ON))
 			}
 
 			// PECI raw value is an offset from Tj_max
-			Subtract (255, Local0, Local1)
+			Local1 = 255 - Local0
 
 			// Handle values greater than Tj_max
-			If (LGreaterEqual (Local1, \TMAX)) {
+			If (Local1 >= \TMAX) {
 				Return (CTOK (\TMAX))
 			}
 
 			// Subtract from Tj_max to get temperature
-			Subtract (\TMAX, Local1, Local0)
+			Local0 = \TMAX - Local1
 			Return (CTOK (Local0))
 		}
 
 		Method (_TMP, 0, Serialized)
 		{
 			// Get temperature from SuperIO in deci-kelvin
-			Store (TCHK (), Local0)
+			Local0 = TCHK ()
 
 			// Critical temperature in deci-kelvin
-			Store (CTOK (\TMAX), Local1)
+			Local1 = CTOK (\TMAX)
 
-			If (LGreaterEqual (Local0, Local1)) {
-				Store ("CRITICAL TEMPERATURE", Debug)
-				Store (Local0, Debug)
+			If (Local0 >= Local1) {
+				Debug = "CRITICAL TEMPERATURE"
+				Debug = Local0
 
 				// Wait 1 second for SuperIO to re-poll
 				Sleep (1000)
 
 				// Re-read temperature from SuperIO
-				Store (TCHK (), Local0)
+				Local0 = TCHK ()
 
-				Store ("RE-READ TEMPERATURE", Debug)
-				Store (Local0, Debug)
+				Debug = "RE-READ TEMPERATURE"
+				Debug = Local0
 			}
 
 			Return (Local0)
 		}
 
 		Method (_AC0) {
-			If (LLessEqual (\FLVL, 0)) {
+			If (\FLVL <= 0) {
 				Return (CTOK (FAN0_THRESHOLD_OFF))
 			} Else {
 				Return (CTOK (FAN0_THRESHOLD_ON))
@@ -119,7 +119,7 @@ Scope (\_TZ)
 		}
 
 		Method (_AC1) {
-			If (LLessEqual (\FLVL, 1)) {
+			If (\FLVL <= 1) {
 				Return (CTOK (FAN1_THRESHOLD_OFF))
 			} Else {
 				Return (CTOK (FAN1_THRESHOLD_ON))
@@ -127,7 +127,7 @@ Scope (\_TZ)
 		}
 
 		Method (_AC2) {
-			If (LLessEqual (\FLVL, 2)) {
+			If (\FLVL <= 2) {
 				Return (CTOK (FAN2_THRESHOLD_OFF))
 			} Else {
 				Return (CTOK (FAN2_THRESHOLD_ON))
@@ -135,7 +135,7 @@ Scope (\_TZ)
 		}
 
 		Method (_AC3) {
-			If (LLessEqual (\FLVL, 3)) {
+			If (\FLVL <= 3) {
 				Return (CTOK (FAN3_THRESHOLD_OFF))
 			} Else {
 				Return (CTOK (FAN3_THRESHOLD_ON))
@@ -143,7 +143,7 @@ Scope (\_TZ)
 		}
 
 		Method (_AC4) {
-			If (LLessEqual (\FLVL, 4)) {
+			If (\FLVL <= 4) {
 				Return (CTOK (FAN4_THRESHOLD_OFF))
 			} Else {
 				Return (CTOK (FAN4_THRESHOLD_ON))
@@ -159,25 +159,23 @@ Scope (\_TZ)
 		PowerResource (FNP0, 0, 0)
 		{
 			Method (_STA) {
-				If (LLessEqual (\FLVL, 0)) {
+				If (\FLVL <= 0) {
 					Return (One)
 				} Else {
 					Return (Zero)
 				}
 			}
 			Method (_ON)  {
-				If (LNot (_STA ())) {
-					Store (0, \FLVL)
-					Store (FAN0_PWM,
-						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+				If (!_STA ()) {
+					\FLVL = 0
+					\_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN0_PWM
 					Notify (\_TZ.THRM, 0x81)
 				}
 			}
 			Method (_OFF) {
 				If (_STA ()) {
-					Store (1, \FLVL)
-					Store (FAN1_PWM,
-						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+					\FLVL = 1
+					\_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN1_PWM
 					Notify (\_TZ.THRM, 0x81)
 				}
 			}
@@ -186,25 +184,23 @@ Scope (\_TZ)
 		PowerResource (FNP1, 0, 0)
 		{
 			Method (_STA) {
-				If (LLessEqual (\FLVL, 1)) {
+				If (\FLVL <= 1) {
 					Return (One)
 				} Else {
 					Return (Zero)
 				}
 			}
 			Method (_ON)  {
-				If (LNot (_STA ())) {
-					Store (1, \FLVL)
-					Store (FAN1_PWM,
-						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+				If (!_STA ()) {
+					\FLVL = 1
+					\_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN1_PWM
 					Notify (\_TZ.THRM, 0x81)
 				}
 			}
 			Method (_OFF) {
 				If (_STA ()) {
-					Store (2, \FLVL)
-					Store (FAN2_PWM,
-						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+					\FLVL = 2
+					\_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN2_PWM
 					Notify (\_TZ.THRM, 0x81)
 				}
 			}
@@ -213,25 +209,23 @@ Scope (\_TZ)
 		PowerResource (FNP2, 0, 0)
 		{
 			Method (_STA) {
-				If (LLessEqual (\FLVL, 2)) {
+				If (\FLVL <= 2) {
 					Return (One)
 				} Else {
 					Return (Zero)
 				}
 			}
 			Method (_ON)  {
-				If (LNot (_STA ())) {
-					Store (2, \FLVL)
-					Store (FAN2_PWM,
-						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+				If (!_STA ()) {
+					\FLVL = 2
+					\_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN2_PWM
 					Notify (\_TZ.THRM, 0x81)
 				}
 			}
 			Method (_OFF) {
 				If (_STA ()) {
-					Store (3, \FLVL)
-					Store (FAN3_PWM,
-						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+					\FLVL = 3
+					\_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN3_PWM
 					Notify (\_TZ.THRM, 0x81)
 				}
 			}
@@ -240,25 +234,23 @@ Scope (\_TZ)
 		PowerResource (FNP3, 0, 0)
 		{
 			Method (_STA) {
-				If (LLessEqual (\FLVL, 3)) {
+				If (\FLVL <= 3) {
 					Return (One)
 				} Else {
 					Return (Zero)
 				}
 			}
 			Method (_ON)  {
-				If (LNot (_STA ())) {
-					Store (3, \FLVL)
-					Store (FAN3_PWM,
-						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+				If (!_STA ()) {
+					\FLVL = 3
+					\_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN3_PWM
 					Notify (\_TZ.THRM, 0x81)
 				}
 			}
 			Method (_OFF) {
 				If (_STA ()) {
-					Store (4, \FLVL)
-					Store (FAN4_PWM,
-						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+					\FLVL = 4
+					\_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN4_PWM
 					Notify (\_TZ.THRM, 0x81)
 				}
 			}
@@ -267,25 +259,23 @@ Scope (\_TZ)
 		PowerResource (FNP4, 0, 0)
 		{
 			Method (_STA) {
-				If (LLessEqual (\FLVL, 4)) {
+				If (\FLVL <= 4) {
 					Return (One)
 				} Else {
 					Return (Zero)
 				}
 			}
 			Method (_ON)  {
-				If (LNot (_STA ())) {
-					Store (4, \FLVL)
-					Store (FAN4_PWM,
-						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+				If (!_STA ()) {
+					\FLVL = 4
+					\_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN4_PWM
 					Notify (\_TZ.THRM, 0x81)
 				}
 			}
 			Method (_OFF) {
 				If (_STA ()) {
-					Store (4, \FLVL)
-					Store (FAN4_PWM,
-						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+					\FLVL = 4
+					\_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN4_PWM
 					Notify (\_TZ.THRM, 0x81)
 				}
 			}

src/mainboard/google/beltino/devicetree.cb

@@ -45,8 +45,6 @@ chip northbridge/intel/haswell
 			register "gpe0_en_3" = "0x00000000"
 			register "gpe0_en_4" = "0x00000000"
 
-			register "ide_legacy_combined" = "0x0"
-			register "sata_ahci" = "0x1"
 			register "sata_port_map" = "0x1"
 			register "sata_devslp_disable" = "0x1"
 

src/mainboard/google/beltino/dsdt.asl

@@ -24,7 +24,7 @@ DefinitionBlock(
 	Scope (\_SB) {
 		Device (PCI0)
 		{
-			#include <northbridge/intel/haswell/acpi/haswell.asl>
+			#include <northbridge/intel/haswell/acpi/hostbridge.asl>
 			#include <southbridge/intel/lynxpoint/acpi/pch.asl>
 		}
 	}

src/mainboard/google/cheza/Kconfig

@@ -1,46 +0,0 @@
-
-config BOARD_GOOGLE_CHEZA_COMMON  # Umbrella option to be selected by variants
-	def_bool n
-
-if BOARD_GOOGLE_CHEZA_COMMON
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	select BOARD_ROMSIZE_KB_16384
-	select COMMON_CBFS_SPI_WRAPPER
-	select EC_GOOGLE_CHROMEEC
-	select EC_GOOGLE_CHROMEEC_RTC
-	select EC_GOOGLE_CHROMEEC_SPI
-	select RTC
-	select SOC_QUALCOMM_SDM845
-	select SPI_FLASH
-	select SPI_FLASH_WINBOND
-	select MAINBOARD_HAS_CHROMEOS
-	select MAINBOARD_HAS_TPM2
-	select MAINBOARD_HAS_SPI_TPM_CR50
-
-config VBOOT
-	select EC_GOOGLE_CHROMEEC_SWITCHES
-	select VBOOT_VBNV_FLASH
-
-config MAINBOARD_DIR
-	string
-	default "google/cheza"
-
-config DRIVER_TPM_SPI_BUS
-	hex
-	default 0x5
-
-config EC_GOOGLE_CHROMEEC_SPI_BUS
-	hex
-	default 0xa
-
-##########################################################
-#### Update below when adding a new derivative board. ####
-##########################################################
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "Cheza" if BOARD_GOOGLE_CHEZA
-
-endif # BOARD_GOOGLE_CHEZA_COMMON

src/mainboard/google/cheza/Kconfig.name

@@ -1,4 +0,0 @@
-
-config BOARD_GOOGLE_CHEZA
-	bool "Cheza"
-	select BOARD_GOOGLE_CHEZA_COMMON

src/mainboard/google/cheza/Makefile.inc

@@ -1,20 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
-bootblock-y += boardid.c
-bootblock-y += chromeos.c
-bootblock-y += bootblock.c
-bootblock-y += reset.c
-
-verstage-y += boardid.c
-verstage-y += chromeos.c
-verstage-y += reset.c
-
-romstage-y += boardid.c
-romstage-y += chromeos.c
-romstage-y += romstage.c
-romstage-y += reset.c
-
-ramstage-y += boardid.c
-ramstage-y += chromeos.c
-ramstage-y += mainboard.c
-ramstage-y += reset.c

src/mainboard/google/cheza/board.h

@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef __COREBOOT_SRC_MAINBOARD_GOOGLE_CHEZA_BOARD_H
-#define __COREBOOT_SRC_MAINBOARD_GOOGLE_CHEZA_BOARD_H
-
-#include <gpio.h>
-#include <soc/gpio.h>
-
-#define GPIO_EC_IN_RW	GPIO(11)
-#define GPIO_AP_EC_INT	GPIO(122)
-#define GPIO_AP_SUSPEND	GPIO(126)
-#define GPIO_WP_STATE	GPIO(128)
-#define GPIO_H1_AP_INT	GPIO(129)
-
-void setup_chromeos_gpios(void);
-
-#endif  /* ! __COREBOOT_SRC_MAINBOARD_GOOGLE_CHEZA_BOARD_H */