Merge remote-tracking branch 'upstream/master' into galp5

Change-Id: I13cd0997db873191951e5c74c819b00acbbf1e89

Documentation/mainboard/hp/folio_9480m.md

@@ -0,0 +1,156 @@
+# HP EliteBook Folio 9480m
+
+This page is about the notebook [HP EliteBook Folio 9480m].
+
+## Release status
+
+HP EliteBook Folio 9480m was released in 2014 and is now end of life.
+It can be bought from a secondhand market like Taobao or eBay.
+
+## Required proprietary blobs
+
+The following blobs are required to operate the hardware:
+
+1. EC firmware
+2. Intel ME firmware
+3. mrc.bin
+
+HP EliteBook Folio 9480m uses SMSC MEC1322 as its embedded controller.
+The EC firmware is stored in the flash chip, but we don't need to touch it
+or use it in the coreboot build process.
+
+Intel ME firmware is in the flash chip. It is not needed when building coreboot.
+
+The Haswell memory reference code binary is needed when building coreboot.
+Please see [mrc.bin](../../northbridge/intel/haswell/mrc.bin).
+
+## Programming
+
+Before flashing, remove the battery and the hard drive cover according to the
+[Maintenance and Service Guide] of this laptop.
+
+![Two flash chips of HP EliteBook Folio 9480m](folio_9480m_flash.webp)
+
+HP EliteBook Folio 9480m has two flash chips, a 16MiB system flash, and a 2MiB
+private flash. To install coreboot, we need to program both flash chips.
+Read [HP Sure Start] for detailed information.
+
+To access the system flash, we need to connect the AC adapter to the machine,
+then clip on the flash chip with an SOIC-8 clip. An [STM32-based flash programmer]
+made with an STM32 development board is tested to work.
+
+To access the private flash chip, we can use a ch341a based flash programmer and
+flash the chip with the AC adapter disconnected.
+
+Before flashing coreboot, we need to do the following:
+
+1. Erase the private flash to disable the IFD protection
+2. Modify the IFD to shrink the BIOS region, so that we'll not use or override
+   the protected bootblock and PEI region, as well as the EC firmware
+
+To erase the private flash chip, attach it with the flash programmer via the SOIC-8 clip,
+then run:
+
+    flashrom -p <programmer> --erase
+
+To modify the IFD, we need a new flash layout. The flash layout of the OEM firmware is:
+
+    00000000:00000fff fd
+    00001000:00002fff gbe
+    00003000:005fffff me
+    00600000:00ffffff bios
+
+The default coreboot configuration sets the flash chip size to 12MiB, so set the end of the
+BIOS region to 0xbfffff in the new layout. The modified IFD is as follows (Platform Data
+region pd is the region protected by HP Sure Start):
+
+    00000000:00000fff fd
+    00001000:00002fff gbe
+    00003000:005fffff me
+    00600000:00bfffff bios
+    00eb5000:00ffffff pd
+
+Write the above layout in a file, and use ifdtool to modify the IFD of a flash image.
+Suppose the above layout file is ``layout.txt`` and the origin content of the system flash
+is in ``factory-sys.rom``, run:
+
+    ifdtool -n layout.txt factory-sys.rom
+
+Then a flash image with a new IFD will be in ``factory-sys.rom.new``.
+
+Flash the IFD of the system flash:
+
+    flashrom -p <programmer> --ifd -i fd -w factory-sys.rom.new
+
+Then flash the coreboot image:
+
+    # first extend the 12M coreboot.rom to 16M
+    fallocate -l 16M build/coreboot.rom
+    flashrom -p <programmer> --ifd -i bios -w build/coreboot.rom
+
+After coreboot is installed, the coreboot firmware can be updated with internal flashing:
+
+    flashrom -p internal --ifd -i bios --noverify-all -w build/coreboot.rom
+
+## Debugging
+
+The board can be debugged with EHCI debug. The EHCI debug port is the USB port on the left.
+
+## Test status
+
+### Known issues
+
+- GRUB payload freezes just like previous EliteBook laptops
+- Sometimes the PCIe WLAN module can not be found in the OS after booting to the system
+- Sometimes all the USB devices can not be found in the OS after S3 resume
+
+### Untested
+
+- Fingerprint reader
+- Smart Card reader
+
+### Working
+
+- i5-4310U CPU with 4G+4G memory
+- SATA and M.2 SATA disk
+- Ethernet
+- WLAN
+- WWAN
+- SD card reader
+- USB
+- Keyboard and touchpad
+- DisplayPort
+- VGA
+- Dock
+- Audio output from speaker and headphone jack
+- Webcam
+- TPM
+- EC ACPI
+- S3 resume
+- Arch Linux with Linux 5.8.9
+- Memory initialization with mrc.bin version 1.6.1 Build 2
+- Graphics initialization with libgfxinit
+- Payload: SeaBIOS, Tianocore
+- EC firmware
+  - KBC Revision 92.15 from OEM firmware version 01.33
+  - KBC Revision 92.17 from OEM firmware version 01.50
+- Internal flashing under coreboot
+
+## Technology
+
+```eval_rst
++------------------+-----------------------------+
+| CPU              | Intel Haswell-ULT           |
++------------------+-----------------------------+
+| PCH              | Intel Lynx Point Low Power  |
++------------------+-----------------------------+
+| EC               | SMSC MEC1322                |
++------------------+-----------------------------+
+| Coprocessor      | Intel Management Engine     |
++------------------+-----------------------------+
+```
+
+[HP EliteBook Folio 9480m]: https://support.hp.com/us-en/product/hp-elitebook-folio-9480m-notebook-pc/7089926
+[Maintenance and Service Guide]: http://h10032.www1.hp.com/ctg/Manual/c05228980
+[STM32-based flash programmer]: https://github.com/dword1511/stm32-vserprog
+[HP Sure Start]: hp_sure_start.md

Documentation/mainboard/hp/hp_sure_start.md

@@ -0,0 +1,60 @@
+# HP Sure Start
+
+According to the [HP Sure Start Technical Whitepaper], HP Sure Start is a chipset
+and processor independent firmware intrusion detection and automatic repair system.
+It is implemented in HP notebooks since 2013, and desktops since 2015.
+
+This document talks about some mechanism of HP Sure Start on some machines, and
+the method to bypass it.
+
+## Laptops with SMSC MEC1322 embedded controller
+
+Haswell EliteBook, ZBook and ProBook 600 series use SMSC MEC1322 embedded controller.
+The EC firmware implements HP Sure Start.
+
+A Haswell EliteBook has two flash chips. According to the strings in the EC firmware,
+the 16MiB flash chip that stores the BIOS firmware is called the *system flash*, and
+the 2MiB flash chip that stores part of the system flash content is called the
+*private flash*. A Haswell ProBook 600 series laptop also uses MEC1322 and has similar
+EC firmware, but the HP Sure Start functions are not enabled.
+
+The private flash is connected to the EC, and is not accessible by the OS.
+It contains the following:
+
+- HP Sure Start policy header (starting with the string "POLI")
+- A copy of the Intel Flash Descriptor
+- A copy of the GbE firmware
+- Machine Unique Data (MUD)
+- Hashes of the IFD, GbE firmware and MUD, the hash algorithm is unknown
+- A copy of the bootblock, UEFI PEI stage, and microcode
+
+If the IFD of the system flash does not match the hash in the private flash, for example,
+modifying the IFD with ``ifdtool -u`` or ``me_cleaner -S``, the EC will recover the IFD.
+
+If the content of the private flash is lost, the EC firmware will still copy the IFD,
+bootblock and PEI to the private flash. However, the IFD is not protected after that.
+
+HP Sure Start also verifies bootblock, PEI, and microcode without using the private flash.
+EC firmware reads them from an absolute address of the system flash chip, which is
+hardcoded in the EC firmware. It looks like this verification is done with a digital
+signature. If the PEI volume is modified, EC firmware will recover it using the copy
+in the private flash. If the private flash has no valid copies of the PEI volume, and
+the PEI volume is modified, the machine will refuse to boot with the CapsLock LED blinking.
+
+## Bypassing HP Sure Start
+
+First search the mainboard for the flash chips. If there are two flash chips,
+the smaller one may be the private flash.
+
+For Intel boards, try to modify the IFD with ``ifdtool -u``, power on and shut down
+the machine, then read the flash again. If the IFD is not modified, it is likely to
+be recovered from the private flash. Find the private flash and erase it, then the IFD
+can be modified.
+
+To bypass the bootblock and PEI verification, we can modify the IFD to make the
+BIOS region not overlap with the protected region. Since the EC firmware is usually
+located at the high address of the flash chip (and in the protected region),
+we can leave it untouched, and do not need to extract the EC firmware to put it in
+the coreboot image.
+
+[HP Sure Start Technical Whitepaper]: http://h10032.www1.hp.com/ctg/Manual/c05163901

Documentation/mainboard/index.md

@@ -61,8 +61,10 @@ The boards in this section are not real mainboards, but emulators.
 ### EliteBook series
 
 - [HP Laptops with KBC1126 EC](hp/hp_kbc1126_laptops.md)
+- [HP Sure Start](hp/hp_sure_start.md)
 - [EliteBook 2560p](hp/2560p.md)
 - [EliteBook 8760w](hp/8760w.md)
+- [EliteBook Folio 9480m](hp/folio_9480m.md)
 
 ## Intel
 

Documentation/mainboard/purism/librem_mini.md

@@ -1,16 +1,19 @@
-# Purism Librem Mini
+# Purism Librem Mini (v1, v2)
 
 This page describes how to run coreboot on the [Purism Librem Mini].
 
 ```eval_rst
 +------------------+--------------------------------------------------+
-| CPU              | Intel Core i7-8565U/8665U                        |
+| CPU              | Intel Core i7-8565U/8665U (v1)                   |
+|                  | Intel Core i7-10510U      (v2)                   |
 +------------------+--------------------------------------------------+
-| PCH              | Whiskey Lake / Cannon Point LP                   |
+| PCH              | Whiskey Lake / Cannon Point LP       (v1)        |
+|                  | Comet Lake LP Premium (Comet Lake-U) (v2)        |
 +------------------+--------------------------------------------------+
 | Super I/O, EC    | ITE IT8528E                                      |
 +------------------+--------------------------------------------------+
-| Coprocessor      | Intel Management Engine (CSME 12.x)              |
+| Coprocessor      | Intel Management Engine (CSME 12.x) (v1)         |
+|                  | Intel Management Engine (CSME 14.x) (v2)         |
 +------------------+--------------------------------------------------+
 ```
 
@@ -34,9 +37,9 @@ only the BIOS region is being modified).
 +-----------------+---------------------------------+---------------------+
 ```
 
-FSP-M and FSP-S are obtained after splitting the Coffee Lake FSP binary (done
+FSP-M and FSP-S are obtained after splitting the FSP binary (done automatically
-automatically by the coreboot build system and included into the image) from
+by the coreboot build system and included into the image; Coffee Lake for v1,
-the `3rdparty/fsp` submodule.
+Comet Lake for v2) from the `3rdparty/fsp` submodule.
 
 Microcode updates are automatically included into the coreboot image by the build
 system from the `3rdparty/intel-microcode` submodule. Official Purism release
@@ -50,12 +53,14 @@ the [purism-blobs] repository.
 
 ## Intel Management Engine
 
-The Librem Mini uses version 12.x of the Intel Management Engine (ME) /
+The Librem Mini uses version 12.x (v1) or 14.x (v2) of the Intel Management
-Converged Security Engine (CSE). The ME/CSE is disabled using the High
+Engine (ME) / Converged Security Engine (CSE). The ME/CSE is disabled using
-Assurance Platform (HAP) bit, which puts the ME into a disabled state
+the High Assurance Platform (HAP) bit, which puts the ME into a disabled state
 after platform bring-up (BUP) and disables all PCI/HECI interfaces.
 This can be verified via the coreboot cbmem utility:
-`sudo ./cbmem -1 | grep 'ME:'`
+
+    `sudo ./cbmem -1 | grep 'ME:'`
+
 provided coreboot has been modified to output the ME status even when
 the PCI device is not visible/active (as it is in Purism's release builds).
 
@@ -64,8 +69,9 @@ the PCI device is not visible/active (as it is in Purism's release builds).
 ### Internal programming
 
 The main SPI flash can be accessed using [flashrom]. The first version
-supporting the chipset is flashrom v1.2. Firmware an be easily flashed
+supporting the chipset is flashrom v1.2 (v1.2-107-gb1f858f or later needed
-with internal programmer (either BIOS region or full image).
+for the Mini v2). Firmware an be easily flashed with internal programmer
+(either BIOS region or full image).
 
 ### External programming
 
@@ -100,17 +106,17 @@ desoldering it from the mainboard.
 ## Working
 
  * External displays via HDMI/DisplayPort with VGA option ROM or FSP/GOP init
-  (no libgfxinit support yet)
+   (no libgfxinit support yet)
- * SeaBIOS (1.13.x), Tianocore (CorebootPayloadpkg), Heads (Purism downstream) payloads
+ * SeaBIOS (1.14), Tianocore (CorebootPayloadPkg), Heads (Purism downstream) payloads
  * Ethernet, m.2 2230 Wi-Fi
  * System firmware updates via flashrom
  * PCIe NVMe
  * m.2 and SATA III
  * Audio via front 3.5mm jack, HDMI, and DisplayPort
  * SMBus (reading SPD from DIMMs)
- * Initialization with CFL FSP 2.0
+ * Initialization with FSP 2.0 (CFL for v1, CML for v2)
  * S3 Suspend/Resume
- * Booting PureOS 9.x, Debian 10.x, Qubes 4.0.3, Linux Mint 19.3, Windows 10 2004
+ * Booting PureOS 10.x, Debian 11.x, Qubes 4.1.0-alpha1, Linux Mint 20, Windows 10 2004
 
 ## Not working / untested
 

Documentation/releases/coreboot-4.13-relnotes.md

@@ -13,6 +13,27 @@ Update this document with changes that should be in the release notes.
 Significant changes
 -------------------
 
+### Native refcode implementation for Bay Trail
+
+Bay Trail no longer needs a refcode binary to function properly. The refcode
+was reimplemented as coreboot code, which should be functionally equivalent.
+Thus, coreboot only needs to run the MRC.bin to successfully boot Bay Trail.
+
+### Unusual config files to build test more code
+
+There's some new highly-unusual config files, whose only purpose is to coerce
+Jenkins into build-testing several disabled-by-default coreboot config options.
+This prevents them from silently decaying over time because of build failures.
+
+### Initial support for Intel Trusted eXecution Technology
+
+coreboot now supports enabling Intel TXT. Though it's not feature-complete yet,
+the code allows successfully launching tboot, a Measured Launch Environment. It
+was tested on Haswell using an Asrock B85M Pro4 mainboard with TPM 2.0 on LPC.
+Though support for other platforms is still not ready, it is being worked on.
+The Haswell MRC.bin needs to be patched so as to enable DPR. Given that the MRC
+binary cannot be redistributed, the best long-term solution is to replace it.
+
 ### Hidden PCI devices
 
 This new functionality takes advantage of the existing 'hidden' keyword in the
@@ -49,6 +70,15 @@ the 64K segment to accomodate additional CPUs and in theory allows as many
 CPU threads as possible limited only by SMRAM space and not by 64K. By default
 this loader version is disabled. Please see cpu/x86/Kconfig for more info.
 
+### Address Sanitizer
+
+coreboot now has an in-built Address Sanitizer, a runtime memory debugger
+designed to find out-of-bounds access and use-after-scope bugs. It is made
+available on all x86 platforms in ramstage and on QEMU i440fx, Intel Apollo
+Lake, and Haswell in romstage. Further, it can be enabled in romstage on other
+x86 platforms as well. Refer [ASan documentation](../technotes/asan.md) for
+more info.
+
 ### Initial support for x86_64
 
 The x86_64 code support has been revived and enabled for qemu. While it started

Documentation/security/vboot/list_vboot.md

@@ -20,7 +20,6 @@
 - Tricky (Dell Chromebox 3010)
 - Zako (HP Chromebox G1)
 - Butterfly (HP Pavilion Chromebook 14)
-- Cheza
 - Banon (Acer Chromebook 15 (CB3-532))
 - Celes (Samsung Chromebook 3)
 - Cyan (Acer Chromebook R11 (C738T))

MAINTAINERS

@@ -212,7 +212,7 @@ CLEVO MAINBOARDS
 M:	Felix Singer <felixsinger@posteo.net>
 M:	Michael Niewöhner <foss@mniewoehner.de>
 S:	Supported
-F:	src/mainboard/clevo
+F:	src/mainboard/clevo/
 
 
 
@@ -401,7 +401,7 @@ F:	src/mainboard/supermicro/x10slm-f/
 SUPERMICRO X11-LGA1151-SERIES
 M:	Michael Niewöhner <foss@mniewoehner.de>
 S:	Maintained
-F:	src/mainboard/supermicro/x11-lga1151-series
+F:	src/mainboard/supermicro/x11-lga1151-series/
 
 ################################################################################
 # Architectures

Makefile.inc

@@ -83,7 +83,7 @@ subdirs-y += src/superio
 subdirs-y += $(wildcard src/drivers/*) $(wildcard src/drivers/*/*) $(wildcard src/drivers/*/*/*)
 subdirs-y += src/cpu src/vendorcode
 subdirs-y += util/cbfstool util/sconfig util/nvramtool util/pgtblgen util/amdfwtool
-subdirs-y += util/futility util/marvell util/bincfg util/supermicro
+subdirs-y += util/futility util/marvell util/bincfg util/supermicro util/qemu
 subdirs-y += $(wildcard src/arch/*)
 subdirs-y += src/mainboard/$(MAINBOARDDIR)
 subdirs-y += src/security
@@ -732,6 +732,16 @@ TXTIBB :=
 
 endif
 
+ifeq ($(CONFIG_INTEL_CBNT_SUPPORT),y)
+
+CBNTIBB := --cbnt
+
+else
+
+CBNTIBB :=
+
+endif # CONFIG_INTEL_CBNT_SUPPORT
+
 ifeq ($(CONFIG_COMPRESS_BOOTBLOCK),y)
 
 $(objcbfs)/bootblock.lz4: $(objcbfs)/bootblock.elf $(objutil)/cbfstool/cbfs-compression-tool
@@ -1063,6 +1073,7 @@ $(obj)/fmap.fmap: $(obj)/fmap.fmd $(FMAPTOOL)
 ifeq ($(CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK),y)
 TS_OPTIONS := -j $(CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE)
 endif
+
 ifneq ($(CONFIG_UPDATE_IMAGE),y)
 $(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) $(IFITTOOL) $$(cpu_ucode_cbfs_file) $(obj)/fmap.fmap $(obj)/fmap.desc
 	$(CBFSTOOL) $@.tmp create -M $(obj)/fmap.fmap -r $(shell cat $(obj)/fmap.desc)
@@ -1072,6 +1083,7 @@ ifeq ($(CONFIG_ARCH_X86),y)
 		-n bootblock \
 		-t bootblock \
 		$(TXTIBB) \
+		$(CBNTIBB) \
 		-b -$(call file-size,$(objcbfs)/bootblock.bin) $(cbfs-autogen-attributes) \
 		$(TS_OPTIONS)
 else # ifeq ($(CONFIG_ARCH_X86),y)

payloads/libpayload/Makefile.inc

@@ -55,7 +55,8 @@ subdirs-$(CONFIG_LP_CBFS) += libcbfs
 subdirs-$(CONFIG_LP_LZMA) += liblzma
 subdirs-$(CONFIG_LP_LZ4) += liblz4
 
-INCLUDES := -Iinclude -Iinclude/$(ARCHDIR-y) -I$(obj) -include include/kconfig.h
+INCLUDES := -Iinclude -Iinclude/$(ARCHDIR-y) -I$(obj)
+INCLUDES += -include include/kconfig.h -include include/compiler.h
 
 CFLAGS +=  $(EXTRA_CFLAGS) $(INCLUDES) -Os -pipe -nostdinc -ggdb3
 CFLAGS += -nostdlib -fno-builtin -ffreestanding -fomit-frame-pointer

payloads/libpayload/bin/lpgcc

@@ -152,7 +152,8 @@ fi
 trygccoption -fno-stack-protector
 [ $? -eq 0 ] && _CFLAGS="$_CFLAGS -fno-stack-protector"
 
-_CFLAGS="$_CFLAGS -include $BASE/../include/kconfig.h -I`$DEFAULT_CC $_ARCHEXTRA -print-search-dirs | head -n 1 | cut -d' ' -f2`include"
+_CFLAGS="$_CFLAGS -include $BASE/../include/kconfig.h -include $BASE/../include/compiler.h"
+_CFLAGS="$_CFLAGS -I`$DEFAULT_CC $_ARCHEXTRA -print-search-dirs | head -n 1 | cut -d' ' -f2`include"
 
 _LDFLAGS="-L$BASE/../lib -L$_LIBDIR $_LDSCRIPT -static"
 

payloads/libpayload/configs/config.cheza

@@ -1,3 +0,0 @@
-CONFIG_LP_CHROMEOS=y
-CONFIG_LP_ARCH_ARM64=y
-CONFIG_LP_TIMER_ARM64_ARCH=y

payloads/libpayload/drivers/storage/storage.c

@@ -28,9 +28,7 @@
 
 #include <libpayload.h>
 #include <pci/pci.h>
-#if CONFIG(LP_STORAGE_AHCI)
+#include <storage/ahci.h>
-# include <storage/ahci.h>
-#endif
 #include <storage/storage.h>
 
 static storage_dev_t **devices = NULL;

payloads/libpayload/drivers/usb/ohci_private.h

@@ -36,7 +36,7 @@
 	// FIXME: fake
 	typedef enum { CMD} reg;
 
-	enum {
+	enum HcRhDescriptorAReg {
 		NumberDownstreamPorts = 1 << 0,
 		PowerSwitchingMode = 1 << 8,
 		NoPowerSwitching = 1 << 9,
@@ -44,19 +44,19 @@
 		OverCurrentProtectionMode = 1 << 11,
 		NoOverCurrentProtection = 1 << 12,
 		PowerOnToPowerGoodTime = 1 << 24
-	} HcRhDescriptorAReg;
+	};
 
-	enum {
+	enum HcRhDescriptorAMask {
 		NumberDownstreamPortsMask = MASK(0, 8),
 		PowerOnToPowerGoodTimeMask = MASK(24, 8)
-	} HcRhDescriptorAMask;
+	};
 
-	enum {
+	enum HcRhDescriptorBReg {
 		DeviceRemovable = 1 << 0,
 		PortPowerControlMask = 1 << 16
-	} HcRhDescriptorBReg;
+	};
 
-	enum {
+	enum HcRhPortStatusRead {
 		CurrentConnectStatus		= 1 << 0,
 		PortEnableStatus		= 1 << 1,
 		PortSuspendStatus		= 1 << 2,
@@ -69,8 +69,9 @@
 		PortSuspendStatusChange		= 1 << 18,
 		PortOverCurrentIndicatorChange	= 1 << 19,
 		PortResetStatusChange		= 1 << 20
-	} HcRhPortStatusRead;
+	};
-	enum {
+
+	enum HcRhPortStatusSet {
 		ClearPortEnable			= 1 << 0,
 		SetPortEnable			= 1 << 1,
 		SetPortSuspend			= 1 << 2,
@@ -78,29 +79,30 @@
 		SetPortReset			= 1 << 4,
 		SetPortPower			= 1 << 8,
 		ClearPortPower			= 1 << 9,
-	} HcRhPortStatusSet;
+	};
 
-	enum {
+	enum HcRhStatusReg {
 		LocalPowerStatus = 1 << 0,
 		OverCurrentIndicator = 1 << 1,
 		DeviceRemoteWakeupEnable = 1 << 15,
 		LocalPowerStatusChange = 1 << 16,
 		OverCurrentIndicatorChange = 1 << 17,
 		ClearRemoteWakeupEnable = 1 << 31
-	} HcRhStatusReg;
+	};
 
-	enum {
+	enum HcFmIntervalOffset {
 		FrameInterval = 1 << 0,
 		FSLargestDataPacket = 1 << 16,
 		FrameIntervalToggle = 1 << 31
-	} HcFmIntervalOffset;
+	};
-	enum {
+
+	enum HcFmIntervalMask {
 		FrameIntervalMask = MASK(0, 14),
 		FSLargestDataPacketMask = MASK(16, 15),
 		FrameIntervalToggleMask = MASK(31, 1)
-	} HcFmIntervalMask;
+	};
 
-	enum {
+	enum HcControlReg {
 		ControlBulkServiceRatio = 1 << 0,
 		PeriodicListEnable = 1 << 2,
 		IsochronousEnable = 1 << 3,
@@ -110,12 +112,12 @@
 		InterruptRouting = 1 << 8,
 		RemoteWakeupConnected = 1 << 9,
 		RemoteWakeupEnable = 1 << 10
-	} HcControlReg;
+	};
 
-	enum {
+	enum HcControlMask {
 		ControlBulkServiceRatioMask = MASK(0, 2),
 		HostControllerFunctionalStateMask = MASK(6, 2)
-	} HcControlMask;
+	};
 
 	enum {
 		USBReset = 0*HostControllerFunctionalState,
@@ -124,24 +126,24 @@
 		USBSuspend = 3*HostControllerFunctionalState
 	};
 
-	enum {
+	enum HcCommandStatusReg {
 		HostControllerReset = 1 << 0,
 		ControlListFilled = 1 << 1,
 		BulkListFilled = 1 << 2,
 		OwnershipChangeRequest = 1 << 3,
 		SchedulingOverrunCount = 1 << 16
-	} HcCommandStatusReg;
+	};
 
-	enum {
+	enum HcCommandStatusMask {
 		SchedulingOverrunCountMask = MASK(16, 2)
-	} HcCommandStatusMask;
+	};
 
-	enum {
+	enum HcFmRemainingReg {
 		FrameRemaining = 1 << 0,
 		FrameRemainingToggle = 1 << 31
-	} HcFmRemainingReg;
+	};
 
-	enum {
+	enum HcInterruptStatusReg {
 		SchedulingOverrung = 1 << 0,
 		WritebackDoneHead = 1 << 1,
 		StartofFrame = 1 << 2,
@@ -150,7 +152,7 @@
 		FrameNumberOverflow = 1 << 5,
 		RootHubStatusChange = 1 << 6,
 		OwnershipChange = 1 << 30
-	} HcInterruptStatusReg;
+	};
 
      typedef struct {
 	// Control and Status Partition

payloads/libpayload/include/cbfs_core.h

@@ -49,7 +49,6 @@
 #include <stddef.h>
 #include <stdint.h>
 #include <stdlib.h>
-#include <compiler.h>
 
 /** These are standard values for the known compression
     alogrithms that coreboot knows about for stages and

payloads/libpayload/include/libpayload.h

@@ -44,7 +44,6 @@
 
 #include <stdbool.h>
 #include <libpayload-config.h>
-#include <compiler.h>
 #include <cbgfx.h>
 #include <ctype.h>
 #include <die.h>

src/acpi/acpi.c

@@ -468,7 +468,7 @@ void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id)
 	{
 		struct device *dev;
 		for (dev = all_devices; dev; dev = dev->next)
-			if (dev->ops && dev->ops->acpi_fill_ssdt)
+			if (dev->enabled && dev->ops && dev->ops->acpi_fill_ssdt)
 				dev->ops->acpi_fill_ssdt(dev);
 		current = (unsigned long) acpigen_get_current();
 	}

src/acpi/acpigen.c

@@ -10,6 +10,8 @@
 
 #define ACPIGEN_MAXLEN 0xfffff
 
+#define CPPC_PACKAGE_NAME "GCPC"
+
 #include <lib.h>
 #include <string.h>
 #include <acpi/acpigen.h>
@@ -340,7 +342,7 @@ void acpigen_write_scope(const char *name)
 
 void acpigen_get_package_op_element(uint8_t package_op, unsigned int element, uint8_t dest_op)
 {
-	/* <dest_op> = DeRefOf (<package_op>[<element]) */
+	/* <dest_op> = DeRefOf (<package_op>[<element>]) */
 	acpigen_write_store();
 	acpigen_emit_byte(DEREF_OP);
 	acpigen_emit_byte(INDEX_OP);
@@ -350,6 +352,52 @@ void acpigen_get_package_op_element(uint8_t package_op, unsigned int element, ui
 	acpigen_emit_byte(dest_op);
 }
 
+void acpigen_set_package_op_element_int(uint8_t package_op, unsigned int element, uint64_t src)
+{
+	/* DeRefOf (<package>[<element>]) = <src> */
+	acpigen_write_store();
+	acpigen_write_integer(src);
+	acpigen_emit_byte(DEREF_OP);
+	acpigen_emit_byte(INDEX_OP);
+	acpigen_emit_byte(package_op);
+	acpigen_write_integer(element);
+	acpigen_emit_byte(ZERO_OP); /* Ignore Index() Destination */
+}
+
+void acpigen_get_package_element(const char *package, unsigned int element, uint8_t dest_op)
+{
+	/* <dest_op> = <package>[<element>] */
+	acpigen_write_store();
+	acpigen_emit_byte(INDEX_OP);
+	acpigen_emit_namestring(package);
+	acpigen_write_integer(element);
+	acpigen_emit_byte(ZERO_OP); /* Ignore Index() Destination */
+	acpigen_emit_byte(dest_op);
+}
+
+void acpigen_set_package_element_int(const char *package, unsigned int element, uint64_t src)
+{
+	/* <package>[<element>] = <src> */
+	acpigen_write_store();
+	acpigen_write_integer(src);
+	acpigen_emit_byte(INDEX_OP);
+	acpigen_emit_namestring(package);
+	acpigen_write_integer(element);
+	acpigen_emit_byte(ZERO_OP); /* Ignore Index() Destination */
+}
+
+void acpigen_set_package_element_namestr(const char *package, unsigned int element,
+					 const char *src)
+{
+	/* <package>[<element>] = <src> */
+	acpigen_write_store();
+	acpigen_emit_namestring(src);
+	acpigen_emit_byte(INDEX_OP);
+	acpigen_emit_namestring(package);
+	acpigen_write_integer(element);
+	acpigen_emit_byte(ZERO_OP); /* Ignore Index() Destination */
+}
+
 void acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len)
 {
 /*
@@ -1318,6 +1366,14 @@ void acpigen_write_debug_op(uint8_t op)
 	acpigen_emit_ext_op(DEBUG_OP);
 }
 
+/* Store (str, DEBUG) */
+void acpigen_write_debug_namestr(const char *str)
+{
+	acpigen_write_store();
+	acpigen_emit_namestring(str);
+	acpigen_emit_ext_op(DEBUG_OP);
+}
+
 void acpigen_write_if(void)
 {
 	acpigen_emit_byte(IF_OP);
@@ -1453,6 +1509,12 @@ void acpigen_write_return_integer(uint64_t arg)
 	acpigen_write_integer(arg);
 }
 
+void acpigen_write_return_namestr(const char *arg)
+{
+	acpigen_emit_byte(RETURN_OP);
+	acpigen_emit_namestring(arg);
+}
+
 void acpigen_write_return_string(const char *arg)
 {
 	acpigen_emit_byte(RETURN_OP);
@@ -1578,8 +1640,6 @@ void acpigen_write_dsm_uuid_arr(struct dsm_uuid *ids, size_t count)
 	acpigen_pop_len();	/* Method _DSM */
 }
 
-#define CPPC_PACKAGE_NAME "\\GCPC"
-
 void acpigen_write_CPPC_package(const struct cppc_config *config)
 {
 	u32 i;
@@ -1621,9 +1681,12 @@ void acpigen_write_CPPC_package(const struct cppc_config *config)
 
 void acpigen_write_CPPC_method(void)
 {
+	char pscope[16];
+	snprintf(pscope, sizeof(pscope), CONFIG_ACPI_CPU_STRING "." CPPC_PACKAGE_NAME, 0);
+
 	acpigen_write_method("_CPC", 0);
 	acpigen_emit_byte(RETURN_OP);
-	acpigen_emit_namestring(CPPC_PACKAGE_NAME);
+	acpigen_emit_namestring(pscope);
 	acpigen_pop_len();
 }
 
@@ -2095,3 +2158,35 @@ void acpigen_write_xpss_object(const struct acpi_xpss_sw_pstate *pstate_values,
 
 	acpigen_pop_len();
 }
+
+/* Delay up to wait_ms until provided namestr matches expected value. */
+void acpigen_write_delay_until_namestr_int(uint32_t wait_ms, const char *name, uint64_t value)
+{
+	uint32_t wait_ms_segment = 1;
+	uint32_t segments = wait_ms;
+
+	/* Sleep in 16ms segments if delay is more than 32ms. */
+	if (wait_ms > 32) {
+		wait_ms_segment = 16;
+		segments = wait_ms / 16;
+	}
+
+	acpigen_write_store_int_to_op(segments, LOCAL7_OP);
+	acpigen_emit_byte(WHILE_OP);
+	acpigen_write_len_f();
+	acpigen_emit_byte(LGREATER_OP);
+	acpigen_emit_byte(LOCAL7_OP);
+	acpigen_emit_byte(ZERO_OP);
+
+	/* If name is not provided then just delay in a loop. */
+	if (name) {
+		acpigen_write_if_lequal_namestr_int(name, value);
+		acpigen_emit_byte(BREAK_OP);
+		acpigen_pop_len(); /* If */
+	}
+
+	acpigen_write_sleep(wait_ms_segment);
+	acpigen_emit_byte(DECREMENT_OP);
+	acpigen_emit_byte(LOCAL7_OP);
+	acpigen_pop_len(); /* While */
+}

src/console/Kconfig

@@ -58,6 +58,14 @@ if CONSOLE_SERIAL
 	comment "device-specific UART"
 	depends on HAVE_UART_SPECIAL
 
+config OVERRIDE_UART_FOR_CONSOLE
+	bool
+	help
+	  Set to "y" when the platform overrides the index of uart port by providing
+	  a get_uart_for_console routine.
+
+if !OVERRIDE_UART_FOR_CONSOLE
+
 config UART_FOR_CONSOLE
 	int
 	prompt "Index for UART port to use for console" if !FIXED_UART_FOR_CONSOLE
@@ -87,6 +95,8 @@ depends on DRIVERS_UART_8250IO && UART_FOR_CONSOLE = 2
 comment "Serial port base address = 0x2e8"
 depends on DRIVERS_UART_8250IO && UART_FOR_CONSOLE = 3
 
+endif
+
 config UART_OVERRIDE_BAUDRATE
 	bool
 	help

src/cpu/intel/fit/Kconfig

@@ -5,7 +5,7 @@ config CPU_INTEL_FIRMWARE_INTERFACE_TABLE
 
 config CPU_INTEL_NUM_FIT_ENTRIES
 	int
-	default 16 if INTEL_TXT
+	default 16 if INTEL_TXT || INTEL_CBNT_SUPPORT
 	default 4
 	depends on CPU_INTEL_FIRMWARE_INTERFACE_TABLE
 	help

src/cpu/intel/haswell/haswell.h

@@ -76,6 +76,26 @@
 #define MSR_CONFIG_TDP_CONTROL		0x64b
 #define MSR_TURBO_ACTIVATION_RATIO	0x64c
 
+#define SMM_MCA_CAP_MSR			0x17d
+#define   SMM_CPU_SVRSTR_BIT		57
+#define   SMM_CPU_SVRSTR_MASK		(1 << (SMM_CPU_SVRSTR_BIT - 32))
+
+#define MSR_PRMRR_PHYS_BASE		0x1f4
+#define MSR_PRMRR_PHYS_MASK		0x1f5
+#define MSR_UNCORE_PRMRR_PHYS_BASE	0x2f4
+#define MSR_UNCORE_PRMRR_PHYS_MASK	0x2f5
+
+#define SMM_FEATURE_CONTROL_MSR		0x4e0
+#define   SMM_CPU_SAVE_EN		(1 << 1)
+
+/* SMM save state MSRs */
+#define SMBASE_MSR			0xc20
+#define IEDBASE_MSR			0xc22
+
+/* MTRR_CAP_MSR bit definitions */
+#define SMRR_SUPPORTED			(1 << 11)
+#define PRMRR_SUPPORTED			(1 << 12)
+
 /* P-state configuration */
 #define PSS_MAX_ENTRIES			8
 #define PSS_RATIO_STEP			2

src/cpu/intel/haswell/smmrelocate.c

@@ -17,22 +17,6 @@
 #include <smp/node.h>
 #include "haswell.h"
 
-#define MSR_PRMRR_PHYS_BASE 0x1f4
-#define MSR_PRMRR_PHYS_MASK 0x1f5
-#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4
-#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5
-#define SMM_MCA_CAP_MSR 0x17d
-#define   SMM_CPU_SVRSTR_BIT 57
-#define   SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32))
-#define SMM_FEATURE_CONTROL_MSR 0x4e0
-#define   SMM_CPU_SAVE_EN (1 << 1)
-/* SMM save state MSRs */
-#define SMBASE_MSR 0xc20
-#define IEDBASE_MSR 0xc22
-
-#define SMRR_SUPPORTED (1 << 11)
-#define PRMRR_SUPPORTED (1 << 12)
-
 static void update_save_state(int cpu, uintptr_t curr_smbase,
 				uintptr_t staggered_smbase,
 				struct smm_relocation_params *relo_params)

src/cpu/intel/model_206ax/model_206ax_init.c

@@ -18,6 +18,7 @@
 #include "chip.h"
 #include <cpu/intel/smm_reloc.h>
 #include <cpu/intel/common/common.h>
+#include <smbios.h>
 
 /*
  * List of supported C-states in this processor
@@ -360,6 +361,25 @@ static void set_max_ratio(void)
 	       ((perf_ctl.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK);
 }
 
+unsigned int smbios_cpu_get_max_speed_mhz(void)
+{
+	msr_t msr;
+	msr = rdmsr(MSR_TURBO_RATIO_LIMIT);
+	return (msr.lo & 0xff) * SANDYBRIDGE_BCLK;
+}
+
+unsigned int smbios_cpu_get_current_speed_mhz(void)
+{
+	msr_t msr;
+	msr = rdmsr(MSR_PLATFORM_INFO);
+	return ((msr.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK;
+}
+
+unsigned int smbios_processor_external_clock(void)
+{
+	return SANDYBRIDGE_BCLK;
+}
+
 static void configure_mca(void)
 {
 	msr_t msr;

src/cpu/intel/smm/gen1/smmrelocate.c

@@ -59,8 +59,8 @@ static void write_smrr_alt(struct smm_relocation_params *relo_params)
 	printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
 	       relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
 
-	wrmsr(MSR_SMRR_PHYS_BASE, relo_params->smrr_base);
+	wrmsr(CORE2_SMRR_PHYS_BASE, relo_params->smrr_base);
-	wrmsr(MSR_SMRR_PHYS_MASK, relo_params->smrr_mask);
+	wrmsr(CORE2_SMRR_PHYS_MASK, relo_params->smrr_mask);
 }
 
 static void fill_in_relocation_params(struct smm_relocation_params *params)

src/cpu/x86/smm/Makefile.inc

@@ -32,6 +32,8 @@ ifeq ($(CONFIG_HAVE_SMI_HANDLER),y)
 ramstage-srcs += $(obj)/cpu/x86/smm/smm.manual
 endif
 
+smm-y += save_state.c
+
 ifeq ($(CONFIG_SMM_TSEG),y)
 
 ramstage-y += tseg_region.c

src/cpu/x86/smm/save_state.c

@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cpu/x86/smm.h>
+#include <cpu/x86/save_state.h>
+
+/* These are weakly linked such that platforms can link only the save state
+   ops they actually require. */
+const struct smm_save_state_ops *legacy_ops __weak = NULL;
+const struct smm_save_state_ops *em64t100_ops __weak = NULL;
+const struct smm_save_state_ops *em64t101_ops __weak = NULL;
+const struct smm_save_state_ops *amd64_ops __weak = NULL;
+
+static const struct smm_save_state_ops *save_state;
+
+/* Returns -1 on failure, 0 on success */
+static int init_save_state(void)
+{
+	const uint32_t revision = smm_revision();
+	int i;
+	static bool initialized = false;
+	const struct smm_save_state_ops *save_state_ops[] = {
+		legacy_ops,
+		em64t100_ops,
+		em64t101_ops,
+		amd64_ops,
+	};
+
+	if (initialized)
+		return 0;
+
+	for (i = 0; i < ARRAY_SIZE(save_state_ops); i++) {
+		const struct smm_save_state_ops *ops = save_state_ops[i];
+		const uint32_t *rev;
+
+		if (ops == NULL)
+			continue;
+
+		for (rev = ops->revision_table; *rev != SMM_REV_INVALID; rev++)
+			if (*rev == revision) {
+				save_state = ops;
+				initialized = true;
+				return 0;
+			}
+	}
+
+	return -1;
+}
+
+int get_apmc_node(u8 cmd)
+{
+	if (init_save_state())
+		return -1;
+
+	return save_state->apmc_node(cmd);
+}
+
+int get_save_state_reg(const enum cpu_reg reg, const int node, void *out, const uint8_t length)
+{
+	if (init_save_state())
+		return -1;
+
+	if (node > CONFIG_MAX_CPUS)
+		return -1;
+
+	return save_state->get_reg(reg, node, out, length);
+}
+
+int set_save_state_reg(const enum cpu_reg reg, const int node, void *in, const uint8_t length)
+{
+	if (init_save_state())
+		return -1;
+
+	if (node > CONFIG_MAX_CPUS)
+		return -1;
+
+	return save_state->set_reg(reg, node, in, length);
+}

src/cpu/x86/smm/smihandler.c

@@ -14,23 +14,6 @@
 #include <spi-generic.h>
 #endif
 
-typedef enum {
-	AMD64,
-	EM64T100,
-	EM64T101,
-	LEGACY
-} save_state_type_t;
-
-typedef struct {
-	save_state_type_t type;
-	union {
-	amd64_smm_state_save_area_t *amd64_state_save;
-	em64t100_smm_state_save_area_t *em64t100_state_save;
-	em64t101_smm_state_save_area_t *em64t101_state_save;
-	legacy_smm_state_save_area_t *legacy_state_save;
-	};
-} smm_state_save_area_t;
-
 static int do_driver_init = 1;
 
 typedef enum { SMI_LOCKED, SMI_UNLOCKED } smi_semaphore;
@@ -162,9 +145,6 @@ bool smm_region_overlaps_handler(const struct region *r)
 void smi_handler(void)
 {
 	unsigned int node;
-	const uint32_t smm_rev = smm_revision();
-	smm_state_save_area_t state_save;
-	u32 smm_base = SMM_BASE; /* ASEG */
 
 	/* Are we ok to execute the handler? */
 	if (!smi_obtain_lock()) {
@@ -190,36 +170,10 @@ void smi_handler(void)
 
 	printk(BIOS_SPEW, "\nSMI# #%d\n", node);
 
-	switch (smm_rev) {
+	/* Use smm_get_save_state() to see if the smm revision is supported */
-	case 0x00030002:
+	if (smm_get_save_state(node) == NULL) {
-	case 0x00030007:
+		printk(BIOS_WARNING, "smm_revision: 0x%08x\n", smm_revision());
-		state_save.type = LEGACY;
+		printk(BIOS_WARNING, "SMI# not supported on your CPU\n");
-		state_save.legacy_state_save =
-			smm_save_state(smm_base,
-				       SMM_LEGACY_ARCH_OFFSET, node);
-		break;
-	case 0x00030100:
-		state_save.type = EM64T100;
-		state_save.em64t100_state_save =
-			smm_save_state(smm_base,
-				       SMM_EM64T100_ARCH_OFFSET, node);
-		break;
-	case 0x00030101: /* SandyBridge, IvyBridge, and Haswell */
-		state_save.type = EM64T101;
-		state_save.em64t101_state_save =
-			smm_save_state(smm_base,
-				       SMM_EM64T101_ARCH_OFFSET, node);
-		break;
-	case 0x00020064:
-	case 0x00030064:
-		state_save.type = AMD64;
-		state_save.amd64_state_save =
-			smm_save_state(smm_base,
-				       SMM_AMD64_ARCH_OFFSET, node);
-		break;
-	default:
-		printk(BIOS_DEBUG, "smm_revision: 0x%08x\n", smm_rev);
-		printk(BIOS_DEBUG, "SMI# not supported on your CPU\n");
 		/* Don't release lock, so no further SMI will happen,
 		 * if we don't handle it anyways.
 		 */

src/cpu/x86/smm/smm.ld

@@ -2,6 +2,9 @@
 
 /* Maximum number of CPUs/cores */
 CPUS = 4;
+
+_ = ASSERT(CPUS >= CONFIG_MAX_CPUS, "The ASEG SMM code only supports up to 4 CPUS");
+
 ENTRY(smm_handler_start);
 
 SECTIONS

src/device/pci_device.c

@@ -1648,21 +1648,3 @@ void pci_dev_disable_bus_master(const struct device *dev)
 	pci_update_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MASTER, 0x0);
 }
 #endif
-
-bool pci_dev_is_wake_source(const struct device *dev)
-{
-	unsigned int pm_cap;
-	uint16_t pmcs;
-
-	if (dev->path.type != DEVICE_PATH_PCI)
-		return false;
-
-	pm_cap = pci_find_capability(dev, PCI_CAP_ID_PM);
-	if (!pm_cap)
-		return false;
-
-	pmcs = pci_read_config16(dev, pm_cap + PCI_PM_CTRL);
-
-	/* PCI Device is a wake source if PME_ENABLE and PME_STATUS are set in PMCS register. */
-	return (pmcs & PCI_PM_CTRL_PME_ENABLE) && (pmcs & PCI_PM_CTRL_PME_STATUS);
-}

src/device/pci_ops.c

@@ -78,3 +78,21 @@ void __noreturn pcidev_die(void)
 {
 	die("PCI: dev is NULL!\n");
 }
+
+bool pci_dev_is_wake_source(const struct device *dev)
+{
+	unsigned int pm_cap;
+	uint16_t pmcs;
+
+	if (dev->path.type != DEVICE_PATH_PCI)
+		return false;
+
+	pm_cap = pci_find_capability(dev, PCI_CAP_ID_PM);
+	if (!pm_cap)
+		return false;
+
+	pmcs = pci_s_read_config16(PCI_BDF(dev), pm_cap + PCI_PM_CTRL);
+
+	/* PCI Device is a wake source if PME_ENABLE and PME_STATUS are set in PMCS register. */
+	return (pmcs & PCI_PM_CTRL_PME_ENABLE) && (pmcs & PCI_PM_CTRL_PME_STATUS);
+}

src/drivers/generic/adau7002/adau7002.c

@@ -17,7 +17,7 @@ static void adau7002_fill_ssdt(const struct device *dev)
 	struct drivers_generic_adau7002_config *config;
 	struct acpi_dp *dp;
 
-	if (!dev || !dev->enabled)
+	if (!dev)
 		return;
 
 	const char *scope = acpi_device_scope(dev);

src/drivers/generic/gpio_keys/gpio_keys.c

@@ -57,7 +57,7 @@ static void gpio_keys_fill_ssdt_generator(const struct device *dev)
 	const char *drv_string = config->is_polled ? "gpio-keys-polled"
 				: "gpio-keys";
 
-	if (!dev->enabled || !scope || !path || !config->gpio.pin_count)
+	if (!scope || !path || !config->gpio.pin_count)
 		return;
 
 	/* Device */

src/drivers/generic/max98357a/max98357a.c

@@ -18,7 +18,7 @@ static void max98357a_fill_ssdt(const struct device *dev)
 	const char *path;
 	struct acpi_dp *dp;
 
-	if (!dev->enabled || !config)
+	if (!config)
 		return;
 
 	const char *scope = acpi_device_scope(dev);

src/drivers/gfx/generic/generic.c

@@ -106,7 +106,7 @@ static void gfx_fill_ssdt_generator(const struct device *dev)
 
 	const char *scope = acpi_device_scope(dev);
 
-	if (!scope || !dev->enabled)
+	if (!scope)
 		return;
 
 	acpigen_write_scope(scope);

src/drivers/i2c/da7219/da7219.c

@@ -27,7 +27,7 @@ static void da7219_fill_ssdt(const struct device *dev)
 	};
 	struct acpi_dp *dsd, *aad;
 
-	if (!dev->enabled || !scope)
+	if (!scope)
 		return;
 
 	/* Device */

src/drivers/i2c/designware/dw_i2c.c

@@ -824,9 +824,6 @@ void dw_i2c_acpi_fill_ssdt(const struct device *dev)
 	const char *path;
 	unsigned int speed;
 
-	if (!dev->enabled)
-		return;
-
 	bus = dw_i2c_soc_dev_to_bus(dev);
 
 	if (bus < 0)

src/drivers/i2c/generic/generic.c

@@ -57,7 +57,7 @@ void i2c_generic_fill_ssdt(const struct device *dev,
 	int reset_gpio_index = -1, enable_gpio_index = -1, irq_gpio_index = -1;
 	const char *path = acpi_device_path(dev);
 
-	if (!dev->enabled || !scope)
+	if (!scope)
 		return;
 
 	if (!config->hid) {

src/drivers/i2c/gpiomux/bus/bus.c

@@ -22,7 +22,7 @@ static void i2c_gpiomux_bus_fill_ssdt(const struct device *dev)
 	const char *scope = acpi_device_scope(dev);
 	const char *path = acpi_device_path(dev);
 
-	if (!dev || !dev->enabled || !scope || !path)
+	if (!dev || !scope || !path)
 		return;
 
 	/* Device */

src/drivers/i2c/gpiomux/mux/mux.c

@@ -27,7 +27,7 @@ static void i2c_gpiomux_mux_fill_ssdt(const struct device *dev)
 	struct acpi_gpio_res_params param[MAX_NUM_MUX_GPIOS];
 	int i;
 
-	if (!dev->enabled || !scope || !path)
+	if (!scope || !path)
 		return;
 
 	/* Device */

src/drivers/i2c/max98373/max98373.c

@@ -24,7 +24,7 @@ static void max98373_fill_ssdt(const struct device *dev)
 	};
 	struct acpi_dp *dp;
 
-	if (!dev->enabled || !scope) {
+	if (!scope) {
 		printk(BIOS_ERR, "%s: dev not enabled\n", __func__);
 		return;
 	}

src/drivers/i2c/max98390/max98390.c

@@ -28,7 +28,7 @@ static void max98390_fill_ssdt(const struct device *dev)
 	struct acpi_dp *dp;
 	uint64_t r0_value, temp_value;
 
-	if (!dev->enabled || !scope)
+	if (!scope)
 		return;
 
 	/* Device */

src/drivers/i2c/max98927/max98927.c

@@ -24,7 +24,7 @@ static void max98927_fill_ssdt(const struct device *dev)
 	};
 	struct acpi_dp *dp;
 
-	if (!dev->enabled || !scope)
+	if (!scope)
 		return;
 
 	/* Device */

src/drivers/i2c/nau8825/nau8825.c

@@ -30,7 +30,7 @@ static void nau8825_fill_ssdt(const struct device *dev)
 	};
 	struct acpi_dp *dp = NULL;
 
-	if (!dev->enabled || !scope)
+	if (!scope)
 		return;
 	if (config->sar_threshold_num > NAU8825_MAX_BUTTONS)
 		return;

src/drivers/i2c/rt1011/rt1011.c

@@ -28,7 +28,7 @@ static void rt1011_fill_ssdt(const struct device *dev)
 	struct acpi_dp *dp;
 	uint64_t r0_value, temp_value;
 
-	if (!dev->enabled || !scope)
+	if (!scope)
 		return;
 
 	/* Device */

src/drivers/i2c/rt5663/rt5663.c

@@ -27,7 +27,7 @@ static void rt5663_fill_ssdt(const struct device *dev)
 	};
 	struct acpi_dp *dp;
 
-	if (!dev->enabled || !scope)
+	if (!scope)
 		return;
 
 	/* Device */

src/drivers/i2c/rx6110sa/chip.h

@@ -3,6 +3,7 @@
 #include "rx6110sa.h"
 
 struct drivers_i2c_rx6110sa_config {
+	unsigned int bus_speed;		/* Bus clock in Hz (default 400 kHz)*/
 	/* The day (of the week) is indicated by 7 bits, bit 0 to bit 6. */
 	unsigned char user_weekday;	/* User day of the week to set */
 	unsigned char user_day;		/* User day to set */

src/drivers/i2c/rx6110sa/rx6110sa.c

@@ -1,7 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <device/i2c_bus.h>
+#include <acpi/acpi_device.h>
+#include <acpi/acpigen.h>
 #include <device/device.h>
+#include <device/i2c.h>
+#include <device/i2c_bus.h>
 #include <version.h>
 #include <console/console.h>
 #include <bcd.h>
@@ -163,11 +166,71 @@ static void rx6110sa_init(struct device *dev)
 	rx6110sa_write(dev, CTRL_REG, reg);
 }
 
+#if CONFIG(HAVE_ACPI_TABLES)
+static void rx6110sa_fill_ssdt(const struct device *dev)
+{
+	struct drivers_i2c_rx6110sa_config *config = dev->chip_info;
+	const char *scope = acpi_device_scope(dev);
+	enum i2c_speed bus_speed;
+
+	if (!scope)
+		return;
+
+	switch (config->bus_speed) {
+	case I2C_SPEED_STANDARD:
+	case I2C_SPEED_FAST:
+		bus_speed = config->bus_speed;
+		break;
+	default:
+		printk(BIOS_INFO, "%s: Bus speed unsupported, fall back to %d kHz!\n",
+			dev_path(dev), I2C_SPEED_STANDARD / 1000);
+		bus_speed = I2C_SPEED_STANDARD;
+		break;
+	}
+
+	struct acpi_i2c i2c = {
+		.address = dev->path.i2c.device,
+		.mode_10bit = dev->path.i2c.mode_10bit,
+		.speed = bus_speed,
+		.resource = scope,
+	};
+
+	/* Device */
+	acpigen_write_scope(scope);
+	acpigen_write_device(acpi_device_name(dev));
+	acpigen_write_name_string("_HID", RX6110SA_HID_NAME);
+	acpigen_write_name_string("_DDN", RX6110SA_HID_DESC);
+	acpigen_write_STA(acpi_device_status(dev));
+
+	/* Resources */
+	acpigen_write_name("_CRS");
+	acpigen_write_resourcetemplate_header();
+	acpi_device_write_i2c(&i2c);
+
+	acpigen_write_resourcetemplate_footer();
+
+	acpigen_pop_len(); /* Device */
+	acpigen_pop_len(); /* Scope */
+
+	printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev),
+			dev->chip_ops->name, dev_path(dev));
+}
+
+static const char *rx6110sa_acpi_name(const struct device *dev)
+{
+	return RX6110SA_ACPI_NAME;
+}
+#endif
+
 static struct device_operations rx6110sa_ops = {
 	.read_resources		= noop_read_resources,
 	.set_resources		= noop_set_resources,
 	.init			= rx6110sa_init,
-	.final			= rx6110sa_final
+	.final			= rx6110sa_final,
+#if CONFIG(HAVE_ACPI_TABLES)
+	.acpi_name		= rx6110sa_acpi_name,
+	.acpi_fill_ssdt		= rx6110sa_fill_ssdt,
+#endif
 };
 
 static void rx6110sa_enable(struct device *dev)

src/drivers/i2c/rx6110sa/rx6110sa.h

@@ -3,9 +3,9 @@
 #ifndef _I2C_RX6110SA_H_
 #define _I2C_RX6110SA_H_
 
-/* The address of this RTC is fixed. */
+#define RX6110SA_ACPI_NAME		"ERX6"
-#define RX6110SA_SLAVE_ADR		0x32
+#define RX6110SA_HID_NAME		"RX6110SA"
-#define RX6110SA_I2C_CONTROLLER		0
+#define RX6110SA_HID_DESC		"Real Time Clock"
 
 /* Register layout */
 #define SECOND_REG			0x10

src/drivers/i2c/sx9310/sx9310.c

@@ -28,7 +28,7 @@ static void i2c_sx9310_fill_ssdt(const struct device *dev)
 	};
 	struct acpi_dp *dsd;
 
-	if (!dev->enabled || !scope || !config)
+	if (!scope || !config)
 		return;
 
 	if (config->speed)

src/drivers/i2c/tpm/chip.c

@@ -20,7 +20,7 @@ static void i2c_tpm_fill_ssdt(const struct device *dev)
 		.resource = scope,
 	};
 
-	if (!dev->enabled || !scope)
+	if (!scope)
 		return;
 
 	if (!config->hid) {

src/drivers/intel/fsp1_1/romstage.c

@@ -41,35 +41,29 @@ static void raminit_common(struct romstage_params *params)
 	params->saved_data_size = 0;
 	params->saved_data = NULL;
 	if (!params->disable_saved_data) {
-		if (vboot_recovery_mode_enabled()) {
+		/* Assume boot device is memory mapped. */
-			/* Recovery mode does not use MRC cache */
+		assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
+
+		params->saved_data = NULL;
+		if (CONFIG(CACHE_MRC_SETTINGS))
+			params->saved_data =
+				mrc_cache_current_mmap_leak(MRC_TRAINING_DATA,
+							    params->fsp_version,
+							    &mrc_size);
+		if (params->saved_data) {
+			/* MRC cache found */
+			params->saved_data_size = mrc_size;
+
+		} else if (s3wake) {
+			/* Waking from S3 and no cache. */
 			printk(BIOS_DEBUG,
-			       "Recovery mode: not using MRC cache.\n");
+			       "No MRC cache "
+			       "found in S3 resume path.\n");
+			post_code(POST_RESUME_FAILURE);
+			/* FIXME: A "system" reset is likely enough: */
+			full_reset();
 		} else {
-			/* Assume boot device is memory mapped. */
+			printk(BIOS_DEBUG, "No MRC cache found.\n");
-			assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
-
-			params->saved_data = NULL;
-			if (CONFIG(CACHE_MRC_SETTINGS))
-				params->saved_data =
-					mrc_cache_current_mmap_leak(MRC_TRAINING_DATA,
-								    params->fsp_version,
-								    &mrc_size);
-			if (params->saved_data) {
-				/* MRC cache found */
-				params->saved_data_size = mrc_size;
-
-			} else if (s3wake) {
-				/* Waking from S3 and no cache. */
-				printk(BIOS_DEBUG,
-				       "No MRC cache "
-				       "found in S3 resume path.\n");
-				post_code(POST_RESUME_FAILURE);
-				/* FIXME: A "system" reset is likely enough: */
-				full_reset();
-			} else {
-				printk(BIOS_DEBUG, "No MRC cache found.\n");
-			}
 		}
 	}
 

src/drivers/intel/fsp2_0/memory_init.c

@@ -92,18 +92,6 @@ static void fsp_fill_mrc_cache(FSPM_ARCH_UPD *arch_upd, uint32_t fsp_version)
 	if (!CONFIG(CACHE_MRC_SETTINGS))
 		return;
 
-	/*
-	 * In recovery mode, force retraining:
-	 * 1. Recovery cache is not supported, or
-	 * 2. Memory retrain switch is set.
-	 */
-	if (vboot_recovery_mode_enabled()) {
-		if (!CONFIG(HAS_RECOVERY_MRC_CACHE))
-			return;
-		if (get_recovery_mode_retrain_switch())
-			return;
-	}
-
 	/* Assume boot device is memory mapped. */
 	assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
 

src/drivers/intel/gma/Kconfig

@@ -59,6 +59,10 @@ config INTEL_GMA_SWSMISCI
 config INTEL_GMA_LIBGFXINIT_EDID
 	bool
 
+config VBT_DATA_SIZE_KB
+	int
+	default 8
+
 config GFX_GMA_ANALOG_I2C_HDMI_B
 	bool
 

src/drivers/intel/gma/opregion.c

@@ -19,7 +19,7 @@ const char *mainboard_vbt_filename(void)
 	return "vbt.bin";
 }
 
-static char vbt_data[9 * KiB];
+static char vbt_data[CONFIG_VBT_DATA_SIZE_KB * KiB];
 static size_t vbt_data_sz;
 
 void *locate_vbt(size_t *vbt_size)

src/drivers/intel/ish/ish.c

@@ -13,7 +13,7 @@ static void ish_fill_ssdt_generator(const struct device *dev)
 	struct device *root = dev->bus->dev;
 	struct acpi_dp *dsd;
 
-	if (!dev->enabled || !config || !config->firmware_name)
+	if (!config || !config->firmware_name)
 		return;
 
 	acpigen_write_scope(acpi_device_path(root));

src/drivers/intel/mipi_camera/camera.c

@@ -909,9 +909,6 @@ static void camera_fill_ssdt(const struct device *dev)
 	const char *scope = NULL;
 	const struct device *pdev;
 
-	if (!dev->enabled)
-		return;
-
 	if (config->has_power_resource) {
 		pdev = dev->bus->dev;
 		if (!pdev || !pdev->enabled)

src/drivers/intel/pmc_mux/conn/conn.c

@@ -32,9 +32,6 @@ static void conn_fill_ssdt(const struct device *dev)
 	const char *scope;
 	const char *name;
 
-	if (!dev->enabled)
-		return;
-
 	/* Reference the existing scope and write CONx device */
 	scope = acpi_device_scope(dev);
 	name = acpi_device_name(dev);

src/drivers/intel/soundwire/soundwire.c

@@ -50,7 +50,7 @@ static void intel_soundwire_fill_ssdt(const struct device *dev)
 	struct intel_soundwire_controller *controller;
 	const char *scope = acpi_device_scope(dev);
 
-	if (!dev->enabled || !scope)
+	if (!scope)
 		return;
 
 	if (soc_fill_soundwire_controller(&controller) < 0 || !controller)

src/drivers/intel/usb4/retimer/retimer.c

@@ -101,7 +101,7 @@ static void usb4_retimer_fill_ssdt(const struct device *dev)
 	const struct drivers_intel_usb4_retimer_config *config = dev->chip_info;
 	const char *scope = acpi_device_scope(dev);
 
-	if (!dev->enabled || !scope || !config)
+	if (!scope || !config)
 		return;
 
 	if (!config->power_gpio.pin_count) {

src/drivers/mrc_cache/Kconfig

@@ -17,11 +17,6 @@ config HAS_RECOVERY_MRC_CACHE
 	bool
 	default n
 
-config MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
-	bool
-	depends on VBOOT_STARTS_IN_BOOTBLOCK
-	default n
-
 config MRC_SETTINGS_VARIABLE_DATA
 	bool
 	default n

src/drivers/mrc_cache/mrc_cache.c

@@ -69,7 +69,20 @@ static const struct cache_region normal_training = {
 	.type = MRC_TRAINING_DATA,
 	.elog_slot = ELOG_MEM_CACHE_UPDATE_SLOT_NORMAL,
 	.tpm_hash_index = MRC_RW_HASH_NV_INDEX,
+#if CONFIG(VBOOT_STARTS_IN_ROMSTAGE)
+	/*
+	 * If VBOOT_STARTS_IN_ROMSTAGE is selected, this means that
+	 * memory training happens before vboot (in RO) and the
+	 * mrc_cache data is always safe to use.
+	 */
 	.flags = NORMAL_FLAG | RECOVERY_FLAG,
+#else
+	/*
+	 * If !VBOOT_STARTS_IN_ROMSTAGE, this means that memory training happens after
+	 * vboot (in RW code) and is never safe to use in recovery.
+	 */
+	.flags = NORMAL_FLAG,
+#endif
 };
 
 static const struct cache_region variable_data = {
@@ -78,7 +91,20 @@ static const struct cache_region variable_data = {
 	.type = MRC_VARIABLE_DATA,
 	.elog_slot = ELOG_MEM_CACHE_UPDATE_SLOT_VARIABLE,
 	.tpm_hash_index = 0,
+#if CONFIG(VBOOT_STARTS_IN_ROMSTAGE)
+	/*
+	 * If VBOOT_STARTS_IN_ROMSTAGE is selected, this means that
+	 * memory training happens before vboot (in RO) and the
+	 * mrc_cache data is always safe to use.
+	 */
 	.flags = NORMAL_FLAG | RECOVERY_FLAG,
+#else
+	/*
+	 * If !VBOOT_STARTS_IN_ROMSTAGE, this means that memory training happens after
+	 * vboot (in RW code) and is never safe to use in recovery.
+	 */
+	.flags = NORMAL_FLAG,
+#endif
 };
 
 /* Order matters here for priority in matching. */
@@ -255,6 +281,13 @@ static int mrc_cache_find_current(int type, uint32_t version,
 	const size_t md_size = sizeof(*md);
 	const bool fail_bad_data = true;
 
+	/*
+	 * In recovery mode, force retraining if the memory retrain
+	 * switch is set.
+	 */
+	if (vboot_recovery_mode_enabled() && get_recovery_mode_retrain_switch())
+		return -1;
+
 	cr = lookup_region(&region, type);
 
 	if (cr == NULL)
@@ -566,10 +599,24 @@ static void invalidate_normal_cache(void)
 	const char *name = DEFAULT_MRC_CACHE;
 	const uint32_t invalid = ~MRC_DATA_SIGNATURE;
 
-	/* Invalidate only on recovery mode with retraining enabled. */
+	/*
+	 * If !HAS_RECOVERY_MRC_CACHE and VBOOT_STARTS_IN_ROMSTAGE is
+	 * selected, this means that memory training occurs before
+	 * verified boot (in RO), so normal mode cache does not need
+	 * to be invalidated.
+	 */
+	if (!CONFIG(HAS_RECOVERY_MRC_CACHE) && CONFIG(VBOOT_STARTS_IN_ROMSTAGE))
+		return;
+
+	/* We only invalidate the normal cache in recovery mode. */
 	if (!vboot_recovery_mode_enabled())
 		return;
-	if (!get_recovery_mode_retrain_switch())
+
+	/*
+	 * For platforms with a recovery mrc_cache, no need to
+	 * invalidate when retrain switch is not set.
+	 */
+	if (CONFIG(HAS_RECOVERY_MRC_CACHE) && !get_recovery_mode_retrain_switch())
 		return;
 
 	if (fmap_locate_area_as_rdev_rw(name, &rdev) < 0) {
@@ -599,7 +646,7 @@ static void update_mrc_cache_from_cbmem(int type)
 	cr = lookup_region(&region, type);
 
 	if (cr == NULL) {
-		printk(BIOS_ERR, "MRC: could not find cache_region type %d\n", type);
+		printk(BIOS_INFO, "MRC: could not find cache_region type %d\n", type);
 		return;
 	}
 
@@ -631,8 +678,7 @@ static void finalize_mrc_cache(void *unused)
 			update_mrc_cache_from_cbmem(MRC_VARIABLE_DATA);
 	}
 
-	if (CONFIG(MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN))
+	invalidate_normal_cache();
-		invalidate_normal_cache();
 
 	protect_mrc_region();
 }
@@ -642,13 +688,6 @@ int mrc_cache_stash_data(int type, uint32_t version, const void *data,
 {
 	const struct cache_region *cr;
 
-	cr = lookup_region_type(type);
-	if (cr == NULL) {
-		printk(BIOS_ERR, "MRC: failed to add to cbmem for type %d.\n",
-			type);
-		return -1;
-	}
-
 	struct mrc_metadata md = {
 		.signature = MRC_DATA_SIGNATURE,
 		.data_size = size,
@@ -664,6 +703,13 @@ int mrc_cache_stash_data(int type, uint32_t version, const void *data,
 		size_t cbmem_size;
 		cbmem_size = sizeof(*cbmem_md) + size;
 
+		cr = lookup_region_type(type);
+		if (cr == NULL) {
+			printk(BIOS_INFO, "MRC: No region type found. Skip adding to cbmem for type %d.\n",
+				type);
+			return 0;
+		}
+
 		cbmem_md = cbmem_add(cr->cbmem_id, cbmem_size);
 
 		if (cbmem_md == NULL) {

src/drivers/soundwire/alc5682/alc5682.c

@@ -128,7 +128,7 @@ static void soundwire_alc5682_fill_ssdt(const struct device *dev)
 	const char *scope = acpi_device_scope(dev);
 	struct acpi_dp *dsd;
 
-	if (!dev->enabled || !scope)
+	if (!scope)
 		return;
 
 	acpigen_write_scope(scope);

src/drivers/soundwire/alc711/alc711.c

@@ -105,7 +105,7 @@ static void soundwire_alc711_fill_ssdt(const struct device *dev)
 	const char *scope = acpi_device_scope(dev);
 	struct acpi_dp *dsd;
 
-	if (!dev->enabled || !scope)
+	if (!scope)
 		return;
 
 	acpigen_write_scope(scope);

src/drivers/soundwire/max98373/max98373.c

@@ -114,7 +114,7 @@ static void soundwire_max98373_fill_ssdt(const struct device *dev)
 	const char *scope = acpi_device_scope(dev);
 	struct acpi_dp *dsd;
 
-	if (!dev->enabled || !scope)
+	if (!scope)
 		return;
 
 	acpigen_write_scope(scope);

src/drivers/spi/acpi/acpi.c

@@ -77,7 +77,7 @@ static void spi_acpi_fill_ssdt_generator(const struct device *dev)
 	int reset_gpio_index = -1;
 	int enable_gpio_index = -1;
 
-	if (!dev->enabled || !scope)
+	if (!scope)
 		return;
 
 	if (spi_acpi_get_bus(dev) == -1) {

src/drivers/uart/acpi/acpi.c

@@ -46,7 +46,7 @@ static void uart_acpi_fill_ssdt(const struct device *dev)
 	int reset_gpio_index = -1;
 	int enable_gpio_index = -1;
 
-	if (!dev->enabled || !scope)
+	if (!scope)
 		return;
 
 	if (!config->hid) {

src/drivers/usb/acpi/chip.h

@@ -44,7 +44,28 @@ struct drivers_usb_acpi_config {
 	bool use_custom_pld;
 	struct acpi_pld custom_pld;
 
+	/* Does the device have a power resource? */
+	bool has_power_resource;
+
+	/* GPIO used to take device out of reset or to put it into reset. */
 	struct acpi_gpio reset_gpio;
+	/* Delay to be inserted after device is taken out of reset. */
+	unsigned int reset_delay_ms;
+	/* Delay to be inserted after device is put into reset. */
+	unsigned int reset_off_delay_ms;
+	/* GPIO used to enable device. */
+	struct acpi_gpio enable_gpio;
+	/* Delay to be inserted after device is enabled. */
+	unsigned int enable_delay_ms;
+	/* Delay to be inserted after device is disabled. */
+	unsigned int enable_off_delay_ms;
+
+	/*
+	 * Define a GPIO that shows the privacy status of the USB device.
+	 * E.g. On a camera: if it is one, it is recording black frames.
+	 * E.g. On a mic: if it is one, it is recording white-noise.
+	 */
+	struct acpi_gpio privacy_gpio;
 };
 
 #endif /* __USB_ACPI_CHIP_H__ */

src/drivers/usb/acpi/usb_acpi.c

@@ -10,13 +10,27 @@
 
 static bool usb_acpi_add_gpios_to_crs(struct drivers_usb_acpi_config *cfg)
 {
-	/*
+	if (cfg->privacy_gpio.pin_count)
-	 * Return false if reset GPIO is not provided.
+		return true;
-	 */
-	if (cfg->reset_gpio.pin_count == 0)
-		return false;
 
-	return true;
+	if (cfg->reset_gpio.pin_count && !cfg->has_power_resource)
+		return true;
+
+	return false;
+}
+
+static int usb_acpi_write_gpio(struct acpi_gpio *gpio, int *curr_index)
+{
+	int ret = -1;
+
+	if (gpio->pin_count == 0)
+		return ret;
+
+	acpi_device_write_gpio(gpio);
+	ret = *curr_index;
+	(*curr_index)++;
+
+	return ret;
 }
 
 static void usb_acpi_fill_ssdt_generator(const struct device *dev)
@@ -24,7 +38,7 @@ static void usb_acpi_fill_ssdt_generator(const struct device *dev)
 	struct drivers_usb_acpi_config *config = dev->chip_info;
 	const char *path = acpi_device_path(dev);
 
-	if (!dev->enabled || !path || !config)
+	if (!path || !config)
 		return;
 
 	/* Don't generate output for hubs, only ports */
@@ -49,18 +63,47 @@ static void usb_acpi_fill_ssdt_generator(const struct device *dev)
 	/* Resources */
 	if (usb_acpi_add_gpios_to_crs(config) == true) {
 		struct acpi_dp *dsd;
+		int idx = 0;
+		int reset_gpio_index = -1;
+		int privacy_gpio_index;
 
 		acpigen_write_name("_CRS");
 		acpigen_write_resourcetemplate_header();
-		acpi_device_write_gpio(&config->reset_gpio);
+		if (!config->has_power_resource) {
+			reset_gpio_index = usb_acpi_write_gpio(
+						&config->reset_gpio, &idx);
+		}
+		privacy_gpio_index = usb_acpi_write_gpio(&config->privacy_gpio,
+							 &idx);
 		acpigen_write_resourcetemplate_footer();
 
 		dsd = acpi_dp_new_table("_DSD");
-		acpi_dp_add_gpio(dsd, "reset-gpio", path, 0, 0,
+		if (reset_gpio_index >= 0)
-				config->reset_gpio.active_low);
+			acpi_dp_add_gpio(dsd, "reset-gpio", path,
+					 reset_gpio_index, 0,
+					 config->reset_gpio.active_low);
+		if (privacy_gpio_index >= 0)
+			acpi_dp_add_gpio(dsd, "privacy-gpio", path,
+					 privacy_gpio_index, 0,
+					 config->privacy_gpio.active_low);
 		acpi_dp_write(dsd);
 	}
 
+	if (config->has_power_resource) {
+		const struct acpi_power_res_params power_res_params = {
+			&config->reset_gpio,
+			config->reset_delay_ms,
+			config->reset_off_delay_ms,
+			&config->enable_gpio,
+			config->enable_delay_ms,
+			config->enable_off_delay_ms,
+			NULL,
+			0,
+			0
+		};
+		acpi_device_add_power_res(&power_res_params);
+	}
+
 	acpigen_pop_len();
 
 	printk(BIOS_INFO, "%s: %s at %s\n", path,

src/drivers/wifi/generic/acpi.c

@@ -44,8 +44,11 @@ static void emit_sar_acpi_structures(const struct device *dev)
 	struct wifi_sar_limits sar_limits;
 	struct wifi_sar_delta_table *wgds;
 
-	/* CBFS SAR and SAR ACPI tables are currently used only by Intel WiFi devices. */
+	/*
-	if (dev->vendor != PCI_VENDOR_ID_INTEL)
+	 * If device type is PCI, ensure that the device has Intel vendor ID. CBFS SAR and SAR
+	 * ACPI tables are currently used only by Intel WiFi devices.
+	 */
+	if (dev->path.type == DEVICE_PATH_PCI && dev->vendor != PCI_VENDOR_ID_INTEL)
 		return;
 
 	/* Retrieve the sar limits data */
@@ -222,9 +225,6 @@ void wifi_pcie_fill_ssdt(const struct device *dev)
 {
 	const char *path;
 
-	if (!is_dev_enabled(dev))
-		return;
-
 	path = acpi_device_path(dev);
 	if (!path)
 		return;
@@ -247,9 +247,6 @@ void wifi_cnvi_fill_ssdt(const struct device *dev)
 {
 	const char *path;
 
-	if (!is_dev_enabled(dev))
-		return;
-
 	path = acpi_device_path(dev->bus->dev);
 	if (!path)
 		return;

src/ec/google/chromeec/audio_codec/audio_codec.c

@@ -15,7 +15,7 @@ static void crosec_audio_codec_fill_ssdt(const struct device *dev)
 	const char *scope = acpi_device_scope(dev);
 	struct ec_google_chromeec_audio_codec_config *cfg = dev->chip_info;
 
-	if (!dev->enabled || !scope || !cfg)
+	if (!scope || !cfg)
 		return;
 
 	acpigen_write_scope(scope);

src/ec/google/chromeec/ec_acpi.c

@@ -140,10 +140,6 @@ static void fill_ssdt_typec_device(const struct device *dev)
 		if (rv)
 			continue;
 
-		if (!config->mux_conn[i])
-			printk(BIOS_ERR, "ERROR: Mux connector info missing for Type-C port "
-			       "#%d\n", i);
-
 		usb2_port = NULL;
 		usb3_port = NULL;
 		usb4_port = NULL;
@@ -227,9 +223,6 @@ void google_chromeec_fill_ssdt_generator(const struct device *dev)
 	struct device_path path;
 	struct device *ec;
 
-	if (!dev->enabled)
-		return;
-
 	/* Set up a minimal EC0 device to pass to the DPTF helpers */
 	path.type = DEVICE_PATH_GENERIC;
 	path.generic.id = 0;

src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c

@@ -17,7 +17,7 @@ static void crosec_i2c_tunnel_fill_ssdt(const struct device *dev)
 	struct ec_google_chromeec_i2c_tunnel_config *cfg = dev->chip_info;
 	struct acpi_dp *dsd;
 
-	if (!dev->enabled || !scope || !cfg)
+	if (!scope || !cfg)
 		return;
 
 	acpigen_write_scope(scope);

src/ec/google/wilco/chip.c

@@ -184,9 +184,6 @@ static void wilco_ec_fill_ssdt_generator(const struct device *dev)
 	void *region_ptr;
 	size_t ucsi_alloc_region_len;
 
-	if (!dev->enabled)
-		return;
-
 	ucsi_alloc_region_len = ucsi_region_len < UCSI_MIN_ALLOC_REGION_LEN ?
 		UCSI_MIN_ALLOC_REGION_LEN : ucsi_region_len;
 	region_ptr = cbmem_add(CBMEM_ID_ACPI_UCSI, ucsi_alloc_region_len);

src/ec/purism/librem/acpi/battery.asl

@@ -65,13 +65,13 @@ Device (BAT)
 	/* Method to enable full battery workaround */
 	Method (BFWE)
 	{
-		Store (One, BFWK)
+		BFWK = 1
 	}
 
 	/* Method to disable full battery workaround */
 	Method (BFWD)
 	{
-		Store (Zero, BFWK)
+		BFWK = 0
 	}
 
 	Method (_STA, 0, Serialized)
@@ -86,22 +86,22 @@ Device (BAT)
 	Method (_BIF, 0, Serialized)
 	{
 		/* Last Full Charge Capacity */
-		Store (BTDF, Index (PBIF, 2))
+		PBIF [2] = BTDF
 
 		/* Design Voltage */
-		Store (BTDV, Index (PBIF, 4))
+		PBIF [4] = BTDV
 
 		/* Design Capacity */
-		Store (BTDA, Local0)
+		Local0 = BTDA
-		Store (Local0, Index (PBIF, 1))
+		PBIF [1] = Local0
 
 		/* Design Capacity of Warning */
-		Divide (Multiply (Local0, DWRN), 100, , Local2)
+		Local2 = (Local0 * DWRN) / 100
-		Store (Local2, Index (PBIF, 5))
+		PBIF [5] = Local2
 
 		/* Design Capacity of Low */
-		Divide (Multiply (Local0, DLOW), 100, , Local2)
+		Local2 = (Local0 * DLOW) / 100
-		Store (Local2, Index (PBIF, 6))
+		PBIF [6] = Local2
 
 		Return (PBIF)
 	}
@@ -109,22 +109,22 @@ Device (BAT)
 	Method (_BIX, 0, Serialized)
 	{
 		/* Last Full Charge Capacity */
-		Store (BTDF, Index (PBIX, 3))
+		PBIX [3] = BTDF
 
 		/* Design Voltage */
-		Store (BTDV, Index (PBIX, 5))
+		PBIX [5] = BTDV
 
 		/* Design Capacity */
-		Store (BTDA, Local0)
+		Local0 = BTDA
-		Store (Local0, Index (PBIX, 2))
+		PBIX [2] = Local0
 
 		/* Design Capacity of Warning */
-		Divide (Multiply (Local0, DWRN), 100, , Local2)
+		Local2 = (Local0 * DWRN) / 100
-		Store (Local2, Index (PBIX, 6))
+		PBIX [6] = Local2
 
 		/* Design Capacity of Low */
-		Divide (Multiply (Local0, DLOW), 100, , Local2)
+		Local2 = (Local0 * DLOW) / 100
-		Store (Local2, Index (PBIX, 7))
+		PBIX [7] = Local2
 
 		Return (PBIX)
 	}
@@ -142,61 +142,60 @@ Device (BAT)
 		/* Check if AC is present */
 		If (ACEX) {
 			/* Read battery status from EC */
-			Store (BSTS, Local0)
+			Local0 = BSTS
 		} Else {
 			/* Always discharging when on battery power */
-			Store (0x01, Local0)
+			Local0 = 0x01
 		}
 
 		/* Check for critical battery level */
 		If (BFCR) {
-			Or (Local0, 0x04, Local0)
+			Local0 |= 0x04
 		}
-		Store (Local0, Index (PBST, 0))
+		PBST [0] = Local0
 
 		/* Notify if battery state has changed since last time */
-		If (LNotEqual (Local0, BSTP)) {
+		If (Local0 != BSTP) {
-			Store (Local0, BSTP)
+			BSTP = Local0
 			Notify (BAT, 0x80)
 		}
 
 		/*
 		 * 1: BATTERY PRESENT RATE
 		 */
-		Store (BTPR, Local1)
+		Local1 = BTPR
-		If (And (Local1, 0x8000)) {
+		If (Local1 & 0x8000) {
-			And (Not (Local1), 0x7FFF, Local0)
+			Local0 = ~Local1 & 0x7FFF
-			Increment (Local0)
+			Local0++
 		} Else {
-			And (Local1, 0x7FFF, Local0)
+			Local0 = Local1 & 0x7FFF
 		}
-		If(LLess(Local0, 0x0352))
+		If(Local0 < 0x0352)
 		{
-			Store(0x0352, Local0)
+			Local0 = 0x0352
 		}
-		Store (Local0, Index (PBST, 1))
+		PBST [1] = Local0
 
 		/*
 		 * 2: BATTERY REMAINING CAPACITY
 		 */
-		Store (BTRA, Local0)
+		Local0 = BTRA
-		If (LAnd (BFWK, LAnd (ACEX, LNot (BSTS)))) {
+		If (BFWK && ACEX && !BSTS) {
-			Store (BTDF, Local1)
+			Local1 = BTDF
 
 			/* See if within ~6% of full */
-			ShiftRight (Local1, 4, Local2)
+			Local2 = Local1 >> 4
-			If (LAnd (LGreater (Local0, Subtract (Local1, Local2)),
+			If ((Local0 > (Local1 - Local2)) && (Local0 < (Local1 + Local2)))
-			          LLess (Local0, Add (Local1, Local2))))
 			{
-				Store (Local1, Local0)
+				Local0 = Local1
 			}
 		}
-		Store (Local0, Index (PBST, 2))
+		PBST [2] = Local0
 
 		/*
 		 * 3: BATTERY PRESENT VOLTAGE
 		 */
-		Store (BTVO, Index (PBST, 3))
+		PBST [3] = BTVO
 
 		Return (PBST)
 	}

src/ec/purism/librem/acpi/ec.asl

@@ -15,12 +15,12 @@ Device (TPSD)
 
 	Method (FNCX, 1, NotSerialized)
 	{
-		If (LEqual (Arg0, 0x86)) {
+		If (Arg0 == 0x86) {
 			/* Enable topstar-laptop kernel driver handling */
-			Store (One, ^^EC.TPSE)
+			^^EC.TPSE = 1
-		} ElseIf (LEqual (Arg0, 0x87)) {
+		} ElseIf (Arg0 == 0x87) {
 			/* Disable topstar-laptop kernel driver handling */
-			Store (Zero, ^^EC.TPSE)
+			^^EC.TPSE = 0
 		}
 	}
 }
@@ -80,10 +80,10 @@ Device (EC)
 	Method (_REG, 2, NotSerialized)
 	{
 		/* Initialize AC power state */
-		Store (ACEX, \PWRS)
+		\PWRS = ACEX
 
 		/* Initialize LID switch state */
-		Store (LIDS, \LIDS)
+		\LIDS = LIDS
 	}
 
 	/* Notify topstar-laptop kernel driver */
@@ -115,7 +115,7 @@ Device (EC)
 	/* AC Status Changed */
 	Method (_Q20)
 	{
-		Store (ACEX, \PWRS)
+		\PWRS = ACEX
 		Notify (AC, 0x80)
 		Notify (BAT, 0x80)
 		PNOT ()
@@ -124,7 +124,7 @@ Device (EC)
 	/* Lid Event */
 	Method (_Q21)
 	{
-		Store (LIDS, \LIDS)
+		\LIDS = LIDS
 		Notify (LID0, 0x80)
 	}
 
@@ -176,7 +176,7 @@ Device (EC)
 		Notify (\_SB.SLPB, 0x80)
 	}
 
-	/* KEY_F13 (Touchpad Enable/Disable)
+	/* KEY_F13 (Touchpad Enable/Disable) */
 	Method (_Q34)
 	{
 		TPSN (0x87)
@@ -193,7 +193,7 @@ Device (EC)
 	/* KEY_BLUETOOTH */
 	Method (_Q37)
 	{
-		XOr (^BTLE, One, ^BTLE)
+		^BTLE ^= 1
 	}
 
 	/* Turbo Enable/Disable */
@@ -208,13 +208,13 @@ Device (EC)
 		 * when the system is charging.
 		 */
 		If (TURB) {
-			Store (PPCM_TURBO, PPCM)
+			PPCM = PPCM_TURBO
 			PPCN ()
-			Store (One, EDTB)
+			EDTB = 1
 		} Else {
-			Store (PPCM_NOTURBO, PPCM)
+			PPCM = PPCM_NOTURBO
 			PPCN ()
-			Store (Zero, EDTB)
+			EDTB = 0
 		}
 	}
 

src/include/acpi/acpi.h

@@ -99,19 +99,24 @@ typedef struct acpi_gen_regaddr {
 	u32 addrh;		/* Register address, high 32 bits */
 } __packed acpi_addr_t;
 
-#define ACPI_ADDRESS_SPACE_MEMORY	   0	/* System memory */
+#define ACPI_ADDRESS_SPACE_MEMORY		0	/* System memory */
-#define ACPI_ADDRESS_SPACE_IO		   1	/* System I/O */
+#define ACPI_ADDRESS_SPACE_IO			1	/* System I/O */
-#define ACPI_ADDRESS_SPACE_PCI		   2	/* PCI config space */
+#define ACPI_ADDRESS_SPACE_PCI			2	/* PCI config space */
-#define ACPI_ADDRESS_SPACE_EC		   3	/* Embedded controller */
+#define ACPI_ADDRESS_SPACE_EC			3	/* Embedded controller */
-#define ACPI_ADDRESS_SPACE_SMBUS	   4	/* SMBus */
+#define ACPI_ADDRESS_SPACE_SMBUS		4	/* SMBus */
-#define ACPI_ADDRESS_SPACE_PCC		0x0A	/* Platform Comm. Channel */
+#define ACPI_ADDRESS_SPACE_CMOS			5	/* SystemCMOS */
-#define ACPI_ADDRESS_SPACE_FIXED	0x7f	/* Functional fixed hardware */
+#define ACPI_ADDRESS_SPACE_PCI_BAR_TARGET	6	/* PciBarTarget */
-#define  ACPI_FFIXEDHW_VENDOR_INTEL	   1	/* Intel */
+#define ACPI_ADDRESS_SPACE_IPMI			7	/* IPMI */
-#define  ACPI_FFIXEDHW_CLASS_HLT	   0	/* C1 Halt */
+#define ACPI_ADDRESS_SPACE_GENERAL_PURPOSE_IO	8	/* GeneralPurposeIO */
-#define  ACPI_FFIXEDHW_CLASS_IO_HLT	   1	/* C1 I/O then Halt */
+#define ACPI_ADDRESS_SPACE_GENERIC_SERIAL_BUS	9	/* GenericSerialBus  */
-#define  ACPI_FFIXEDHW_CLASS_MWAIT	   2	/* MWAIT Native C-state */
+#define ACPI_ADDRESS_SPACE_PCC			0x0A	/* Platform Comm. Channel */
-#define  ACPI_FFIXEDHW_FLAG_HW_COORD	   1	/* Hardware Coordination bit */
+#define ACPI_ADDRESS_SPACE_FIXED		0x7f	/* Functional fixed hardware */
-#define  ACPI_FFIXEDHW_FLAG_BM_STS	   2	/* BM_STS avoidance bit */
+#define  ACPI_FFIXEDHW_VENDOR_INTEL		1	/* Intel */
+#define  ACPI_FFIXEDHW_CLASS_HLT		0	/* C1 Halt */
+#define  ACPI_FFIXEDHW_CLASS_IO_HLT		1	/* C1 I/O then Halt */
+#define  ACPI_FFIXEDHW_CLASS_MWAIT		2	/* MWAIT Native C-state */
+#define  ACPI_FFIXEDHW_FLAG_HW_COORD		1	/* Hardware Coordination bit */
+#define  ACPI_FFIXEDHW_FLAG_BM_STS		2	/* BM_STS avoidance bit */
 /* 0x80-0xbf: Reserved */
 /* 0xc0-0xff: OEM defined */
 

src/include/acpi/acpigen.h

@@ -286,6 +286,7 @@ struct cppc_config {
 };
 
 void acpigen_write_return_integer(uint64_t arg);
+void acpigen_write_return_namestr(const char *arg);
 void acpigen_write_return_string(const char *arg);
 void acpigen_write_len_f(void);
 void acpigen_pop_len(void);
@@ -374,6 +375,7 @@ void acpigen_write_xor(uint8_t arg1, uint8_t arg2, uint8_t res);
 void acpigen_write_and(uint8_t arg1, uint8_t arg2, uint8_t res);
 void acpigen_write_not(uint8_t arg, uint8_t res);
 void acpigen_write_debug_string(const char *str);
+void acpigen_write_debug_namestr(const char *str);
 void acpigen_write_debug_integer(uint64_t val);
 void acpigen_write_debug_op(uint8_t op);
 void acpigen_write_if(void);
@@ -466,7 +468,7 @@ int get_cst_entries(acpi_cstate_t **);
 
 /*
  * Get element from package into specified destination op:
- *   <dest_op> = DeRefOf (<package_op>[<element])
+ *   <dest_op> = DeRefOf (<package_op>[<element>])
  *
  * Example:
  *  acpigen_get_package_op_element(ARG0_OP, 0, LOCAL0_OP)
@@ -474,6 +476,25 @@ int get_cst_entries(acpi_cstate_t **);
  */
 void acpigen_get_package_op_element(uint8_t package_op, unsigned int element, uint8_t dest_op);
 
+/* Set element of package op to specified op:  DeRefOf (<package>[<element>]) = <src> */
+void acpigen_set_package_op_element_int(uint8_t package_op, unsigned int element, uint64_t src);
+
+/* Get element from package to specified op:  <dest_op> = <package>[<element>] */
+void acpigen_get_package_element(const char *package, unsigned int element, uint8_t dest_op);
+
+/* Set element of package to specified op:  <package>[<element>] = <src> */
+void acpigen_set_package_element_int(const char *package, unsigned int element, uint64_t src);
+
+/* Set element of package to specified namestr:  <package>[<element>] = <src> */
+void acpigen_set_package_element_namestr(const char *package, unsigned int element,
+					 const char *src);
+
+/*
+ * Delay up to wait_ms milliseconds until the provided name matches the expected value.
+ * If wait_ms is >= 32ms then it will wait in 16ms chunks.  This function uses LOCAL7_OP.
+ */
+void acpigen_write_delay_until_namestr_int(uint32_t wait_ms, const char *name, uint64_t value);
+
 /*
  * Soc-implemented functions for generating ACPI AML code for GPIO handling. All
  * these functions are expected to use only Local5, Local6 and Local7

src/include/console/uart.h

@@ -20,6 +20,18 @@ static inline unsigned int get_uart_baudrate(void)
 }
 #endif
 
+#if CONFIG(OVERRIDE_UART_FOR_CONSOLE)
+/* Return the index of uart port, define this in your platform
+ * when need to use variables to override the index.
+ */
+unsigned int get_uart_for_console(void);
+#else
+static inline unsigned int get_uart_for_console(void)
+{
+	return CONFIG_UART_FOR_CONSOLE;
+}
+#endif
+
 /* Returns the divisor value for a given baudrate.
  * The formula to satisfy is:
  *    refclk / divisor = baudrate * oversample
@@ -56,15 +68,15 @@ void oxford_remap(unsigned int new_base);
 #if __CONSOLE_SERIAL_ENABLE__
 static inline void __uart_init(void)
 {
-	uart_init(CONFIG_UART_FOR_CONSOLE);
+	uart_init(get_uart_for_console());
 }
 static inline void __uart_tx_byte(u8 data)
 {
-	uart_tx_byte(CONFIG_UART_FOR_CONSOLE, data);
+	uart_tx_byte(get_uart_for_console(), data);
 }
 static inline void __uart_tx_flush(void)
 {
-	uart_tx_flush(CONFIG_UART_FOR_CONSOLE);
+	uart_tx_flush(get_uart_for_console());
 }
 #else
 static inline void __uart_init(void)		{}

src/include/cpu/x86/mtrr.h

@@ -31,9 +31,10 @@
 #define IA32_SMRR_PHYS_MASK		0x1f3
 #define SMRR_PHYS_MASK_LOCK		(1 << 10)
 
-/* Specific to model_6fx and model_1067x */
+/* Specific to model_6fx and model_1067x.
-#define MSR_SMRR_PHYS_BASE		0xa0
+   These are named MSR_SMRR_PHYSBASE in the SDM. */
-#define MSR_SMRR_PHYS_MASK		0xa1
+#define CORE2_SMRR_PHYS_BASE		0xa0
+#define CORE2_SMRR_PHYS_MASK		0xa1
 
 #define MTRR_PHYS_BASE(reg)		(0x200 + 2 * (reg))
 #define MTRR_PHYS_MASK(reg)		(MTRR_PHYS_BASE(reg) + 1)

src/include/cpu/x86/save_state.h

@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __CPU_X86_SAVE_STATE_H__
+#define __CPU_X86_SAVE_STATE_H__
+
+#include <stdint.h>
+
+enum cpu_reg {
+	RAX,
+	RBX,
+	RCX,
+	RDX
+};
+
+#define SMM_REV_INVALID 0xffffffff
+
+struct smm_save_state_ops {
+	const uint32_t *revision_table;
+	/* Accessors for CPU registers in the SMM save state
+	   Returns -1 on failure, 0 on success */
+	int (*get_reg)(const enum cpu_reg reg, const int node, void *out, const uint8_t length);
+	int (*set_reg)(const enum cpu_reg reg, const int node, void *in, const uint8_t length);
+	/* Returns -1 on failure, the node on which the 'cmd' was send on success */
+	int (*apmc_node)(u8 cmd);
+};
+
+/* Return -1 on failure, otherwise returns which CPU node issued an APMC IO write */
+int get_apmc_node(u8 cmd);
+/* Return -1 on failure, 0 on succes.
+   Accessors for the SMM save state CPU registers RAX, RBX, RCX and RDX */
+int get_save_state_reg(const enum cpu_reg reg, const int node, void *out, const uint8_t length);
+int set_save_state_reg(const enum cpu_reg reg, const int node, void *in, const uint8_t length);
+
+#endif /* __CPU_X86_SAVE_STATE_H__ */

src/include/cpu/x86/smm.h

@@ -197,5 +197,8 @@ void smm_list_regions(void);
 /* Return the SMM save state revision. The revision can be fetched from the smm savestate
    which is always at the same offset downward from the top of the save state. */
 uint32_t smm_revision(void);
+/* Returns the PM ACPI SMI port. On Intel systems this typically not configurable (APM_CNT, 0xb2).
+   On AMD systems it is sometimes configurable. */
+uint16_t pm_acpi_smi_cmd_port(void);
 
 #endif /* CPU_X86_SMM_H */

src/include/device/pci.h

@@ -79,15 +79,6 @@ void pci_bus_enable_resources(struct device *dev);
 void pci_bus_reset(struct bus *bus);
 struct device *pci_probe_dev(struct device *dev, struct bus *bus,
 				unsigned int devfn);
-
-/*
- * Determine if the given PCI device is the source of wake from sleep by checking PME_STATUS and
- * PME_ENABLE bits in PM control and status register.
- *
- * Returns true if PCI device is wake source, false otherwise.
- */
-bool pci_dev_is_wake_source(const struct device *dev);
-
 void do_pci_scan_bridge(struct device *dev,
 	void (*do_scan_bus)(struct bus *bus,
 		unsigned int min_devfn, unsigned int max_devfn));

src/include/device/pci_ids.h

@@ -2926,6 +2926,7 @@
 #define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_29		0x7a1d
 #define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_30		0x7a1e
 #define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_31		0x7a1f
+#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_32		0x5181
 #define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_0		0x7a80
 #define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_1		0x7a81
 #define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_2		0x7a82

src/include/device/pci_ops.h

@@ -209,4 +209,12 @@ u16 pci_find_capability(const struct device *dev, u16 cap)
 	return pci_s_find_capability(PCI_BDF(dev), cap);
 }
 
+/*
+ * Determine if the given PCI device is the source of wake from sleep by checking PME_STATUS and
+ * PME_ENABLE bits in PM control and status register.
+ *
+ * Returns true if PCI device is wake source, false otherwise.
+ */
+bool pci_dev_is_wake_source(const struct device *dev);
+
 #endif /* PCI_OPS_H */

src/mainboard/51nb/x210/devicetree.cb

@@ -55,7 +55,6 @@ chip soc/intel/skylake
 	register "PmConfigSlpS4MinAssert" = "1"		# 1s
 	register "PmConfigSlpSusMinAssert" = "3"	# 500ms
 	register "PmConfigSlpAMinAssert" = "3"		# 2s
-	register "PmTimerDisabled" = "0"
 
 	register "serirq_mode" = "SERIRQ_CONTINUOUS"
 

src/mainboard/amd/mandolin/Kconfig

@@ -24,10 +24,10 @@ config AMD_LPC_DEBUG_CARD
 	select PICASSO_LPC_IOMUX
 	select SUPERIO_SMSC_SIO1036
 	help
-	  AMD's debug card contains an SMSC SIO1036 device which provides
+	  AMD's debug card contains an SMSC SIO1036 device which provides an
-	  an I/O-based UART in the system.  This feature is not compatible with
+	  I/O-mapped UART in the system. This is mutually exclusive with
-	  CONFIG_HUDSON_UART enabling the memory-mapped UART in the chipset.
+	  PICASSO_CONSOLE_UART which selects the SoC's integrated memory-mapped
-	  Note that Kconfig does not currently enforce this restriction.
+	  UART for coreboot console output.
 
 config CBFS_SIZE
 	hex
@@ -52,10 +52,6 @@ config DEVICETREE
 	string
 	default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"
 
-config MAX_CPUS
-	int
-	default 8
-
 config ONBOARD_VGA_IS_PRIMARY
 	bool
 	default y
@@ -76,6 +72,9 @@ config MANDOLIN_MCHP_FW_FILE
 	depends on MANDOLIN_HAVE_MCHP_FW
 	default "3rdparty/blobs/mainboard/amd/mandolin/EC_mandolin.bin" if BOARD_AMD_MANDOLIN
 	default "3rdparty/blobs/mainboard/amd/mandolin/EC_cereme.bin" if BOARD_AMD_CEREME
+	help
+	  The EC firmware blob is usually the first 128kByte of the stock
+	  firmware image.
 
 if !AMD_LPC_DEBUG_CARD
 choice

src/mainboard/asrock/b85m_pro4/devicetree.cb

@@ -27,7 +27,6 @@ chip northbridge/intel/haswell
 
 		chip southbridge/intel/lynxpoint
 			register "gen1_dec"      = "0x000c0291"	# Super I/O HWM
-			register "sata_ahci"     = "1"
 			register "sata_port_map" = "0x3f"
 
 			device pci 14.0 on  end		# xHCI controller

src/mainboard/asrock/b85m_pro4/dsdt.asl

@@ -20,7 +20,7 @@ DefinitionBlock(
 
 	Device (\_SB.PCI0)
 	{
-		#include <northbridge/intel/haswell/acpi/haswell.asl>
+		#include <northbridge/intel/haswell/acpi/hostbridge.asl>
 		#include <southbridge/intel/lynxpoint/acpi/pch.asl>
 		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 	}

src/mainboard/asrock/h110m/devicetree.cb

@@ -24,7 +24,6 @@ chip soc/intel/skylake
 	# FSP Configuration
 	register "PrimaryDisplay" = "Display_PEG"
 	register "SaGv" = "SaGv_Enabled"
-	register "PmTimerDisabled" = "0"
 
 	# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
 	# SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s

src/mainboard/asrock/h81m-hds/devicetree.cb

@@ -35,7 +35,6 @@ chip northbridge/intel/haswell
 		end
 
 		chip southbridge/intel/lynxpoint
-			register "sata_ahci" = "1"
 			register "sata_port_map" = "0x33"
 
 			register "gen1_dec" = "0x00000295" # Super I/O HWM

src/mainboard/asrock/h81m-hds/dsdt.asl

@@ -20,7 +20,7 @@ DefinitionBlock(
 	{
 		Device (PCI0)
 		{
-		#include <northbridge/intel/haswell/acpi/haswell.asl>
+		#include <northbridge/intel/haswell/acpi/hostbridge.asl>
 		#include <southbridge/intel/lynxpoint/acpi/pch.asl>
 		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}

src/mainboard/asus/f2a85-m/Kconfig

@@ -84,7 +84,7 @@ config VGA_BIOS_ID
 
 config HUDSON_LEGACY_FREE
 	bool
-	default y
+	default n
 
 config POST_IO
 	bool

src/mainboard/clevo/Kconfig

@@ -12,4 +12,4 @@ source "src/mainboard/clevo/*/Kconfig"
 config MAINBOARD_VENDOR
 	default "Clevo"
 
-endif
+endif # VENDOR_CLEVO

src/mainboard/clevo/cml-u/Kconfig

@@ -9,6 +9,8 @@ config BOARD_SPECIFIC_OPTIONS
 	select HAVE_ACPI_TABLES
 	select HAVE_SMI_HANDLER
 	select HAVE_SPD_IN_CBFS
+	select HAVE_OPTION_TABLE
+	select HAVE_CMOS_DEFAULT
 	select INTEL_GMA_HAVE_VBT
 	select INTEL_LPSS_UART_FOR_CONSOLE
 	select MAINBOARD_HAS_LPC_TPM

src/mainboard/clevo/cml-u/cmos.default

@@ -0,0 +1,3 @@
+boot_option=Fallback
+debug_level=Debug
+power_on_after_fail=Disable

src/mainboard/clevo/cml-u/cmos.layout

@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# start-bit	length	config	config-ID	name
+0		120	r	0		reserved_memory
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384		  1	e	4		boot_option
+388		  4	h	0		reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395		  4    e	6		debug_level
+
+# -----------------------------------------------------------------
+# coreboot config options: cpu
+400		  1    e	2		hyper_threading
+
+# -----------------------------------------------------------------
+# coreboot config options: southbridge
+410		  2	e	7		power_on_after_fail
+
+# -----------------------------------------------------------------
+# vboot nv area
+800		128	r	0		vbnv
+
+# -----------------------------------------------------------------
+# coreboot config options: check sums
+984		 16	h	0		check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+6     0     Emergency
+6     1     Alert
+6     2     Critical
+6     3     Error
+6     4     Warning
+6     5     Notice
+6     6     Info
+6     7     Debug
+6     8     Spew
+7     0     Disable
+7     1     Enable
+7     2     Keep
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 799 984

src/mainboard/clevo/cml-u/variants/l140cu/ramstage.c

@@ -6,6 +6,6 @@
 void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 {
 	/* Configure pads prior to SiliconInit() in case there's any
-	 * dependencies during hardware initialization. */
+	   dependencies during hardware initialization. */
 	cnl_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
 }

src/mainboard/emulation/qemu-aarch64/memlayout.ld

@@ -21,7 +21,8 @@ SECTIONS
 	BOOTBLOCK(0x60010000, 64K)
 	STACK(0x60020000, 62K)
 	FMAP_CACHE(0x6002F800, 2K)
-	ROMSTAGE(0x60030000, 128K)
+        TIMESTAMP(0x60030000, 1K)
+	ROMSTAGE(0x60031000, 128K)
 	TTB(0x60070000, 128K)
 	RAMSTAGE(0x600b0000, 16M)
 

src/mainboard/emulation/qemu-q35/Makefile.inc

@@ -14,3 +14,5 @@ ramstage-y += ../qemu-i440fx/northbridge.c
 verstage-$(CONFIG_CHROMEOS) += chromeos.c
 verstage-$(CONFIG_CHROMEOS) += ../qemu-i440fx/fw_cfg.c
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += smi.c

src/mainboard/emulation/qemu-q35/smi.c

@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cpu/x86/smm.h>
+
+/* The X86 qemu target uses AMD64 save states but the APM port is not configurable. */
+uint16_t pm_acpi_smi_cmd_port(void)
+{
+	return APM_CNT;
+}