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AGESA f10 vendorcode: Remove refcode sources

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We never had a board in the tree that implements this.

Change-Id: Idce32a20c24e31eb52f8509d4a7cccfc24cf17cf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Kyösti Mälkki
2017-08-24 08:18:26 +03:00
parent e029c18f67
commit e363894d06
545 changed files with 0 additions and 158518 deletions
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1
src/vendorcode/amd/agesa/Makefile.inc
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@ -1,4 +1,3 @@
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY10) += f10
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += f12
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += f14
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15) += f15

2897
src/vendorcode/amd/agesa/f10/AGESA.h
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478
src/vendorcode/amd/agesa/f10/AMD.h
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@ -1,478 +0,0 @@
/**
* @file
*
* Agesa structures and definitions
*
* Contains AMD AGESA core interface
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Include
* @e \$Revision: 7668 $ @e \$Date: 2008-08-25 18:59:15 -0700 (Mon, 25 Aug 2008) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#ifndef _AMD_H_
#define _AMD_H_
#define AGESA_REVISION "Arch2008"
#define AGESA_ID "AGESA"
#define Int16FromChar(a,b) ((a) << 0 | (b) << 8)
#define Int32FromChar(a,b,c,d) ((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24)
//
//
// AGESA Types and Definitions
//
//
#define LAST_ENTRY 0xFFFFFFFF
#define IMAGE_SIGNATURE Int32FromChar ('$', 'A', 'M', 'D')
#define IOCF8 0xCF8
#define IOCFC 0xCFC
/// The return status for all AGESA public services.
///
/// Services return the most severe status of any logged event. Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK
/// will have log entries with more detail.
///
typedef enum {
AGESA_SUCCESS = 0, ///< The service completed normally. Info may be logged.
AGESA_UNSUPPORTED, ///< The dispatcher or create struct had an unimplemented function requested.
///< Not logged.
AGESA_BOUNDS_CHK, ///< A dynamic parameter was out of range and the service was not provided.
///< Example, memory address not installed, heap buffer handle not found.
///< Not Logged.
// AGESA_STATUS of greater severity (the ones below this line), always have a log entry available.
AGESA_ALERT, ///< An observed condition, but no loss of function.
///< See log. Example, HT CRC.
AGESA_WARNING, ///< Possible or minor loss of function. See Log.
AGESA_ERROR, ///< Significant loss of function, boot may be possible. See Log.
AGESA_CRITICAL, ///< Continue boot only to notify user. See Log.
AGESA_FATAL, ///< Halt booting. See Log, however Fatal errors pertaining to heap problems
///< may not be able to reliably produce log events.
AgesaStatusMax ///< Not a status, for limit checking.
} AGESA_STATUS;
/// For checking whether a status is at or above the mandatory log level.
#define AGESA_STATUS_LOG_LEVEL AGESA_ALERT
/**
* Callout method to the host environment.
*
* Callout using a dispatch with appropriate thunk layer, which is determined by the host environment.
*
* @param[in] Function The specific callout function being invoked.
* @param[in] FcnData Function specific data item.
* @param[in,out] ConfigPtr Reference to Callout params.
*/
typedef AGESA_STATUS (*CALLOUT_ENTRY) (
IN UINT32 Function,
IN UINTN FcnData,
IN OUT VOID *ConfigPtr
);
typedef AGESA_STATUS (*IMAGE_ENTRY) (VOID *ConfigPtr);
typedef AGESA_STATUS (*MODULE_ENTRY) (VOID *ConfigPtr);
///This allocation type is used by the AmdCreateStruct entry point
typedef enum {
PreMemHeap = 0, ///< Create heap in cache.
PostMemDram, ///< Create heap in memory.
ByHost ///< Create heap by Host.
} ALLOCATION_METHOD;
/// These width descriptors are used by the library function, and others, to specify the data size
typedef enum ACCESS_WIDTH {
AccessWidth8 = 1, ///< Access width is 8 bits.
AccessWidth16, ///< Access width is 16 bits.
AccessWidth32, ///< Access width is 32 bits.
AccessWidth64, ///< Access width is 64 bits.
AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data.
AccessS3SaveWidth16, ///< Save 16 bits data.
AccessS3SaveWidth32, ///< Save 32 bits data.
AccessS3SaveWidth64, ///< Save 64 bits data.
} ACCESS_WIDTH;
/// AGESA struct name
typedef enum {
// AGESA BASIC FUNCTIONS
AMD_INIT_RECOVERY = 0x00020000, ///< AmdInitRecovery entry point handle
AMD_CREATE_STRUCT, ///< AmdCreateStruct handle
AMD_INIT_EARLY, ///< AmdInitEarly entry point handle
AMD_INIT_ENV, ///< AmdInitEnv entry point handle
AMD_INIT_LATE, ///< AmdInitLate entry point handle
AMD_INIT_MID, ///< AmdInitMid entry point handle
AMD_INIT_POST, ///< AmdInitPost entry point handle
AMD_INIT_RESET, ///< AmdInitReset entry point handle
AMD_INIT_RESUME, ///< AmdInitResume entry point handle
AMD_RELEASE_STRUCT, ///< AmdReleaseStruct handle
AMD_S3LATE_RESTORE, ///< AmdS3LateRestore entry point handle
AMD_S3_SAVE, ///< AmdS3Save entry point handle
AMD_GET_APIC_ID, ///< AmdGetApicId entry point handle
AMD_GET_PCI_ADDRESS, ///< AmdGetPciAddress entry point handle
AMD_IDENTIFY_CORE, ///< AmdIdentifyCore general service handle
AMD_READ_EVENT_LOG, ///< AmdReadEventLog general service handle
AMD_LATE_RUN_AP_TASK, ///< AmdLateRunApTask entry point handle
AMD_IDENTIFY_DIMMS ///< AmdIdentifyDimm general service handle
} AGESA_STRUCT_NAME;
/* ResetType constant values */
#define WARM_RESET_WHENEVER 1
#define COLD_RESET_WHENEVER 2
#define WARM_RESET_IMMEDIATELY 3
#define COLD_RESET_IMMEDIATELY 4
// AGESA Structures
/// The standard header for all AGESA services.
/// For internal AGESA naming conventions, see @ref amdconfigparamname .
typedef struct {
IN UINT32 ImageBasePtr; ///< The AGESA Image base address.
IN UINT32 Func; ///< The service desired
IN UINT32 AltImageBasePtr; ///< Alternate Image location
IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA
IN UINT8 HeapStatus; ///< For heap status from boot time slide.
IN UINT64 HeapBasePtr; ///< Location of the heap
IN OUT UINT8 Reserved[7]; ///< This space is reserved for future use.
} AMD_CONFIG_PARAMS;
/// Create Struct Interface.
typedef struct {
IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
IN AGESA_STRUCT_NAME AgesaFunctionName; ///< The service to init
IN ALLOCATION_METHOD AllocationMethod; ///< How to handle buffer allocation
IN OUT UINT32 NewStructSize; ///< The size of the allocated data, in for ByHost, else out only.
IN OUT VOID *NewStructPtr; ///< The struct for the service.
///< The struct to init for ByHost allocation,
///< the initialized struct on return.
} AMD_INTERFACE_PARAMS;
#define FUNC_0 0 // bit-placed for PCI address creation
#define FUNC_1 1
#define FUNC_2 2
#define FUNC_3 3
#define FUNC_4 4
#define FUNC_5 5
#define FUNC_6 6
#define FUNC_7 7
/// AGESA Binary module header structure
typedef struct {
IN UINT32 Signature; ///< Binary Signature
IN CHAR8 CreatorID[8]; ///< 8 characters ID
IN CHAR8 Version[12]; ///< 12 characters version
IN UINT32 ModuleInfoOffset; ///< Offset of module
IN UINT32 EntryPointAddress; ///< Entry address
IN UINT32 ImageBase; ///< Image base
IN UINT32 RelocTableOffset; ///< Relocate Table offset
IN UINT32 ImageSize; ///< Size
IN UINT16 Checksum; ///< Checksum
IN UINT8 ImageType; ///< Type
IN UINT8 V_Reserved; ///< Reserved
} AMD_IMAGE_HEADER;
/// AGESA Binary module header structure
typedef struct _AMD_MODULE_HEADER {
IN UINT32 ModuleHeaderSignature; ///< Module signature
IN CHAR8 ModuleIdentifier[8]; ///< 8 characters ID
IN CHAR8 ModuleVersion[12]; ///< 12 characters version
IN VOID *ModuleDispatcher; ///< A pointer point to dispatcher
IN struct _AMD_MODULE_HEADER *NextBlock; ///< Next module header link
} AMD_MODULE_HEADER;
// AMD_CODE_HEADER Signatures.
#define AGESA_CODE_SIGNATURE {'!', '!', 'A', 'G', 'E', 'S', 'A', ' '}
#define CIMXNB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'}
#define CIMXSB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'}
/// AGESA_CODE_SIGNATURE
typedef struct {
IN CHAR8 Signature[8]; ///< code header Signature
IN CHAR8 ComponentName[8]; ///< 8 character name of the code module
IN CHAR8 Version[12]; ///< 12 character version string
IN CHAR8 TerminatorNull; ///< null terminated string
IN CHAR8 VerReserved[7]; ///< reserved space
} AMD_CODE_HEADER;
/// Extended PCI address format
typedef struct {
IN OUT UINT32 Register:12; ///< Register offset
IN OUT UINT32 Function:3; ///< Function number
IN OUT UINT32 Device:5; ///< Device number
IN OUT UINT32 Bus:8; ///< Bus number
IN OUT UINT32 Segment:4; ///< Segment
} EXT_PCI_ADDR;
/// Union type for PCI address
typedef union _PCI_ADDR {
IN UINT32 AddressValue; ///< Formal address
IN EXT_PCI_ADDR Address; ///< Extended address
} PCI_ADDR;
// SBDFO - Segment Bus Device Function Offset
// 31:28 Segment (4-bits)
// 27:20 Bus (8-bits)
// 19:15 Device (5-bits)
// 14:12 Function(3-bits)
// 11:00 Offset (12-bits)
#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((UINT32) (Seg)) << 28) | (((UINT32) (Bus)) << 20) | \
(((UINT32)(Dev)) << 15) | (((UINT32)(Fun)) << 12) | ((UINT32)(Off)))
#define ILLEGAL_SBDFO 0xFFFFFFFF
/// CPUID data received registers format
typedef struct {
OUT UINT32 EAX_Reg; ///< CPUID instruction result in EAX
OUT UINT32 EBX_Reg; ///< CPUID instruction result in EBX
OUT UINT32 ECX_Reg; ///< CPUID instruction result in ECX
OUT UINT32 EDX_Reg; ///< CPUID instruction result in EDX
} CPUID_DATA;
/// HT frequency for external callbacks
typedef enum {
HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks
HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks
HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks
HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks
HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks
HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks
HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks
HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks
HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks
HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks
HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks
HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks
HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks
HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks
HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks
HT_FREQUENCY_3200M = 19, ///< HT speed 3200 for external callbacks
HT_FREQUENCY_MAX ///< Limit check.
} HT_FREQUENCIES;
// The minimum HT3 frequency
#define HT3_FREQUENCY_MIN HT_FREQUENCY_1200M
#ifndef BIT0
#define BIT0 0x0000000000000001ull
#endif
#ifndef BIT1
#define BIT1 0x0000000000000002ull
#endif
#ifndef BIT2
#define BIT2 0x0000000000000004ull
#endif
#ifndef BIT3
#define BIT3 0x0000000000000008ull
#endif
#ifndef BIT4
#define BIT4 0x0000000000000010ull
#endif
#ifndef BIT5
#define BIT5 0x0000000000000020ull
#endif
#ifndef BIT6
#define BIT6 0x0000000000000040ull
#endif
#ifndef BIT7
#define BIT7 0x0000000000000080ull
#endif
#ifndef BIT8
#define BIT8 0x0000000000000100ull
#endif
#ifndef BIT9
#define BIT9 0x0000000000000200ull
#endif
#ifndef BIT10
#define BIT10 0x0000000000000400ull
#endif
#ifndef BIT11
#define BIT11 0x0000000000000800ull
#endif
#ifndef BIT12
#define BIT12 0x0000000000001000ull
#endif
#ifndef BIT13
#define BIT13 0x0000000000002000ull
#endif
#ifndef BIT14
#define BIT14 0x0000000000004000ull
#endif
#ifndef BIT15
#define BIT15 0x0000000000008000ull
#endif
#ifndef BIT16
#define BIT16 0x0000000000010000ull
#endif
#ifndef BIT17
#define BIT17 0x0000000000020000ull
#endif
#ifndef BIT18
#define BIT18 0x0000000000040000ull
#endif
#ifndef BIT19
#define BIT19 0x0000000000080000ull
#endif
#ifndef BIT20
#define BIT20 0x0000000000100000ull
#endif
#ifndef BIT21
#define BIT21 0x0000000000200000ull
#endif
#ifndef BIT22
#define BIT22 0x0000000000400000ull
#endif
#ifndef BIT23
#define BIT23 0x0000000000800000ull
#endif
#ifndef BIT24
#define BIT24 0x0000000001000000ull
#endif
#ifndef BIT25
#define BIT25 0x0000000002000000ull
#endif
#ifndef BIT26
#define BIT26 0x0000000004000000ull
#endif
#ifndef BIT27
#define BIT27 0x0000000008000000ull
#endif
#ifndef BIT28
#define BIT28 0x0000000010000000ull
#endif
#ifndef BIT29
#define BIT29 0x0000000020000000ull
#endif
#ifndef BIT30
#define BIT30 0x0000000040000000ull
#endif
#ifndef BIT31
#define BIT31 0x0000000080000000ull
#endif
#ifndef BIT32
#define BIT32 0x0000000100000000ull
#endif
#ifndef BIT33
#define BIT33 0x0000000200000000ull
#endif
#ifndef BIT34
#define BIT34 0x0000000400000000ull
#endif
#ifndef BIT35
#define BIT35 0x0000000800000000ull
#endif
#ifndef BIT36
#define BIT36 0x0000001000000000ull
#endif
#ifndef BIT37
#define BIT37 0x0000002000000000ull
#endif
#ifndef BIT38
#define BIT38 0x0000004000000000ull
#endif
#ifndef BIT39
#define BIT39 0x0000008000000000ull
#endif
#ifndef BIT40
#define BIT40 0x0000010000000000ull
#endif
#ifndef BIT41
#define BIT41 0x0000020000000000ull
#endif
#ifndef BIT42
#define BIT42 0x0000040000000000ull
#endif
#ifndef BIT43
#define BIT43 0x0000080000000000ull
#endif
#ifndef BIT44
#define BIT44 0x0000100000000000ull
#endif
#ifndef BIT45
#define BIT45 0x0000200000000000ull
#endif
#ifndef BIT46
#define BIT46 0x0000400000000000ull
#endif
#ifndef BIT47
#define BIT47 0x0000800000000000ull
#endif
#ifndef BIT48
#define BIT48 0x0001000000000000ull
#endif
#ifndef BIT49
#define BIT49 0x0002000000000000ull
#endif
#ifndef BIT50
#define BIT50 0x0004000000000000ull
#endif
#ifndef BIT51
#define BIT51 0x0008000000000000ull
#endif
#ifndef BIT52
#define BIT52 0x0010000000000000ull
#endif
#ifndef BIT53
#define BIT53 0x0020000000000000ull
#endif
#ifndef BIT54
#define BIT54 0x0040000000000000ull
#endif
#ifndef BIT55
#define BIT55 0x0080000000000000ull
#endif
#ifndef BIT56
#define BIT56 0x0100000000000000ull
#endif
#ifndef BIT57
#define BIT57 0x0200000000000000ull
#endif
#ifndef BIT58
#define BIT58 0x0400000000000000ull
#endif
#ifndef BIT59
#define BIT59 0x0800000000000000ull
#endif
#ifndef BIT60
#define BIT60 0x1000000000000000ull
#endif
#ifndef BIT61
#define BIT61 0x2000000000000000ull
#endif
#ifndef BIT62
#define BIT62 0x4000000000000000ull
#endif
#ifndef BIT63
#define BIT63 0x8000000000000000ull
#endif
#endif // _AMD_H_

51
src/vendorcode/amd/agesa/f10/Dispatcher.h
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@ -1,51 +0,0 @@
/**
* @file
*
* AMD Pushhigh Interface
*
* Contains interface to Pushhigh entry
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Legacy
* @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*/
#ifndef _DISPATCHER_H_
#define _DISPATCHER_H_
// AGESA function prototypes
AGESA_STATUS CALLCONV AmdAgesaDispatcher ( IN OUT VOID *ConfigPtr );
AGESA_STATUS CALLCONV AmdAgesaCallout ( IN UINT32 Func, IN UINTN Data, IN OUT VOID *ConfigPtr );
#endif // _DISPATCHER_H_

166
src/vendorcode/amd/agesa/f10/Include/AdvancedApi.h
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@ -1,166 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Advanced API Interface for HT, Memory and CPU
*
* Contains additional declarations need to use HT, Memory and CPU Advanced interface, such as
* would be required by the basic interface implementations.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Include
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _ADVANCED_API_H_
#define _ADVANCED_API_H_
/*----------------------------------------------------------------------------
* HT FUNCTIONS PROTOTYPE
*
*----------------------------------------------------------------------------
*/
/**
* A constructor for the HyperTransport input structure.
*
* Sets inputs to valid, basic level, defaults.
*
* @param[in] StdHeader Opaque handle to standard config header
* @param[in] AmdHtInterface HT Interface structure to initialize.
*
* @retval AGESA_SUCCESS Constructors are not allowed to fail
*/
AGESA_STATUS
AmdHtInterfaceConstructor (
IN AMD_CONFIG_PARAMS *StdHeader,
IN AMD_HT_INTERFACE *AmdHtInterface
);
/**
* The top level external interface for Hypertransport Initialization.
*
* Create our initial internal state, initialize the coherent fabric,
* initialize the non-coherent chains, and perform any required fabric tuning or
* optimization.
*
* @param[in] StdHeader Opaque handle to standard config header
* @param[in] PlatformConfiguration The platform configuration options.
* @param[in] AmdHtInterface HT Interface structure.
*
* @retval AGESA_SUCCESS Only information events logged.
* @retval AGESA_ALERT Sync Flood or CRC error logged.
* @retval AGESA_WARNING Example: expected capability not found
* @retval AGESA_ERROR logged events indicating some devices may not be available
* @retval AGESA_FATAL Mixed Family or MP capability mismatch
*
*/
AGESA_STATUS
AmdHtInitialize (
IN AMD_CONFIG_PARAMS *StdHeader,
IN PLATFORM_CONFIGURATION *PlatformConfiguration,
IN AMD_HT_INTERFACE *AmdHtInterface
);
/*----------------------------------------------------------------------------
* HT Recovery FUNCTIONS PROTOTYPE
*
*----------------------------------------------------------------------------
*/
/**
* A constructor for the HyperTransport input structure.
*
*/
AGESA_STATUS
AmdHtResetConstructor (
IN AMD_CONFIG_PARAMS *StdHeader,
IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface
);
/**
* Initialize HT at Reset for both Normal and Recovery.
*
*/
AGESA_STATUS
AmdHtInitReset (
IN AMD_CONFIG_PARAMS *StdHeader,
IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface
);
/**
* Initialize the Node and Socket maps for an AP Core.
*
*/
AGESA_STATUS
AmdHtInitRecovery (
IN AMD_CONFIG_PARAMS *StdHeader
);
///----------------------------------------------------------------------------
/// MEMORY FUNCTIONS PROTOTYPE
///
///----------------------------------------------------------------------------
AGESA_STATUS
AmdMemRecovery (
IN OUT MEM_DATA_STRUCT *MemPtr
);
AGESA_STATUS
AmdMemAuto (
IN OUT MEM_DATA_STRUCT *MemPtr
);
VOID
AmdMemInitDataStructDef (
IN OUT MEM_DATA_STRUCT *MemPtr,
IN OUT PLATFORM_CONFIGURATION *PlatFormConfig
);
VOID
memDefRet ( VOID );
BOOLEAN
memDefTrue ( VOID );
BOOLEAN
memDefFalse ( VOID );
VOID
MemRecDefRet ( VOID );
BOOLEAN
MemRecDefTrue ( VOID );
#endif // _ADVANCED_API_H_

124
src/vendorcode/amd/agesa/f10/Include/CommonReturns.h
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@ -1,124 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Common Return routines.
*
* Routines which do nothing, returning a result (preferably some version of zero) which
* is consistent with "do nothing" or "default". Useful for function pointer tables.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Common
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ***************************************************************************
*
*/
#ifndef _COMMON_RETURNS_H_
#define _COMMON_RETURNS_H_
/**
* Return True
*
* @retval True Default case, no special action
*/
BOOLEAN
CommonReturnTrue ( VOID );
/**
* Return False.
*
* @retval FALSE Default case, no special action
*/
BOOLEAN
CommonReturnFalse ( VOID );
/**
* Return (UINT8)zero.
*
*
* @retval zero None, or only case zero.
*/
UINT8
CommonReturnZero8 ( VOID );
/**
* Return (UINT32)zero.
*
*
* @retval zero None, or only case zero.
*/
UINT32
CommonReturnZero32 ( VOID );
/**
* Return (UINT64)zero.
*
*
* @retval zero None, or only case zero.
*/
UINT64
CommonReturnZero64 ( VOID );
/**
* Return NULL
*
* @retval NULL pointer to nothing
*/
VOID *
CommonReturnNULL ( VOID );
/**
* Return AGESA_SUCCESS.
*
* @retval AGESA_SUCCESS Success.
*/
AGESA_STATUS
CommonReturnAgesaSuccess ( VOID );
/**
* Do Nothing.
*
*/
VOID
CommonVoid ( VOID );
/**
* ASSERT if this routine is called.
*
*/
VOID
CommonAssert ( VOID );
#endif // _COMMON_RETURNS_H_

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src/vendorcode/amd/agesa/f10/Include/Filecode.h
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@ -1,547 +0,0 @@
/**
* @file
*
* Collectively assign unique filecodes for assert and debug to each source file.
*
* Publish values for decorated filenames, which can be used for
* ASSERT and debug support using a preprocessor define like:
* @n <tt> \#define FILECODE MY_C_FILENAME_FILECODE </tt> @n
* This file serves as a reference for debugging to associate the code and filename.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Include
* @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#ifndef _FILECODE_H_
#define _FILECODE_H_
#define UNASSIGNED_FILE_FILECODE (0xFFFF)
/// For debug use in any Platform's options C file.
/// Can be reused for platforms and image builds, since only one options file can be built.
#define PLATFORM_SPECIFIC_OPTIONS_FILECODE (0xBBBB)
#define PROC_GNB_GNBINITATEARLY_FILECODE (0xA001)
#define PROC_GNB_GNBINITATENV_FILECODE (0xA002)
#define PROC_GNB_GNBINITATLATE_FILECODE (0xA003)
#define PROC_GNB_GNBINITATMID_FILECODE (0xA004)
#define PROC_GNB_GNBINITATPOST_FILECODE (0xA005)
#define PROC_GNB_GNBINITATRESET_FILECODE (0xA006)
#define PROC_GNB_COMMON_CPUACCLIB_FILECODE (0xA010)
#define PROC_GNB_COMMON_GNBHEAPLIB_FILECODE (0xA011)
#define PROC_GNB_COMMON_GNBLIB_FILECODE (0xA012)
#define PROC_GNB_COMMON_MEMACCLIB_FILECODE (0xA013)
#define PROC_GNB_COMMON_PCIACCLIB_FILECODE (0xA014)
#define PROC_GNB_COMMON_PCILIB_FILECODE (0xA015)
#define PROC_GNB_COMMON_IOACCLIB_FILECODE (0xA016)
#define PROC_GNB_GFX_GFXCARDINFO_FILECODE (0xA020)
#define PROC_GNB_GFX_GFXCONFIGDATA_FILECODE (0xA021)
#define PROC_GNB_GFX_GFXGMCINIT_FILECODE (0xA022)
#define PROC_GNB_GFX_GFXINITATENVPOST_FILECODE (0xA023)
#define PROC_GNB_GFX_GFXINITATMIDPOST_FILECODE (0xA024)
#define PROC_GNB_GFX_GFXINITATPOST_FILECODE (0xA025)
#define PROC_GNB_GFX_GFXINTEGRATEDINFOTABLEINIT_FILECODE (0xA026)
#define PROC_GNB_GFX_GFXREGISTERACC_FILECODE (0xA027)
#define PROC_GNB_GFX_GFXSTRAPSINIT_FILECODE (0xA028)
#define PROC_GNB_GFX_FAMILY_0X12_F12GFXSERVICES_FILECODE (0xA029)
#define PROC_GNB_GFX_FAMILY_0X14_F14GFXSERVICES_FILECODE (0xA02A)
#define PROC_GNB_NB_NBCONFIGDATA_FILECODE (0xA030)
#define PROC_GNB_NB_NBINIT_FILECODE (0xA031)
#define PROC_GNB_NB_NBINITATEARLY_FILECODE (0xA032)
#define PROC_GNB_NB_NBINITATLATEPOST_FILECODE (0xA033)
#define PROC_GNB_NB_NBINITATRESET_FILECODE (0xA034)
#define PROC_GNB_NB_NBINITATENV_FILECODE (0xA035)
#define PROC_GNB_NB_NBSMULIB_FILECODE (0xA036)
#define PROC_GNB_NB_NBSMUSERVICES_FILECODE (0xA037)
#define PROC_GNB_NB_FAMILY_0X12_F12NBSERVICES_FILECODE (0xA038)
#define PROC_GNB_NB_FAMILY_0X14_F14NBSERVICES_FILECODE (0xA039)
#define PROC_GNB_PCIE_PCIECONFIGDATA_FILECODE (0xA041)
#define PROC_GNB_PCIE_PCIEINIT_FILECODE (0xA043)
#define PROC_GNB_PCIE_PCIEINITATEARLYPOST_FILECODE (0xA044)
#define PROC_GNB_PCIE_PCIEINITATLATEPOST_FILECODE (0xA045)
#define PROC_GNB_PCIE_PCIEINPUTPARSER_FILECODE (0xA046)
#define PROC_GNB_PCIE_PCIELATEINIT_FILECODE (0xA047)
#define PROC_GNB_PCIE_PCIEMAPTOPOLOGY_FILECODE (0xA048)
#define PROC_GNB_PCIE_PCIEPORTLATEINIT_FILECODE (0xA049)
#define PROC_GNB_PCIE_PCIEPIFSERVICES_FILECODE (0xA04A)
#define PROC_GNB_PCIE_PCIEPORTINIT_FILECODE (0xA04B)
#define PROC_GNB_PCIE_PCIEPORTREGACC_FILECODE (0xA04C)
#define PROC_GNB_PCIE_PCIETIMER_FILECODE (0xA04D)
#define PROC_GNB_PCIE_PCIETOPOLOGYSERVICES_FILECODE (0xA04E)
#define PROC_GNB_PCIE_PCIETRAINING_FILECODE (0xA04F)
#define PROC_GNB_PCIE_PCIEUTILITYLIB_FILECODE (0xA050)
#define PROC_GNB_PCIE_PCIEWRAPPERREGACC_FILECODE (0xA051)
#define PROC_GNB_PCIE_PCIEPOWERSAVINGFEATURES_FILECODE (0xA052)
#define PROC_GNB_PCIE_PCIESBLINK_FILECODE (0xA053)
#define PROC_GNB_PCIE_PCIEWORKAROUNDS_FILECODE (0xA054)
#define PROC_GNB_PCIE_FAMILY_0X12_F12PCIECOMPLEXCONFIG_FILECODE (0xA060)
#define PROC_GNB_PCIE_FAMILY_0X12_F12PCIECOMPLEXSERVICES_FILECODE (0xA061)
#define PROC_GNB_PCIE_FAMILY_0X12_F12PCIEPHYSERVICES_FILECODE (0xA062)
#define PROC_GNB_PCIE_FAMILY_0X12_F12PCIEWRAPPERSERVICES_FILECODE (0xA063)
#define PROC_GNB_PCIE_FAMILY_0X14_F14PCIECOMPLEXCONFIG_FILECODE (0xA070)
#define PROC_GNB_PCIE_FAMILY_0X14_F14PCIECOMPLEXSERVICES_FILECODE (0xA071)
#define PROC_GNB_PCIE_FAMILY_0X14_F14PCIEPHYSERVICES_FILECODE (0xA072)
#define PROC_GNB_PCIE_FAMILY_0X14_F14PCIEWRAPPERSERVICES_FILECODE (0xA073)
#define PROC_GNB_PCIE_FEATURE_PCIEASPM_FILECODE (0xA074)
#define PROC_GNB_PCIE_FEATURE_PCIEASPMEXITLATENCY_FILECODE (0xA075)
#define PROC_GNB_GFX_GFXPOWERPLAYTABLE_FILECODE (0xA076)
#define PROC_GNB_GFX_GFXFUSETABLEINIT_FILECODE (0xA077)
#define PROC_GNB_NB_NBPOWERMGMT_FILECODE (0xA078)
#define PROC_RECOVERY_GNB_GNBRECOVERY_FILECODE (0xAE01)
#define PROC_RECOVERY_GNB_GFXRECOVERY_FILECODE (0xAE02)
#define PROC_RECOVERY_GNB_NBINITRECOVERY_FILECODE (0xAE03)
#define LIB_AMDLIB_FILECODE (0xC001)
#define LEGACY_PROC_AGESACALLOUTS_FILECODE (0xC010)
#define LEGACY_PROC_HOBTRANSFER_FILECODE (0xC011)
#define LEGACY_PROC_DISPATCHER_FILECODE (0xC012)
#define UEFI_DXE_AMDAGESADXEDRIVER_AMDAGESADXEDRIVER_FILECODE (0xC120)
#define UEFI_DXE_AMDAGESAS3DRIVER_AMDAGESAS3DRIVER_FILECODE (0xC121)
#define UEFI_PEI_AMDINITPOSTPEIM_AMDINITPOSTPEIM_FILECODE (0xC140)
#define UEFI_PEI_AMDPROCESSORINITPEIM_AMDPROCESSORINITPEIM_FILECODE (0xC141)
#define UEFI_PEI_AMDRESETMANAGER_AMDRESETMANAGER_FILECODE (0xC142)
#define UEFI_PROC_HOBTRANSFERUEFI_FILECODE (0xC162)
#define PROC_COMMON_AMDINITEARLY_FILECODE (0xC020)
#define PROC_COMMON_AMDINITENV_FILECODE (0xC021)
#define PROC_COMMON_AMDINITLATE_FILECODE (0xC022)
#define PROC_COMMON_AMDINITMID_FILECODE (0xC023)
#define PROC_COMMON_AMDINITPOST_FILECODE (0xC024)
#define PROC_COMMON_AMDINITRECOVERY_FILECODE (0xC025)
#define PROC_COMMON_AMDINITRESET_FILECODE (0xC026)
#define PROC_COMMON_AMDINITRESUME_FILECODE (0xC027)
#define PROC_COMMON_AMDS3LATERESTORE_FILECODE (0xC028)
#define PROC_COMMON_AMDS3SAVE_FILECODE (0xC029)
#define PROC_COMMON_AMDLATERUNAPTASK_FILECODE (0xC02A)
#define PROC_COMMON_COMMONRETURNS_FILECODE (0xC0C0)
#define PROC_COMMON_CREATESTRUCT_FILECODE (0xC0D0)
#define PROC_COMMON_COMMONINITS_FILECODE (0xC0F0)
#define PROC_COMMON_S3RESTORESTATE_FILECODE (0xC0F8)
#define PROC_COMMON_S3SAVESTATE_FILECODE (0xC0F9)
#define PROC_CPU_CPUAPICUTILITIES_FILECODE (0xC401)
#define PROC_CPU_CPUBRANDID_FILECODE (0xC402)
#define PROC_CPU_TABLE_FILECODE (0xC403)
#define PROC_CPU_CPUEARLYINIT_FILECODE (0xC405)
#define PROC_CPU_CPUEVENTLOG_FILECODE (0xC406)
#define PROC_CPU_CPUFAMILYTRANSLATION_FILECODE (0xC407)
#define PROC_CPU_CPUGENERALSERVICES_FILECODE (0xC408)
#define PROC_CPU_CPUINITEARLYTABLE_FILECODE (0xC409)
#define PROC_CPU_CPULATEINIT_FILECODE (0xC40A)
#define PROC_CPU_CPUMICROCODEPATCH_FILECODE (0xC40B)
#define PROC_CPU_CPUWARMRESET_FILECODE (0xC40C)
#define PROC_CPU_HEAPMANAGER_FILECODE (0xC40D)
#define PROC_CPU_CPUBIST_FILECODE (0xC40E)
#define PROC_CPU_CPUPOSTINIT_FILECODE (0xC420)
#define PROC_CPU_CPUPOWERMGMT_FILECODE (0xC430)
#define PROC_CPU_CPUPOWERMGMTMULTISOCKET_FILECODE (0xC431)
#define PROC_CPU_CPUPOWERMGMTSINGLESOCKET_FILECODE (0xC432)
#define PROC_CPU_S3_FILECODE (0xC460)
#define PROC_CPU_FAMILY_0X10_CPUCOMMONF10UTILITIES_FILECODE (0xC801)
#define PROC_CPU_FAMILY_0X10_CPUF10BRANDID_FILECODE (0xC802)
#define PROC_CPU_FAMILY_0X10_CPUF10CACHEDEFAULTS_FILECODE (0xC803)
#define PROC_CPU_FAMILY_0X10_CPUF10CACHEFLUSHONHALT_FILECODE (0xC804)
#define PROC_CPU_FAMILY_0X10_CPUF10DMI_FILECODE (0xC805)
#define PROC_CPU_FAMILY_0X10_CPUF10EARLYINIT_FILECODE (0xC806)
#define PROC_CPU_FAMILY_0X10_CPUF10FEATURELEVELING_FILECODE (0xC807)
#define PROC_CPU_FAMILY_0X10_CPUF10HTPHYTABLES_FILECODE (0xC808)
#define PROC_CPU_FAMILY_0X10_CPUF10MSRTABLES_FILECODE (0xC809)
#define PROC_CPU_FAMILY_0X10_CPUF10PCITABLES_FILECODE (0xC80A)
#define PROC_CPU_FAMILY_0X10_CPUF10POWERCHECK_FILECODE (0xC80B)
#define PROC_CPU_FAMILY_0X10_CPUF10POWERMGMTSYSTEMTABLES_FILECODE (0xC80C)
#define PROC_CPU_FAMILY_0X10_CPUF10POWERPLANE_FILECODE (0xC80D)
#define PROC_CPU_FAMILY_0X10_CPUF10SOFTWARETHERMAL_FILECODE (0xC80E)
#define PROC_CPU_FAMILY_0X10_CPUF10UTILITIES_FILECODE (0xC80F)
#define PROC_CPU_FAMILY_0X10_CPUF10WHEAINITDATATABLES_FILECODE (0xC810)
#define PROC_CPU_FAMILY_0X10_CPUF10PSTATE_FILECODE (0xC827)
#define PROC_CPU_FAMILY_0X10_F10PMNBCOFVIDINIT_FILECODE (0xC811)
#define PROC_CPU_FAMILY_0X10_F10SINGLELINKPCITABLES_FILECODE (0xC812)
#define PROC_CPU_FAMILY_0X10_F10MULTILINKPCITABLES_FILECODE (0xC813)
#define PROC_CPU_FAMILY_0X10_F10PMNBPSTATEINIT_FILECODE (0xC814)
#define PROC_CPU_FAMILY_0X10_REVC_F10REVCUTILITIES_FILECODE (0xC815)
#define PROC_CPU_FAMILY_0X10_REVC_F10REVCHWC1E_FILECODE (0xC816)
#define PROC_CPU_FAMILY_0X10_REVC_F10REVCPCITABLES_FILECODE (0xC81A)
#define PROC_CPU_FAMILY_0X10_REVC_F10REVCMSRTABLES_FILECODE (0xC81B)
#define PROC_CPU_FAMILY_0X10_REVC_F10REVCHTPHYTABLES_FILECODE (0xC81C)
#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLHTPHYTABLES_FILECODE (0xC820)
#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLLOGICALIDTABLES_FILECODE (0xC821)
#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLMICROCODEPATCHTABLES_FILECODE (0xC822)
#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLMSRTABLES_FILECODE (0xC823)
#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLEQUIVALENCETABLE_FILECODE (0xC824)
#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLPCITABLES_FILECODE (0xC825)
#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLCACHEFLUSHONHALT_FILECODE (0xC826)
#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAHTPHYTABLES_FILECODE (0xC830)
#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DALOGICALIDTABLES_FILECODE (0xC831)
#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAMICROCODEPATCHTABLES_FILECODE (0xC832)
#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAMSRTABLES_FILECODE (0xC833)
#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAEQUIVALENCETABLE_FILECODE (0xC834)
#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAPCITABLES_FILECODE (0xC835)
#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DACACHEFLUSHONHALT_FILECODE (0xC836)
#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBHTPHYTABLES_FILECODE (0xC850)
#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBLOGICALIDTABLES_FILECODE (0xC851)
#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBMICROCODEPATCHTABLES_FILECODE (0xC852)
#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBMSRTABLES_FILECODE (0xC853)
#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBEQUIVALENCETABLE_FILECODE (0xC854)
#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBPCITABLES_FILECODE (0xC855)
#define PROC_CPU_FAMILY_0X10_REVD_F10REVDUTILITIES_FILECODE (0xC817)
#define PROC_CPU_FAMILY_0X10_REVD_F10REVDMSGBASEDC1E_FILECODE (0xC818)
#define PROC_CPU_FAMILY_0X10_REVD_F10REVDHTASSIST_FILECODE (0xC819)
#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYHTPHYTABLES_FILECODE (0xC840)
#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYINITEARLYTABLE_FILECODE (0xC841)
#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYLOGICALIDTABLES_FILECODE (0xC842)
#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYMICROCODEPATCHTABLES_FILECODE (0xC843)
#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYMSRTABLES_FILECODE (0xC844)
#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYEQUIVALENCETABLE_FILECODE (0xC845)
#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYPCITABLES_FILECODE (0xC846)
#define PROC_CPU_FAMILY_0X12_CPUCOMMONF12UTILITIES_FILECODE (0XC901)
#define PROC_CPU_FAMILY_0X12_CPUF12BRANDID_FILECODE (0XC902)
#define PROC_CPU_FAMILY_0X12_CPUF12CACHEDEFAULTS_FILECODE (0XC903)
#define PROC_CPU_FAMILY_0X12_CPUF12DMI_FILECODE (0XC904)
#define PROC_CPU_FAMILY_0X12_CPUF12MSRTABLES_FILECODE (0xC906)
#define PROC_CPU_FAMILY_0X12_CPUF12PCITABLES_FILECODE (0xC907)
#define PROC_CPU_FAMILY_0X12_CPUF12POWERCHECK_FILECODE (0XC908)
#define PROC_CPU_FAMILY_0X12_CPUF12POWERMGMTSYSTEMTABLES_FILECODE (0XC909)
#define PROC_CPU_FAMILY_0X12_CPUF12POWERPLANE_FILECODE (0XC90A)
#define PROC_CPU_FAMILY_0X12_CPUF12SOFTWARETHERMAL_FILECODE (0XC90B)
#define PROC_CPU_FAMILY_0X12_CPUF12UTILITIES_FILECODE (0XC90C)
#define PROC_CPU_FAMILY_0X12_CPUF12WHEAINITDATATABLES_FILECODE (0XC90D)
#define PROC_CPU_FAMILY_0X12_CPUF12PSTATE_FILECODE (0XC90E)
#define PROC_CPU_FAMILY_0X12_F12C6STATE_FILECODE (0XC90F)
#define PROC_CPU_FAMILY_0X12_LN_F12LNLOGICALIDTABLES_FILECODE (0xC921)
#define PROC_CPU_FAMILY_0X12_LN_F12LNMICROCODEPATCHTABLES_FILECODE (0xC922)
#define PROC_CPU_FAMILY_0X12_LN_F12LNEQUIVALENCETABLE_FILECODE (0xC923)
#define PROC_CPU_FAMILY_0X14_CPUCOMMONF14UTILITIES_FILECODE (0XCA01)
#define PROC_CPU_FAMILY_0X14_CPUF14BRANDID_FILECODE (0XCA02)
#define PROC_CPU_FAMILY_0X14_CPUF14CACHEDEFAULTS_FILECODE (0XCA03)
#define PROC_CPU_FAMILY_0X14_CPUF14DMI_FILECODE (0XCA04)
#define PROC_CPU_FAMILY_0X14_CPUF14MSRTABLES_FILECODE (0xCA06)
#define PROC_CPU_FAMILY_0X14_CPUF14PCITABLES_FILECODE (0xCA07)
#define PROC_CPU_FAMILY_0X14_CPUF14POWERCHECK_FILECODE (0XCA08)
#define PROC_CPU_FAMILY_0X14_CPUF14POWERMGMTSYSTEMTABLES_FILECODE (0XCA09)
#define PROC_CPU_FAMILY_0X14_CPUF14POWERPLANE_FILECODE (0XCA0A)
#define PROC_CPU_FAMILY_0X14_CPUF14SOFTWARETHERMAL_FILECODE (0XCA0B)
#define PROC_CPU_FAMILY_0X14_CPUF14UTILITIES_FILECODE (0XCA0C)
#define PROC_CPU_FAMILY_0X14_CPUF14WHEAINITDATATABLES_FILECODE (0XCA0D)
#define PROC_CPU_FAMILY_0X14_CPUF14PSTATE_FILECODE (0XCA0E)
#define PROC_CPU_FAMILY_0X14_ON_F14ONLOGICALIDTABLES_FILECODE (0xCA21)
#define PROC_CPU_FAMILY_0X14_ON_F14ONMICROCODEPATCHTABLES_FILECODE (0xCA22)
#define PROC_CPU_FAMILY_0X14_ON_F14ONMSRTABLES_FILECODE (0xCA23)
#define PROC_CPU_FAMILY_0X14_ON_F14ONEQUIVALENCETABLE_FILECODE (0xCA24)
#define PROC_CPU_FAMILY_0X14_ON_F14ONPCITABLES_FILECODE (0xCA25)
#define PROC_CPU_FEATURE_CPUCACHEFLUSHONHALT_FILECODE (0xDC01)
#define PROC_CPU_FEATURE_CPUCACHEINIT_FILECODE (0xDC02)
#define PROC_CPU_FEATURE_CPUDMI_FILECODE (0xDC10)
#define PROC_CPU_FEATURE_CPUFEATURELEVELING_FILECODE (0xDC20)
#define PROC_CPU_FEATURE_CPUHTASSIST_FILECODE (0xDC30)
#define PROC_CPU_FEATURE_CPUPSTATEGATHER_FILECODE (0xDC41)
#define PROC_CPU_FEATURE_CPUPSTATELEVELING_FILECODE (0xDC42)
#define PROC_CPU_FEATURE_CPUPSTATETABLES_FILECODE (0xDC43)
#define PROC_CPU_FEATURE_CPUSLIT_FILECODE (0xDC50)
#define PROC_CPU_FEATURE_CPUSRAT_FILECODE (0xDC60)
#define PROC_CPU_FEATURE_CPUWHEA_FILECODE (0xDC70)
#define PROC_CPU_FEATURE_CPUHWC1E_FILECODE (0xDC80)
#define PROC_CPU_FEATURE_CPUC6STATE_FILECODE (0xDC81)
#define PROC_CPU_FEATURE_CPUFEATURES_FILECODE (0xDC90)
#define PROC_CPU_FEATURE_CPUMSGBASEDC1E_FILECODE (0xDCA0)
#define PROC_CPU_FEATURE_CPUCORELEVELING_FILECODE (0xDCB0)
#define PROC_CPU_FEATURE_PRESERVEMAILBOX_FILECODE (0xDCC0)
#define PROC_RECOVERY_CPU_CPURECOVERY_FILECODE (0xDE01)
#define PROC_HT_FEATURES_HTFEATSETS_FILECODE (0xE001)
#define PROC_HT_FEATURES_HTFEATDYNAMICDISCOVERY_FILECODE (0xE002)
#define PROC_HT_FEATURES_HTFEATGANGING_FILECODE (0xE003)
#define PROC_HT_FEATURES_HTFEATNONCOHERENT_FILECODE (0xE004)
#define PROC_HT_FEATURES_HTFEATOPTIMIZATION_FILECODE (0xE005)
#define PROC_HT_FEATURES_HTFEATROUTING_FILECODE (0xE006)
#define PROC_HT_FEATURES_HTFEATSUBLINKS_FILECODE (0xE007)
#define PROC_HT_FEATURES_HTFEATTRAFFICDISTRIBUTION_FILECODE (0xE008)
#define PROC_HT_FEATURES_HTIDS_FILECODE (0xE009)
#define PROC_HT_HTFEAT_FILECODE (0xE021)
#define PROC_HT_HTINTERFACE_FILECODE (0xE022)
#define PROC_HT_HTINTERFACECOHERENT_FILECODE (0xE023)
#define PROC_HT_HTINTERFACEGENERAL_FILECODE (0xE024)
#define PROC_HT_HTINTERFACENONCOHERENT_FILECODE (0xE025)
#define PROC_HT_HTMAIN_FILECODE (0xE026)
#define PROC_HT_HTNOTIFY_FILECODE (0xE027)
#define PROC_HT_HTGRAPH_HTGRAPH_FILECODE (0xE028)
#define PROC_HT_HTNB_FILECODE (0xE081)
#define PROC_HT_NBCOMMON_HTNBCOHERENT_FILECODE (0xE082)
#define PROC_HT_NBCOMMON_HTNBNONCOHERENT_FILECODE (0xE083)
#define PROC_HT_NBCOMMON_HTNBOPTIMIZATION_FILECODE (0xE084)
#define PROC_HT_NBCOMMON_HTNBUTILITIES_FILECODE (0xE085)
#define PROC_HT_FAM10_HTNBFAM10_FILECODE (0xE0C1)
#define PROC_HT_FAM10_HTNBCOHERENTFAM10_FILECODE (0xE0C2)
#define PROC_HT_FAM10_HTNBNONCOHERENTFAM10_FILECODE (0xE0C3)
#define PROC_HT_FAM10_HTNBOPTIMIZATIONFAM10_FILECODE (0xE0C4)
#define PROC_HT_FAM10_HTNBSYSTEMFAM10_FILECODE (0xE0C5)
#define PROC_HT_FAM10_HTNBUTILITIESFAM10_FILECODE (0xE0C6)
#define PROC_HT_FAM12_HTNBFAM12_FILECODE (0xE101)
#define PROC_HT_FAM12_HTNBUTILITIESFAM12_FILECODE (0xE102)
#define PROC_HT_FAM14_HTNBFAM14_FILECODE (0xE141)
#define PROC_HT_FAM14_HTNBUTILITIESFAM14_FILECODE (0xE142)
#define PROC_RECOVERY_HT_HTINITRECOVERY_FILECODE (0xE302)
#define PROC_RECOVERY_HT_HTINITRESET_FILECODE (0xE301)
#define PROC_IDS_CONTROL_IDSCTRL_FILECODE (0xE801)
#define PROC_IDS_CONTROL_IDSLIB_FILECODE (0xE802)
#define PROC_IDS_DEBUG_IDSDEBUG_FILECODE (0xE803)
#define PROC_IDS_PERF_IDSPERF_FILECODE (0xE804)
#define PROC_IDS_FAMILY_0X10_IDSF10ALLSERVICE_FILECODE (0xE805)
#define PROC_IDS_FAMILY_0X10_BL_IDSF10BLSERVICE_FILECODE (0xE806)
#define PROC_IDS_FAMILY_0X10_DA_IDSF10DASERVICE_FILECODE (0xE807)
#define PROC_IDS_FAMILY_0X10_HY_IDSF10HYSERVICE_FILECODE (0xE808)
#define PROC_IDS_FAMILY_0X10_RB_IDSF10RBSERVICE_FILECODE (0xE809)
#define PROC_IDS_FAMILY_0X12_IDSF12ALLSERVICE_FILECODE (0xE80A)
#define PROC_IDS_FAMILY_0X14_IDSF14ALLSERVICE_FILECODE (0xE80B)
#define PROC_MEM_ARDK_MA_FILECODE (0xF001)
#define PROC_MEM_ARDK_DR_MARDR2_FILECODE (0xF002)
#define PROC_MEM_ARDK_DR_MARDR3_FILECODE (0xF003)
#define PROC_MEM_ARDK_HY_MARHY3_FILECODE (0xF004)
#define PROC_MEM_ARDK_LN_MASLN3_FILECODE (0xF005)
#define PROC_MEM_ARDK_DR_MAUDR3_FILECODE (0xF006)
#define PROC_MEM_ARDK_HY_MAUHY3_FILECODE (0xF007)
#define PROC_MEM_ARDK_LN_MAULN3_FILECODE (0xF008)
#define PROC_MEM_ARDK_DA_MAUDA3_FILECODE (0xF009)
#define PROC_MEM_ARDK_DA_MASDA2_FILECODE (0xF00A)
#define PROC_MEM_ARDK_DA_MASDA3_FILECODE (0xF00B)
#define PROC_MEM_ARDK_NI_MASNI3_FILECODE (0xF00C)
#define PROC_MEM_ARDK_C32_MARC32_3_FILECODE (0xF00D)
#define PROC_MEM_ARDK_C32_MAUC32_3_FILECODE (0xF00E)
#define PROC_MEM_ARDK_NI_MAUNI3_FILECODE (0xF00F)
#define PROC_MEM_ARDK_ON_MASON3_FILECODE (0xF010)
#define PROC_MEM_ARDK_ON_MAUON3_FILECODE (0xF011)
#define PROC_MEM_FEAT_CHINTLV_MFCHI_FILECODE (0xF081)
#define PROC_MEM_FEAT_CSINTLV_MFCSI_FILECODE (0xF082)
#define PROC_MEM_FEAT_ECC_MFECC_FILECODE (0xF083)
#define PROC_MEM_FEAT_ECC_MFEMP_FILECODE (0xF085)
#define PROC_MEM_FEAT_EXCLUDIMM_MFDIMMEXCLUD_FILECODE (0xF086)
#define PROC_MEM_FEAT_IDENDIMM_MFIDENDIMM_FILECODE (0xF088)
#define PROC_MEM_FEAT_INTLVRN_MFINTLVRN_FILECODE (0xF089)
#define PROC_MEM_FEAT_LVDDR3_MFLVDDR3_FILECODE (0xF08A)
#define PROC_MEM_FEAT_MEMCLR_MFMEMCLR_FILECODE (0xF08B)
#define PROC_MEM_FEAT_NDINTLV_MFNDI_FILECODE (0xF08C)
#define PROC_MEM_FEAT_ODTHERMAL_MFODTHERMAL_FILECODE (0xF08D)
#define PROC_MEM_FEAT_OLSPARE_MFSPR_FILECODE (0xF08E)
#define PROC_MEM_FEAT_PARTRN_MFPARALLELTRAINING_FILECODE (0xF08F)
#define PROC_MEM_FEAT_PARTRN_MFSTANDARDTRAINING_FILECODE (0xF091)
#define PROC_MEM_FEAT_S3_MFS3_FILECODE (0xF092)
#define PROC_MEM_FEAT_TABLE_MFTDS_FILECODE (0xF093)
#define PROC_MEM_MAIN_MDEF_FILECODE (0xF101)
#define PROC_MEM_MAIN_MINIT_FILECODE (0xF102)
#define PROC_MEM_MAIN_MM_FILECODE (0xF103)
#define PROC_MEM_FEAT_DMI_MFDMI_FILECODE (0xF104)
#define PROC_MEM_MAIN_MMECC_FILECODE (0xF105)
#define PROC_MEM_MAIN_MMEXCLUDEDIMM_FILECODE (0xF106)
#define PROC_MEM_MAIN_DR_MMFLOWDR_FILECODE (0xF107)
#define PROC_MEM_MAIN_HY_MMFLOWHY_FILECODE (0xF108)
#define PROC_MEM_MAIN_LN_MMFLOWLN_FILECODE (0xF109)
#define PROC_MEM_MAIN_ON_MMFLOWON_FILECODE (0xF10A)
#define PROC_MEM_MAIN_MMNODEINTERLEAVE_FILECODE (0xF10B)
#define PROC_MEM_MAIN_MMONLINESPARE_FILECODE (0xF10C)
#define PROC_MEM_MAIN_MMPARALLELTRAINING_FILECODE (0xF10D)
#define PROC_MEM_MAIN_MMSTANDARDTRAINING_FILECODE (0xF10E)
#define PROC_MEM_MAIN_MUC_FILECODE (0xF10F)
#define PROC_MEM_MAIN_MMMEMCLR_FILECODE (0xF110)
#define PROC_MEM_MAIN_DA_MMFLOWDA_FILECODE (0xF111)
#define PROC_MEM_MAIN_MMFLOW_FILECODE (0xF112)
#define PROC_MEM_MAIN_MERRHDL_FILECODE (0xF113)
#define PROC_MEM_MAIN_C32_MMFLOWC32_FILECODE (0xF114)
#define PROC_MEM_MAIN_MMLVDDR3_FILECODE (0xF115)
#define PROC_MEM_MAIN_MMUMAALLOC_FILECODE (0xF116)
#define PROC_MEM_MAIN_MMMEMRESTORE_FILECODE (0xF117)
#define PROC_MEM_MAIN_MMCONDITIONALPSO_FILECODE (0xF118)
#define PROC_MEM_NB_DR_MNDR_FILECODE (0XF213)
#define PROC_MEM_NB_DR_MNFLOWDR_FILECODE (0XF214)
#define PROC_MEM_NB_DR_MNIDENDIMMDR_FILECODE (0XF216)
#define PROC_MEM_NB_DR_MNMCTDR_FILECODE (0XF217)
#define PROC_MEM_NB_DR_MNDCTDR_FILECODE (0XF218)
#define PROC_MEM_NB_DR_MNOTDR_FILECODE (0XF219)
#define PROC_MEM_NB_DR_MNPARTRAINDR_FILECODE (0XF21A)
#define PROC_MEM_NB_DR_MNPROTODR_FILECODE (0XF21C)
#define PROC_MEM_NB_DR_MNS3DR_FILECODE (0XF21D)
#define PROC_MEM_NB_DR_MNREGDR_FILECODE (0XF21E)
#define PROC_MEM_NB_HY_MNFLOWHY_FILECODE (0XF233)
#define PROC_MEM_NB_HY_MNHY_FILECODE (0XF235)
#define PROC_MEM_NB_HY_MNIDENDIMMHY_FILECODE (0XF236)
#define PROC_MEM_NB_HY_MNMCTHY_FILECODE (0XF237)
#define PROC_MEM_NB_HY_MNDCTHY_FILECODE (0XF238)
#define PROC_MEM_NB_HY_MNOTHY_FILECODE (0XF239)
#define PROC_MEM_NB_HY_MNPARTRAINHY_FILECODE (0XF23A)
#define PROC_MEM_NB_HY_MNPHYHY_FILECODE (0XF23B)
#define PROC_MEM_NB_HY_MNPROTOHY_FILECODE (0XF23C)
#define PROC_MEM_NB_HY_MNS3HY_FILECODE (0XF23D)
#define PROC_MEM_NB_HY_MNREGHY_FILECODE (0XF23E)
#define PROC_MEM_NB_ON_MNON_FILECODE (0xF240)
#define PROC_MEM_NB_ON_MNREGON_FILECODE (0xF241)
#define PROC_MEM_NB_ON_MNDCTON_FILECODE (0xF242)
#define PROC_MEM_NB_ON_MNIDENDIMMON_FILECODE (0xF244)
#define PROC_MEM_NB_ON_MNMCTON_FILECODE (0xF245)
#define PROC_MEM_NB_ON_MNOTON_FILECODE (0xF246)
#define PROC_MEM_NB_ON_MNPHYON_FILECODE (0xF247)
#define PROC_MEM_NB_ON_MNS3ON_FILECODE (0xF248)
#define PROC_MEM_NB_ON_MNFLOWON_FILECODE (0xF249)
#define PROC_MEM_NB_LN_MNDCTLN_FILECODE (0XF252)
#define PROC_MEM_NB_LN_MNFLOWLN_FILECODE (0XF253)
#define PROC_MEM_NB_LN_MNIDENDIMMLN_FILECODE (0XF254)
#define PROC_MEM_NB_LN_MNMCTLN_FILECODE (0XF255)
#define PROC_MEM_NB_LN_MNOTLN_FILECODE (0XF256)
#define PROC_MEM_NB_LN_MNPHYLN_FILECODE (0XF257)
#define PROC_MEM_NB_LN_MNPROTOLN_FILECODE (0XF258)
#define PROC_MEM_NB_LN_MNLN_FILECODE (0XF259)
#define PROC_MEM_NB_LN_MNS3LN_FILECODE (0XF25A)
#define PROC_MEM_NB_LN_MNREGLN_FILECODE (0XF25B)
#define PROC_MEM_NB_DA_MNDA_FILECODE (0XF260)
#define PROC_MEM_NB_DA_MNFLOWDA_FILECODE (0XF261)
#define PROC_MEM_NB_DA_MNIDENDIMMDA_FILECODE (0XF263)
#define PROC_MEM_NB_DA_MNMCTDA_FILECODE (0XF264)
#define PROC_MEM_NB_DA_MNDCTDA_FILECODE (0XF265)
#define PROC_MEM_NB_DA_MNOTDA_FILECODE (0XF266)
#define PROC_MEM_NB_DA_MNPARTRAINDA_FILECODE (0XF267)
#define PROC_MEM_NB_DA_MNPROTODA_FILECODE (0XF269)
#define PROC_MEM_NB_DA_MNS3DA_FILECODE (0XF26A)
#define PROC_MEM_NB_DA_MNREGDA_FILECODE (0XF26B)
#define PROC_MEM_NB_C32_MNC32_FILECODE (0XF26C)
#define PROC_MEM_NB_C32_MNDCTC32_FILECODE (0XF26D)
#define PROC_MEM_NB_C32_MNFLOWC32_FILECODE (0XF26E)
#define PROC_MEM_NB_C32_MNIDENDIMMC32_FILECODE (0XF26F)
#define PROC_MEM_NB_C32_MNMCTC32_FILECODE (0XF270)
#define PROC_MEM_NB_C32_MNOTC32_FILECODE (0XF271)
#define PROC_MEM_NB_C32_MNPARTRAINC32_FILECODE (0XF272)
#define PROC_MEM_NB_C32_MNPHYC32_FILECODE (0XF273)
#define PROC_MEM_NB_C32_MNPROTOC32_FILECODE (0XF274)
#define PROC_MEM_NB_C32_MNS3C32_FILECODE (0XF275)
#define PROC_MEM_NB_C32_MNREGC32_FILECODE (0XF277)
#define PROC_MEM_NB_MN_FILECODE (0XF27C)
#define PROC_MEM_NB_MNDCT_FILECODE (0XF27D)
#define PROC_MEM_NB_MNPHY_FILECODE (0XF27E)
#define PROC_MEM_NB_MNMCT_FILECODE (0XF27F)
#define PROC_MEM_NB_MNS3_FILECODE (0XF280)
#define PROC_MEM_NB_MNFLOW_FILECODE (0XF281)
#define PROC_MEM_NB_MNFEAT_FILECODE (0XF282)
#define PROC_MEM_NB_MNTRAIN2_FILECODE (0XF283)
#define PROC_MEM_NB_MNTRAIN3_FILECODE (0XF284)
#define PROC_MEM_NB_MNREG_FILECODE (0XF285)
#define PROC_MEM_NB_NI_MNNI_FILECODE (0XF286)
#define PROC_MEM_NB_NI_MNS3NI_FILECODE (0XF287)
#define PROC_MEM_PS_MP_FILECODE (0XF401)
#define PROC_MEM_PS_DR_MPRDR3_FILECODE (0XF402)
#define PROC_MEM_PS_HY_MPRHY3_FILECODE (0XF403)
#define PROC_MEM_PS_LN_MPRLN3_FILECODE (0XF404)
#define PROC_MEM_PS_DR_MPSDR3_FILECODE (0XF405)
#define PROC_MEM_PS_HY_MPSHY3_FILECODE (0XF406)
#define PROC_MEM_PS_LN_MPSLN3_FILECODE (0XF407)
#define PROC_MEM_PS_DR_MPUDR3_FILECODE (0XF408)
#define PROC_MEM_PS_HY_MPUHY3_FILECODE (0XF409)
#define PROC_MEM_PS_LN_MPULN3_FILECODE (0XF40A)
#define PROC_MEM_PS_DA_MPUDA3_FILECODE (0XF40B)
#define PROC_MEM_PS_DA_MPSDA2_FILECODE (0XF40C)
#define PROC_MEM_PS_DA_MPSDA3_FILECODE (0XF40D)
#define PROC_MEM_PS_DR_MPRDR2_FILECODE (0XF40E)
#define PROC_MEM_PS_DR_MPUDR2_FILECODE (0XF40F)
#define PROC_MEM_PS_C32_MPRC32_3_FILECODE (0XF410)
#define PROC_MEM_PS_C32_MPUC32_3_FILECODE (0XF411)
#define PROC_MEM_PS_NI_MPSNI3_FILECODE (0XF412)
#define PROC_MEM_PS_NI_MPUNI3_FILECODE (0XF413)
#define PROC_MEM_PS_ON_MPSON3_FILECODE (0XF414)
#define PROC_MEM_PS_ON_MPUON3_FILECODE (0XF415)
#define PROC_MEM_TECH_MT_FILECODE (0XF501)
#define PROC_MEM_TECH_MTHDI_FILECODE (0XF502)
#define PROC_MEM_TECH_MTTDIMBT_FILECODE (0XF504)
#define PROC_MEM_TECH_MTTECC_FILECODE (0XF505)
#define PROC_MEM_TECH_MTTHRC_FILECODE (0XF506)
#define PROC_MEM_TECH_MTTML_FILECODE (0XF507)
#define PROC_MEM_TECH_MTTOPTSRC_FILECODE (0XF509)
#define PROC_MEM_TECH_MTTSRC_FILECODE (0XF50B)
#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE (0XF50C)
#define PROC_MEM_TECH_DDR2_MT2_FILECODE (0XF541)
#define PROC_MEM_TECH_DDR2_MTOT2_FILECODE (0XF543)
#define PROC_MEM_TECH_DDR2_MTSPD2_FILECODE (0XF544)
#define PROC_MEM_TECH_DDR3_MT3_FILECODE (0XF581)
#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE (0XF583)
#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE (0XF584)
#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE (0XF585)
#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE (0XF586)
#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE (0XF587)
#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE (0XF588)
#define PROC_RECOVERY_MEM_MRDEF_FILECODE (0XF801)
#define PROC_RECOVERY_MEM_MRINIT_FILECODE (0XF802)
#define PROC_RECOVERY_MEM_MRM_FILECODE (0XF803)
#define PROC_RECOVERY_MEM_MRUC_FILECODE (0XF804)
#define PROC_RECOVERY_MEM_NB_DR_MRNDR_FILECODE (0XF812)
#define PROC_RECOVERY_MEM_NB_DR_MRNMCTDR_FILECODE (0XF813)
#define PROC_RECOVERY_MEM_NB_HY_MRNDCTHY_FILECODE (0XF821)
#define PROC_RECOVERY_MEM_NB_HY_MRNHY_FILECODE (0XF822)
#define PROC_RECOVERY_MEM_NB_HY_MRNMCTHY_FILECODE (0XF823)
#define PROC_RECOVERY_MEM_NB_HY_MRNPROTOHY_FILECODE (0XF825)
#define PROC_RECOVERY_MEM_NB_LN_MRNDCTLN_FILECODE (0XF831)
#define PROC_RECOVERY_MEM_NB_LN_MRNMCTLN_FILECODE (0XF832)
#define PROC_RECOVERY_MEM_NB_LN_MRNLN_FILECODE (0XF833)
#define PROC_RECOVERY_MEM_NB_DA_MRNDA_FILECODE (0XF842)
#define PROC_RECOVERY_MEM_NB_DA_MRNMCTDA_FILECODE (0XF843)
#define PROC_RECOVERY_MEM_NB_NI_MRNNI_FILECODE (0XF845)
#define PROC_RECOVERY_MEM_NB_C32_MRNC32_FILECODE (0XF851)
#define PROC_RECOVERY_MEM_NB_C32_MRNMCTC32_FILECODE (0XF852)
#define PROC_RECOVERY_MEM_NB_C32_MRNPROTOC32_FILECODE (0XF853)
#define PROC_RECOVERY_MEM_NB_ON_MRNDCTON_FILECODE (0xF861)
#define PROC_RECOVERY_MEM_NB_ON_MRNMCTON_FILECODE (0xF862)
#define PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE (0xF863)
#define PROC_RECOVERY_MEM_TECH_MRTTPOS_FILECODE (0XF8C1)
#define PROC_RECOVERY_MEM_TECH_MRTTSRC_FILECODE (0XF8C2)
#define PROC_RECOVERY_MEM_TECH_DDR3_MRT3_FILECODE (0XF8C3)
#define PROC_RECOVERY_MEM_TECH_DDR3_MRTRCI3_FILECODE (0XF8C4)
#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSDI3_FILECODE (0XF8C5)
#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSPD3_FILECODE (0XF8C6)
#define PROC_RECOVERY_MEM_TECH_DDR3_MRTTWL3_FILECODE (0XF8C7)
#define PROC_RECOVERY_MEM_NB_MRN_FILECODE (0XF8C8)
#define PROC_RECOVERY_MEM_NB_MRNDCT_FILECODE (0XF8C9)
#define PROC_RECOVERY_MEM_NB_MRNMCT_FILECODE (0XF8CA)
#define PROC_RECOVERY_MEM_NB_MRNTRAIN3_FILECODE (0XF8CB)
#endif // _FILECODE_H_

200
src/vendorcode/amd/agesa/f10/Include/GeneralServices.h
View File

@ -1,200 +0,0 @@
/**
* @file
*
* General Services
*
* Provides Services similar to the external General Services API, except
* suited to use within AGESA components. Socket, Core and PCI identification.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Common
* @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef _GENERAL_SERVICES_H_
#define _GENERAL_SERVICES_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
#define NUMBER_OF_EVENT_DATA_PARAMS 4
/**
* AMD Device id for MMIO check.
*/
#define AMD_DEV_VEN_ID 0x1022
#define AMD_DEV_VEN_ID_ADDRESS 0
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
/**
* An AGESA Event Log entry.
*/
typedef struct {
AGESA_STATUS EventClass; ///< The severity of the event, its associated AGESA_STATUS.
UINT32 EventInfo; ///< Uniquely identifies the event.
UINT32 DataParam1; ///< Event specific additional data
UINT32 DataParam2; ///< Event specific additional data
UINT32 DataParam3; ///< Event specific additional data
UINT32 DataParam4; ///< Event specific additional data
} AGESA_EVENT;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
/**
* Get a specified Core's APIC ID.
*
* @param[in] StdHeader Header for library and services.
* @param[in] Socket The Core's Socket.
* @param[in] Core The Core id.
* @param[out] ApicAddress The Core's APIC ID.
* @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds.
*
* @retval TRUE The core is present, APIC Id valid
* @retval FALSE The core is not present, APIC Id not valid.
*/
BOOLEAN
GetApicId (
IN AMD_CONFIG_PARAMS *StdHeader,
IN UINT32 Socket,
IN UINT32 Core,
OUT UINT8 *ApicAddress,
OUT AGESA_STATUS *AgesaStatus
);
/**
* Get Processor Module's PCI Config Space address.
*
* @param[in] StdHeader Header for library and services.
* @param[in] Socket The Core's Socket.
* @param[in] Module The Module in that Processor
* @param[out] PciAddress The Processor's PCI Config Space address (Function 0, Register 0)
* @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds.
*
* @retval TRUE The core is present, PCI Address valid
* @retval FALSE The core is not present, PCI Address not valid.
*/
BOOLEAN
GetPciAddress (
IN AMD_CONFIG_PARAMS *StdHeader,
IN UINT32 Socket,
IN UINT32 Module,
OUT PCI_ADDR *PciAddress,
OUT AGESA_STATUS *AgesaStatus
);
/**
* "Who am I" for the current running core.
*
* @param[in] StdHeader Header for library and services.
* @param[out] Socket The current Core's Socket
* @param[out] Module The current Core's Processor Module
* @param[out] Core The current Core's core id.
* @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds.
*
*/
VOID
IdentifyCore (
IN AMD_CONFIG_PARAMS *StdHeader,
OUT UINT32 *Socket,
OUT UINT32 *Module,
OUT UINT32 *Core,
OUT AGESA_STATUS *AgesaStatus
);
/**
* A boolean function determine executed CPU is BSP core.
*/
BOOLEAN
IsBsp (
IN OUT AMD_CONFIG_PARAMS *StdHeader,
OUT AGESA_STATUS *AgesaStatus
);
/**
* This function logs AGESA events into the event log.
*/
VOID
PutEventLog (
IN AGESA_STATUS EventClass,
IN UINT32 EventInfo,
IN UINT32 DataParam1,
IN UINT32 DataParam2,
IN UINT32 DataParam3,
IN UINT32 DataParam4,
IN AMD_CONFIG_PARAMS *StdHeader
);
/**
* This function gets event logs from the circular buffer.
*/
AGESA_STATUS
GetEventLog (
OUT AGESA_EVENT *EventRecord,
IN AMD_CONFIG_PARAMS *StdHeader
);
/**
* This function gets event logs from the circular buffer without flushing the entry.
*/
BOOLEAN
PeekEventLog (
OUT AGESA_EVENT *EventRecord,
IN UINT16 Index,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*---------------------------------------------------------------------------------------*/
/**
* This routine programs the registers necessary to get the PCI MMIO mechanism
* up and functioning.
*/
VOID
InitializePciMmio (
IN AMD_CONFIG_PARAMS *StdHeader
);
#endif // _GENERAL_SERVICES_H_

87
src/vendorcode/amd/agesa/f10/Include/GnbInterface.h
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@ -1,87 +0,0 @@
/**
* @file
*
* GNB API definition.
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: GNB
* @e \$Revision: 20270 $ @e \$Date: 2009-10-09 10:09:20 -0700 (Fri, 09 Oct 2009) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _GNBINTERFACE_H_
#define _GNBINTERFACE_H_
AGESA_STATUS
GnbInitAtReset (
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
GnbInitAtEarly (
IN AMD_CONFIG_PARAMS *StdHeader,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN GNB_CONFIGURATION *GnbConfig
);
AGESA_STATUS
GnbInitAtPost (
IN AMD_CONFIG_PARAMS *StdHeader,
IN OUT MEM_PARAMETER_STRUCT *MemConfig
);
AGESA_STATUS
GnbInitAtEnv (
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
GnbInitAtMid (
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
GnbInitAtLate (
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
AmdGnbRecovery (
IN AMD_CONFIG_PARAMS *StdHeader
);
#endif

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@ -1,202 +0,0 @@
/**
* @file
*
*
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: GNB
* @e \$Revision: 20379 $ @e \$Date: 2009-10-12 23:41:06 -0700 (Mon, 12 Oct 2009) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------*/
/**
* Init GNB at Reset Stub
*
*
*
* @param[in] StdHeader Standard configuration header
* @retval AGESA_STATUS Always succeeds
*/
AGESA_STATUS
GnbInitAtReset (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------*/
/**
* Init GNB at Early Stub
*
*
*
* @param[in] StdHeader Standard configuration header
* @param[in] PlatformConfig Platform configuration
* @param[in] GnbConfig Gnb configuration
* @retval AGESA_STATUS Always succeeds
*/
AGESA_STATUS
GnbInitAtEarly (
IN AMD_CONFIG_PARAMS *StdHeader,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN GNB_CONFIGURATION *GnbConfig
)
{
return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------*/
/**
* Init GNB at Env
*
*
*
* @param[in] StdHeader Standard configuration header
* @retval AGESA_STATUS Always succeeds
*/
AGESA_STATUS
GnbInitAtEnv (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------*/
/**
* Init GNB at Reset
*
*
*
* @param[in] StdHeader Standard configuration header
* @param[in,out] MemConfig Memory configuration
* @retval AGESA_STATUS Always succeeds
*/
AGESA_STATUS
GnbInitAtPost (
IN AMD_CONFIG_PARAMS *StdHeader,
IN OUT MEM_PARAMETER_STRUCT *MemConfig
)
{
return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------*/
/**
* Init GNB at Mid post
*
*
*
* @param[in] StdHeader Standard configuration header
* @retval AGESA_STATUS Always succeeds
*/
AGESA_STATUS
GnbInitAtMid (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------*/
/**
* Init GNB at Late post
*
*
*
* @param[in] StdHeader Standard configuration header
* @retval AGESA_STATUS Always succeeds
*/
AGESA_STATUS
GnbInitAtLate (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------*/
/**
* AmdGnbRecovery
*
*
*
* @param[in] StdHeader Standard configuration header
* @retval AGESA_STATUS Always succeeds
*/
AGESA_STATUS
AmdGnbRecovery (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
return AGESA_SUCCESS;
}

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@ -1,791 +0,0 @@
/**
* @file
*
* AMD IDS Routines
*
* Contains AMD AGESA Integrated Debug Macros
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: IDS
* @e \$Revision: $ @e \$Date: 2008-04-07 15:08:45 -0500 (Mon, 07 Apr 2008) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
/* Macros to aid debugging */
/* These definitions expand to zero (0) bytes of code when disabled */
#ifndef _IDS_H_
#define _IDS_H_
#undef FALSE
#undef TRUE
#define FALSE 0
#define TRUE 1
// Proto type for optionsids.h
typedef UINT32 IDS_STATUS; ///< Status of IDS function.
#define IDS_SUCCESS ((IDS_STATUS) 0x00000000) ///< IDS Function is Successful.
#define IDS_UNSUPPORTED ((IDS_STATUS) 0xFFFFFFFF) ///< IDS Function is not existed.
#define IDS_STRINGIZE(a) #a ///< for define stringize macro
/**
* IDS Option Hook Points
*
* These are the values to indicate hook point in AGESA for IDS Options.
*
*/
typedef enum { //vv- for debug reference only
IDS_INIT_EARLY_BEFORE, ///< 00 Option Hook Point before AGESA function AMD_INIT_EARLY.
///< IDS Object is initialized.
///< Override CPU Core Leveling Mode.
///< Set P-State in Post
IDS_INIT_EARLY_AFTER, ///< 01 Option Hook Point after AGESA function AMD_INIT_EARLY.
IDS_INIT_LATE_BEFORE, ///< 02 Option Hook Point before AGESA function AMD_INIT_LATE.
///< It will be used to control the following tables.
///< ACPI P-State Table (_PSS, XPSS, _PCT, _PSD, _PPC)
///< ACPI SRAT Table
///< ACPI SLIT Table
///< ACPI WHEA Table
///< DMI Table
IDS_INIT_LATE_AFTER, ///< 03 Option Hook Point after AGESA function AMD_INIT_LATE.
IDS_INIT_MID_BEFORE, ///< 04 Option Hook Point before AGESA function AMD_INIT_MID.
IDS_INIT_MID_AFTER, ///< 05 Option Hook Point after AGESA function AMD_INIT_MID.
IDS_INIT_POST_BEFORE, ///< 06 Option Hook Point before AGESA function AMD_INIT_POST.
///< Control Interleaving and DRAM memory hole
///< Override the setting of ECC Control
///< Override the setting of Online Spare Rank
IDS_INIT_POST_AFTER, ///< 07 Option Hook Point after AGESA function AMD_INIT_POST.
IDS_INIT_RESET_BEFORE, ///< 08 Option Hook Point before AGESA function AMD_INIT_RESET.
IDS_INIT_RESET_AFTER, ///< 09 Option Hook Point after AGESA function AMD_INIT_RESET.
IDS_INIT_POST_MID, ///< 0a Option Hook Point after AGESA function AMD_INIT_POST.
IDS_BEFORE_S3_SAVE, ///< 0b override any settings before S3 save.
IDS_BEFORE_S3_RESTORE, ///< 0c override any settings before S3 restore
IDS_AFTER_S3_SAVE, ///< 0d Override any settings after S3 save
IDS_AFTER_S3_RESTORE, ///< 0e Override any settings after S3 restore
IDS_BEFORE_DQS_TRAINING, ///< 0f override any settings before DQS training
IDS_BEFORE_DRAM_INIT, ///< 10 override any settings before Dram initialization
IDS_BEFORE_MEM_FREQ_CHG, ///< 11 override settings before MemClk frequency change
IDS_AFTER_WARM_RESET , ///< 12 Override PCI or MSR Registers Before Warm Reset
IDS_BEFORE_MEM_INIT, ///< 13 Override PCI or MSR Registers Before Memory Init
IDS_BEFORE_PCI_INIT, ///< 14 Override PCI or MSR Registers Before PCI Init
IDS_BEFORE_OS, ///< 15 Override PCI or MSR Registers Before booting to OS
IDS_UCODE, ///< 16 Enable or Disable microcode patching
IDS_PLATFORM_RSVD1 = 0x38, ///< from 0x38 to 0x3f will reserved for platform used
IDS_PLATFORM_RSVD2 = 0x39, ///< from 0x38 to 0x3f will reserved for platform used
IDS_PLATFORM_RSVD3 = 0x3a, ///< from 0x38 to 0x3f will reserved for platform used
IDS_PLATFORM_RSVD4 = 0x3b, ///< from 0x38 to 0x3f will reserved for platform used
IDS_PLATFORM_RSVD5 = 0x3c, ///< from 0x38 to 0x3f will reserved for platform used
IDS_PLATFORM_RSVD6 = 0x3d, ///< from 0x38 to 0x3f will reserved for platform used
IDS_PLATFORM_RSVD7 = 0x3e, ///< from 0x38 to 0x3f will reserved for platform used
IDS_PLATFORM_RSVD8 = 0x3f, ///< from 0x38 to 0x3f will reserved for platform used
// All the above timing point is used by BVM, their value should never be changed
IDS_HT_CONTROL, ///< 40 Override the setting of HT Link Control
IDS_HT_TRISTATE, ///< 41 Enable or Disable HT Tri-state during an LDTSTP#
IDS_INIT_DRAM_TABLE, ///< 42 Generate override table for Dram Timing
///< Dram Controller, Drive Strength and DQS Timing
IDS_GET_DRAM_TABLE, ///< 43 Generate override table for Dram Timing
IDS_GANGING_MODE, ///< 44 override Memory Mode Unganged
IDS_POWERDOWN_MODE, ///< 45 override Power Down Mode
IDS_BURST_LENGTH32, ///< 46 override Burst Length32
IDS_ALL_MEMORY_CLOCK, ///< 47 override All Memory Clks Enable
IDS_ECC, ///< 48 override ECC parameter
IDS_ECCSYMBOLSIZE, ///< 49 override ECC symbol size
IDS_CPU_Early_Override, ///< 4a override CPU early parameter
IDS_CACHE_FLUSH_HLT, ///< 4b override Cache Flush Hlt
IDS_CHANNEL_INTERLEAVE, ///< 4c override Channel Interleave
IDS_MEM_ERROR_RECOVERY, ///< 4d override memory error recovery
IDS_MEM_RETRAIN_TIMES, ///< 4e override memory retrain times
IDS_MEM_SIZE_OVERLAY, ///< 4f Override the syslimit
IDS_HT_ASSIST, ///< 50 Override Probe Filter
IDS_CHECK_NEGATIVE_WL, ///< 51 Check for negative write leveling result
IDS_DLL_SHUT_DOWN, ///< 52 Check for Dll Shut Down
IDS_POR_MEM_FREQ, ///< 53 Entry to enable/disable MemClk frequency enforcement
IDS_PHY_DLL_STANDBY_CNTRL, ///< 54 Enable/Disable Phy DLL standby feature
IDS_PLATFORMCFG_OVERRIDE, ///< 55 Hook for Override PlatformConfig structure
IDS_LOADCARD_ERROR_RECOVERY, ///< 56 Special error handling for load card support
IDS_MEM_IGNORE_ERROR, ///< 57 Ignore error and do not do fatal exit in memory
IDS_GNB_PPFUSE_OVERRIDE, ///< 58 override GNB default PowerPlay fuse table
IDS_GNB_INTEGRATED_TABLE_CONFIG, ///<59 override GNB integrated table config
IDS_GNB_SMU_SERVICE_CONFIG, ///< 5a Config GNB SMU service
IDS_GNB_PCIE_PLATFORM_CONFIG, ///< 5b Config PCIE platform
IDS_GNB_ORBDYNAMIC_WAKE, ///< 5c config GNB dynamic wake
IDS_GNB_PLATFORMCFG_OVERRIDE ///< 5d override ids gnb platform config
} AGESA_IDS_OPTION;
#include "OptionsIds.h"
#include "Filecode.h"
/* Initialize IDS controls */
#ifndef IDSOPT_IDS_ENABLED
#define IDSOPT_IDS_ENABLED FALSE
#endif
#ifndef IDSOPT_CONTROL_ENABLED
#define IDSOPT_CONTROL_ENABLED FALSE
#endif
#ifndef IDSOPT_TRACING_ENABLED
#define IDSOPT_TRACING_ENABLED FALSE
#endif
#ifndef IDSOPT_PERF_ANALYSIS
#define IDSOPT_PERF_ANALYSIS FALSE
#endif
#ifndef IDSOPT_HEAP_CHECKING
#define IDSOPT_HEAP_CHECKING FALSE
#endif
#ifndef IDSOPT_ASSERT_ENABLED
#define IDSOPT_ASSERT_ENABLED FALSE
#endif
#ifndef IDSOPT_ERROR_TRAP_ENABLED
#define IDSOPT_ERROR_TRAP_ENABLED FALSE
#endif
#ifndef IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
#define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE
#endif
#if IDSOPT_IDS_ENABLED == FALSE
#undef IDSOPT_CONTROL_ENABLED
#undef IDSOPT_TRACING_ENABLED
#undef IDSOPT_PERF_ANALYSIS
#undef IDSOPT_HEAP_CHECKING
#undef IDSOPT_ASSERT_ENABLED
#undef IDSOPT_ERROR_TRAP_ENABLED
#undef IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
#define IDSOPT_CONTROL_ENABLED FALSE
#define IDSOPT_TRACING_ENABLED FALSE
#define IDSOPT_PERF_ANALYSIS FALSE
#define IDSOPT_HEAP_CHECKING FALSE
#define IDSOPT_ASSERT_ENABLED FALSE
#define IDSOPT_ERROR_TRAP_ENABLED FALSE
#define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE
#endif
/**
* Make a Progress Report to the User.
*
* This Macro is always enabled. The default action is to write the TestPoint value
* to an I/O port. The I/O port is 8 bits in size and the default address is 0x80.
* IBVs can change AGESA's default port by defining IDS_DEBUG_PORT to desired port
* in OptionsIds.h in their build tip.
*
* @param[in] TestPoint The value for display indicating progress
* @param[in,out] StdHeader Pointer of AMD_CONFIG_PARAMS
*
**/
#define AGESA_TESTPOINT(TestPoint, StdHeader) IdsAgesaTestPoint ((TestPoint), (StdHeader))
#ifndef IDS_DEBUG_PORT
#define IDS_DEBUG_PORT 0x80
#endif
/**
* @def STOP_HERE
* (macro) - Causes program to halt. This is @b only for use during active debugging .
*
* Causes the program to halt and display the file number of the source of the
* halt (displayed in decimal).
*
**/
#if IDSOPT_IDS_ENABLED == TRUE
#ifdef STOP_CODE
#undef STOP_CODE
#endif
#define STOP_CODE (((UINT32)FILECODE)*0x10000 + \
((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
(((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
#define STOP_HERE IdsErrorStop (STOP_CODE);
#else
#define STOP_HERE STOP_HERE_Needs_To_Be_Removed //"WARNING: Debug code needs to be removed for production builds."
#endif
/**
* @def ASSERT
* Test an assertion that the given statement is True.
*
* The statement is evaluated to a boolean value. If the statement is True,
* then no action is taken (no error). If the statement is False, a error stop
* is generated to halt the program. Used for testing for fatal errors that
* must be resolved before production. This is used to do parameter checks,
* bounds checking, range checks and 'sanity' checks.
*
* @param[in] conditional Assert that evaluating this conditional results in TRUE.
*
**/
#ifndef ASSERT
#if IDSOPT_ASSERT_ENABLED == TRUE
#ifdef STOP_CODE
#undef STOP_CODE
#endif
#define STOP_CODE (((UINT32)FILECODE)*0x10000 + \
((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
(((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
#define ASSERT(conditional) ((conditional) ? 0 : IdsErrorStop (STOP_CODE));
#else
#define ASSERT(conditional)
#endif
#endif
#if IDSOPT_CAR_CORRUPTION_CHECK_ENABLED == TRUE
#undef IDSOPT_ERROR_TRAP_ENABLED
#define IDSOPT_ERROR_TRAP_ENABLED TRUE
#define IDS_CAR_CORRUPTION_CHECK(StdHeader) //IdsCarCorruptionCheck(StdHeader)
#else
#define IDS_CAR_CORRUPTION_CHECK(StdHeader)
#endif
/**
* @def IDS_ERROR_TRAP
* Trap AGESA Error events with stop code display.
*
* Works similarly to use of "ASSERT (FALSE);"
*
*/
#if IDSOPT_ERROR_TRAP_ENABLED == TRUE
#ifdef STOP_CODE
#undef STOP_CODE
#endif
#define STOP_CODE (((UINT32)FILECODE)*0x10000 + \
((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
(((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
#define IDS_ERROR_TRAP IdsErrorStop (STOP_CODE)
#else
#define IDS_ERROR_TRAP
#endif
///give the extended Macro default value
#ifndef __IDS_EXTENDED__
#define IDS_EXTENDED_HOOK(idsoption, dataptr, idsnvptr, stdheader) IDS_SUCCESS
#define IDS_INITIAL_F10_PM_STEP
#define IDS_EXTENDED_GET_DATA_EARLY(data, StdHeader)
#define IDS_EXTENDED_GET_DATA_LATE(data, StdHeader)
#define IDS_EXTENDED_HEAP_SIZE 0
#define IDS_EXT_INCLUDE_F10(file)
#define IDS_EXT_INCLUDE(file)
#endif
#ifndef IDS_NUM_NV_ITEM
#define IDS_NUM_NV_ITEM (IDS_NUM_EXT_NV_ITEM)
#endif
#if IDSOPT_CONTROL_ENABLED == TRUE
#define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader) \
AmdIdsCtrlDispatcher ((IdsOption), (DataPtr), (StdHeader))
#else
#define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader)
#endif
/**
* Macro to add a *skip* hook for IDS options
*
* The default minimal action is to do nothing and there is no any code to increase.
* For debug environments, IDS dispatcher function will be called to perform
* the detailed action and to skip AGESA code if necessary.
*
* @param[in] IdsOption IDS Option ID for this hook point
* @param[in, out] DataPtr Data Pointer to override
* @param[in, out] StdHeader Pointer of AMD_CONFIG_PARAMS
*
*
**/
#if IDSOPT_CONTROL_ENABLED == TRUE
#define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader) \
if (AmdIdsCtrlDispatcher (IdsOption, DataPtr, StdHeader) == IDS_SUCCESS)
#else
#define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader)
#endif
/**
* Macro to add a heap manager routine
*
* when memory is allocated the heap manager actually allocates two extra dwords of data,
* one dword buffer before the actual memory, and one dword afterwards.
* a complete heap walk and check to be performed at any time.
* it would ASSERT if the heap is corrupt
*
* @param[in] StdHeader Pointer of AMD_CONFIG_PARAMS
*
*
**/
// Heap debug feature
#if IDSOPT_IDS_ENABLED == TRUE
#if IDSOPT_HEAP_CHECKING == TRUE
#define SIZE_OF_SENTINEL 4
#define SENTINEL_BEFORE_VALUE 0xCCAA5533
#define SENTINEL_AFTER_VALUE 0x3355AACC
#define SET_SENTINEL_BEFORE(NodePtr) (*(UINT32 *) ((UINT8 *) NodePtr + sizeof (BUFFER_NODE)) = SENTINEL_BEFORE_VALUE);
#define SET_SENTINEL_AFTER(NodePtr) (*(UINT32 *) ((UINT8 *) NodePtr + sizeof (BUFFER_NODE) + SIZE_OF_SENTINEL + NodePtr->BufferSize) = SENTINEL_AFTER_VALUE);
#define Heap_Check(stdheader) AmdHeapIntactCheck(stdheader)
#else
#define SIZE_OF_SENTINEL 0
#define SENTINEL_BEFORE_VALUE 0xCCAA5533
#define SENTINEL_AFTER_VALUE 0x3355AACC
#define SET_SENTINEL_BEFORE(NodePtr)
#define SET_SENTINEL_AFTER(NodePtr)
#define Heap_Check(stdheader)
#endif
#else
#define SIZE_OF_SENTINEL 0
#define SENTINEL_BEFORE_VALUE 0xCCAA5533
#define SENTINEL_AFTER_VALUE 0x3355AACC
#define SET_SENTINEL_BEFORE(NodePtr)
#define SET_SENTINEL_AFTER(NodePtr)
#define Heap_Check(stdheader)
#endif
/**
* Macro to add HDT OUT in memory code.
*
* The default minimal action is to do nothing and there is no any code to increase.
* For debug environments, the debug information can be displayed in HDT or other
* devices.
*
* @param[in] Command HDT_OUT command to control the communication between
* HDT and memory initialization code.
* @param[in] Data Data to be sent to HDT.
* @param[in] Condition Allow the Data to be output if TRUE.
* @param[in] NvId NV ID to control this HDT OUT.
* @param[in,out] StdHeader The Pointer of AGESA Header.
*
**/
#define OPTION_NON_CONSOLE 0xD0
#define OPTION_HDT_CONSOLE 0xD1
#define OPTION_IDS_CONSOLE OPTION_NON_CONSOLE
#if IDSOPT_IDS_ENABLED == TRUE
#if IDSOPT_TRACING_ENABLED == TRUE
#undef OPTION_IDS_CONSOLE
#define OPTION_IDS_CONSOLE OPTION_HDT_CONSOLE
#define IDS_FUNCLIST_ADDR ScriptFuncList
#define IDS_FUNCLIST_EXTERN() extern SCRIPT_FUNCTION ScriptFuncList[]
#define IDS_TIMEOUT_CTL(t) IdsMemTimeOut (t)
#define IDS_HDT_CONSOLE_INIT(x)
#define IDS_HDT_CONSOLE_EXIT(x)
#ifdef __GNUC__
#if IS_ENABLED(CONFIG_REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL)
#define IDS_HDT_CONSOLE(s, args...) do_printk(BIOS_DEBUG, s, ##args)
///#define IDS_HDT_CONSOLE(f, s, args...) printk(((MEM_FLOW) - (f) + (BIOS_DEBUG)), s, ##args)
#else
#define IDS_HDT_CONSOLE(s, args...)
#endif
#else
#define IDS_HDT_CONSOLE(s, args...)
#endif
#else
#define IDS_HDT_CONSOLE_INIT(x)
#define IDS_HDT_CONSOLE_EXIT(x)
#define IDS_HDT_CONSOLE 1 ? (VOID) 0 : AmdIdsConsolePrint
#define IDS_FUNCLIST_ADDR NULL
#define IDS_FUNCLIST_EXTERN()
#define IDS_TIMEOUT_CTL(t)
#endif
#else
#define IDS_HDT_CONSOLE_INIT(x)
#define IDS_HDT_CONSOLE_EXIT(x)
#define IDS_HDT_CONSOLE 1 ? (VOID) 0 : AmdIdsConsolePrint
#define IDS_FUNCLIST_ADDR NULL
#define IDS_FUNCLIST_EXTERN()
#define IDS_TIMEOUT_CTL(t)
#endif
#if IDSOPT_PERF_ANALYSIS == TRUE
#define IDS_PERF_TIMESTAMP(StdHeader, TestPoint) //IdsPerfTimestamp ((StdHeader), (TestPoint))
#define IDS_PERF_ANALYSE(StdHeader) //IdsPerfAnalyseTimestamp (StdHeader)
#define IDS_PERF_TIME_MEASURE(StdHeader) //AGESA_TESTPOINT (TpPerfUnit, StdHeader); AGESA_TESTPOINT (TpPerfUnit, StdHeader);
#else
#define IDS_PERF_TIMESTAMP(StdHeader, TestPoint)
#define IDS_PERF_ANALYSE(StdHeader)
#define IDS_PERF_TIME_MEASURE(StdHeader)
#endif
///For IDS feat use
#define IDS_FAMILY_ALL 0xFFFFFFFFFFFFFFFFull
#define IDS_BSP_ONLY TRUE
#define IDS_ALL_CORES FALSE
#define IDS_LATE_RUN_AP_TASK_ID PROC_IDS_CONTROL_IDSLIB_FILECODE
#define IDS_CALLOUT_INIT 1 ///< The function data of IDS callout function of initialization.
/// Function entry for HDT script to call
typedef struct _SCRIPT_FUNCTION {
UINTN FuncAddr; ///< Function address in ROM
CHAR8 FuncName[40]; ///< Function name
} SCRIPT_FUNCTION;
/// Data Structure for Mem ECC parameter override
typedef struct {
IN BOOLEAN CfgEccRedirection; ///< ECC Redirection
IN UINT16 CfgScrubDramRate; ///< Scrub Dram Rate
IN UINT16 CfgScrubL2Rate; ///< Scrub L2Rate
IN UINT16 CfgScrubL3Rate; ///< Scrub L3Rate
IN UINT16 CfgScrubIcRate; ///< Scrub Ic Rate
IN UINT16 CfgScrubDcRate; ///< Scrub Dc Rate
IN BOOLEAN CfgEccSyncFlood; ///< ECC Sync Flood
} ECC_OVERRIDE_STRUCT;
/**
* AGESA Test Points
*
* These are the values displayed to the user to indicate progress through boot.
* These can be used in a debug environment to stop the debugger at a specific
* test point:
* For SimNow!, this command
* bi 81 w vb 49
* will stop the debugger on one of the TracePoints (49 is the TP value in this example).
*
*/
typedef enum {
StartProcessorTestPoints, ///< 00 Entry used for range testing for @b Processor related TPs
// Memory test points
TpProcMemBeforeMemDataInit, ///< 01 .. Memory structure initialization (Public interface)
TpProcMemBeforeSpdProcessing, ///< 02 .. SPD Data processing (Public interface)
TpProcMemAmdMemAuto, ///< 03 .. Memory configuration (Public interface)
TpProcMemDramInit, ///< 04 .. DRAM initialization
TpProcMemSPDChecking, ///< 05 ..
TpProcMemModeChecking, ///< 06 ..
TpProcMemSpeedTclConfig, ///< 07 .. Speed and TCL configuration
TpProcMemSpdTiming, ///< 08 ..
TpProcMemDramMapping, ///< 09 ..
TpProcMemPlatformSpecificConfig, ///< 0A ..
TPProcMemPhyCompensation, ///< 0B ..
TpProcMemStartDcts, ///< 0C ..
TpProcMemBeforeDramInit, ///< 0D .. (Public interface)
TpProcMemPhyFenceTraining, ///< 0E ..
TpProcMemSynchronizeDcts, ///< 0F ..
TpProcMemSystemMemoryMapping, ///< 10 ..
TpProcMemMtrrConfiguration, ///< 11 ..
TpProcMemDramTraining, ///< 12 ..
TpProcMemBeforeAnyTraining, ///< 13 .. (Public interface)
TpProcMemWriteLevelizationTraining, ///< 14 ..
TpProcMemWlFirstPass, ///< 15 .. Below 800Mhz first pass start
TpProcMemWlSecondPass, ///< 16 .. Above 800Mhz second pass start
TpProcMemWlDimmConfig, ///< 17 .. Target DIMM configured
TpProcMemWlPrepDimms, ///< 18 .. Prepare DIMMS for WL
TpProcMemWlConfigDimms, ///< 19 .. Configure DIMMS for WL
TpProcMemReceiverEnableTraining, ///< 1A ..
TpProcMemRcvrStartSweep, ///< 1B .. Start sweep loop
TpProcMemRcvrSetDelay, ///< 1C .. Set receiver Delay
TpProcMemRcvrWritePattern, ///< 1D .. Write test pattern
TpProcMemRcvrReadPattern, ///< 1E .. Read test pattern
TpProcMemRcvrTestPattern, ///< 1F .. Compare test pattern
TpProcMemRcvrCalcLatency, ///< 20 .. Calculate MaxRdLatency per channel
TpProcMemReceiveDqsTraining, ///< 21 ..
TpProcMemRcvDqsSetDelay, ///< 22 .. Set Write Data delay
TpProcMemRcvDqsWritePattern, ///< 23 .. Write test pattern
TpProcMemRcvDqsStartSweep, ///< 24 .. Start read sweep
TpProcMemRcvDqsSetRcvDelay, ///< 25 .. Set Receive DQS delay
TpProcMemRcvDqsReadPattern, ///< 26 .. Read Test pattern
TpProcMemRcvDqsTstPattern, ///< 27 .. Compare Test pattern
TpProcMemRcvDqsResults, ///< 28 .. Update results
TpProcMemRcvDqsFindWindow, ///< 29 .. Start Find passing window
TpProcMemTransmitDqsTraining, ///< 2A ..
TpProcMemTxDqStartSweep, ///< 2B .. Start write sweep
TpProcMemTxDqSetDelay, ///< 2C .. Set Transmit DQ delay
TpProcMemTxDqWritePattern, ///< 2D .. Write test pattern
TpProcMemTxDqReadPattern, ///< 2E .. Read Test pattern
TpProcMemTxDqTestPattern, ///< 2F .. Compare Test pattern
TpProcMemTxDqResults, ///< 30 .. Update results
TpProcMemTxDqFindWindow, ///< 31 .. Start Find passing window
TpProcMemMaxRdLatencyTraining, ///< 32 ..
TpProcMemMaxRdLatStartSweep, ///< 33 .. Start sweep
TpProcMemMaxRdLatSetDelay, ///< 34 .. Set delay
TpProcMemMaxRdLatWritePattern, ///< 35 .. Write test pattern
TpProcMemMaxRdLatReadPattern, ///< 36 .. Read Test pattern
TpProcMemMaxRdLatTestPattern, ///< 37 .. Compare Test pattern
TpProcMemOnlineSpareInit, ///< 38 .. Online Spare init
TpProcMemBankInterleaveInit, ///< 39 .. Bank Interleave Init
TpProcMemNodeInterleaveInit, ///< 3A .. Node Interleave Init
TpProcMemChannelInterleaveInit, ///< 3B .. Channel Interleave Init
TpProcMemEccInitialization, ///< 3C .. ECC initialization
TpProcMemPlatformSpecificInit, ///< 3D .. Platform Specific Init
TpProcMemBeforeAgesaReadSpd, ///< 3E .. Before callout for "AgesaReadSpd"
TpProcMemAfterAgesaReadSpd, ///< 3F .. After callout for "AgesaReadSpd"
TpProcMemBeforeAgesaHookBeforeDramInit, ///< 40 .. Before optional callout "AgesaHookBeforeDramInit"
TpProcMemAfterAgesaHookBeforeDramInit, ///< 41 .. After optional callout "AgesaHookBeforeDramInit"
TpProcMemBeforeAgesaHookBeforeDQSTraining, ///< 42 .. Before optional callout "AgesaHookBeforeDQSTraining"
TpProcMemAfterAgesaHookBeforeDQSTraining, ///< 43 .. After optional callout "AgesaHookBeforeDQSTraining"
TpProcMemBeforeAgesaHookBeforeExitSelfRef, ///< 44 .. Before optional callout "AgesaHookBeforeDramInit"
TpProcMemAfterAgesaHookBeforeExitSelfRef, ///< 45 .. After optional callout "AgesaHookBeforeDramInit"
TpProcMemAfterMemDataInit, ///< 46 .. After MemDataInit
TpProcMemInitializeMCT, ///< 47 .. Before InitializeMCT
TpProcMemLvDdr3, ///< 48 .. Before LV DDR3
TpProcMemInitMCT, ///< 49 .. Before InitMCT
TpProcMemOtherTiming, ///< 4A.. Before OtherTiming
TpProcMemUMAMemTyping, ///< 4B .. Before UMAMemTyping
TpProcMemSetDqsEccTmgs, ///< 4C .. Before SetDqsEccTmgs
TpProcMemMemClr, ///< 4D .. Before MemClr
TpProcMemOnDimmThermal, ///< 4E .. Before On DIMM Thermal
TpProcMemDmi, ///< 4F .. Before DMI
TpProcMemEnd, ///< 50 .. End of memory code
// CPU test points
TpProcCpuEntryDmi, ///< 51 .. Entry point CreateDmiRecords
TpProcCpuEntryPstate, ///< 52 .. Entry point CreateAcpiTables
TpProcCpuEntryPstateLeveling, ///< 53 .. Entry point PStateLeveling
TpProcCpuEntryPstateGather, ///< 54 .. Entry point PStateGatherData
TpProcCpuEntryWhea, ///< 55 .. Entry point CreateAcpiWhea
TpProcCpuEntrySrat, ///< 56 .. Entry point CreateAcpiSrat
TpProcCpuEntrySlit, ///< 57 .. Entry point CreateAcpiSlit
TpProcCpuProcessRegisterTables, ///< 58 .. Register table processing
TpProcCpuSetBrandID, ///< 59 .. Set brand ID
TpProcCpuLocalApicInit, ///< 5A .. Initialize local APIC
TpProcCpuLoadUcode, ///< 5B .. Load microcode patch
TpProcCpuPowerMgmtInit, ///< 5C .. Power Management table processing
TpProcCpuEarlyFeatureInit, ///< 5D .. Early feature dispatch point
TpProcCpuCoreLeveling, ///< 5E .. Core Leveling
TpProcCpuApMtrrSync, ///< 5F .. AP MTRR sync up
TpProcCpuPostFeatureInit, ///< 60 .. POST feature dispatch point
TpProcCpuFeatureLeveling, ///< 61 .. CPU Feature Leveling
TpProcCpuBeforeAllocateWheaBuffer, ///< 62 .. Before the WHEA init code calls out to allocate a buffer
TpProcCpuAfterAllocateWheaBuffer, ///< 63 .. After the WHEA init code calls out to allocate a buffer
TpProcCpuBeforeAllocateSratBuffer, ///< 64 .. Before the SRAT init code calls out to allocate a buffer
TpProcCpuAfterAllocateSratBuffer, ///< 65 .. After the SRAT init code calls out to allocate a buffer
TpProcCpuBeforeLocateSsdtBuffer, ///< 66 .. Before the P-state init code calls out to locate a buffer
TpProcCpuAfterLocateSsdtBuffer, ///< 67 .. After the P-state init code calls out to locate a buffer
TpProcCpuBeforeAllocateSsdtBuffer, ///< 68 .. Before the P-state init code calls out to allocate a buffer
TpProcCpuAfterAllocateSsdtBuffer, ///< 69 .. After the P-state init code calls out to allocate a buffer
// HT test points
TpProcHtEntry = 0x71, ///< 71 .. Coherent Discovery begin (Public interface)
TpProcHtTopology, ///< 72 .. Topology match, routing, begin
TpProcHtManualNc, ///< 73 .. Manual Non-coherent Init begin
TpProcHtAutoNc, ///< 74 .. Automatic Non-coherent init begin
TpProcHtOptGather, ///< 75 .. Optimization: Gather begin
TpProcHtOptRegang, ///< 76 .. Optimization: Regang begin
TpProcHtOptLinks, ///< 77 .. Optimization: Link Begin
TpProcHtOptSubLinks, ///< 78 .. Optimization: Sublinks begin
TpProcHtOptFinish, ///< 79 .. Optimization: Set begin
TpProcHtTrafficDist, ///< 7A .. Traffic Distribution begin
TpProcHtTuning, ///< 7B .. Misc Tuning Begin
TpProcHtDone, ///< 7C .. HT Init complete
TpProcHtApMapEntry, ///< 7D .. AP HT: Init Maps begin
TpProcHtApMapDone, ///< 7E .. AP HT: Complete
StartNbTestPoints = 0x90, ///< 90 Entry used for range testing for @b NorthBridge related TPs
TpNbxxx, ///< 91 .
EndNbTestPoints, ///< 92 End of TP range for NB
StartSbTestPoints = 0xB0, ///< B0 Entry used for range testing for @b SouthBridge related TPs
TpSbxxx, ///< B1 .
EndSbTestPoints, ///< B2 End of TP range for SB
// Interface test points
TpIfAmdInitResetEntry = 0xC0, ///< C0 .. Entry to AmdInitReset
TpIfAmdInitResetExit, ///< C1 .. Exiting from AmdInitReset
TpIfAmdInitRecoveryEntry, ///< C2 .. Entry to AmdInitRecovery
TpIfAmdInitRecoveryExit, ///< C3 .. Exiting from AmdInitRecovery
TpIfAmdInitEarlyEntry, ///< C4 .. Entry to AmdInitEarly
TpIfAmdInitEarlyExit, ///< C5 .. Exiting from AmdInitEarly
TpIfAmdInitPostEntry, ///< C6 .. Entry to AmdInitPost
TpIfAmdInitPostExit, ///< C7 .. Exiting from AmdInitPost
TpIfAmdInitEnvEntry, ///< C8 .. Entry to AmdInitEnv
TpIfAmdInitEnvExit, ///< C9 .. Exiting from AmdInitEnv
TpIfAmdInitMidEntry, ///< CA .. Entry to AmdInitMid
TpIfAmdInitMidExit, ///< CB .. Exiting from AmdInitMid
TpIfAmdInitLateEntry, ///< CC .. Entry to AmdInitLate
TpIfAmdInitLateExit, ///< CD .. Exiting from AmdInitLate
TpIfAmdS3SaveEntry, ///< CE .. Entry to AmdS3Save
TpIfAmdS3SaveExit, ///< CF .. Exiting from AmdS3Save
TpIfAmdInitResumeEntry, ///< D0 .. Entry to AmdInitResume
TpIfAmdInitResumeExit, ///< D1 .. Exiting from AmdInitResume
TpIfAmdS3LateRestoreEntry, ///< D2 .. Entry to AmdS3LateRestore
TpIfAmdS3LateRestoreExit, ///< D3 .. Exiting from AmdS3LateRestore
TpIfAmdLateRunApTaskEntry, ///< D4 .. Entry to AmdS3LateRestore
TpIfAmdLateRunApTaskExit, ///< D5 .. Exiting from AmdS3LateRestore
TpIfAmdReadEventLogEntry, ///< D6 .. Entry to AmdReadEventLog
TpIfAmdReadEventLogExit, ///< D7 .. Exiting from AmdReadEventLog
TpIfAmdGetApicIdEntry, ///< D8 .. Entry to AmdGetApicId
TpIfAmdGetApicIdExit, ///< D9 .. Exiting from AmdGetApicId
TpIfAmdGetPciAddressEntry, ///< DA .. Entry to AmdGetPciAddress
TpIfAmdGetPciAddressExit, ///< DB .. Exiting from AmdGetPciAddress
TpIfAmdIdentifyCoreEntry, ///< DC .. Entry to AmdIdentifyCore
TpIfAmdIdentifyCoreExit, ///< DD .. Exiting from AmdIdentifyCore
TpIfBeforeRunApFromIds, ///< DE .. After IDS calls out to run code on an AP
TpIfAfterRunApFromIds, ///< DF .. After IDS calls out to run code on an AP
TpIfBeforeGetIdsData, ///< E0 .. Before IDS calls out to get IDS data
TpIfAfterGetIdsData, ///< E1 .. After IDS calls out to get IDS data
TpIfBeforeAllocateHeapBuffer, ///< E2 .. Before the heap manager calls out to allocate a buffer
TpIfAfterAllocateHeapBuffer, ///< E3 .. After the heap manager calls out to allocate a buffer
TpIfBeforeDeallocateHeapBuffer, ///< E4 .. Before the heap manager calls out to deallocate a buffer
TpIfAfterDeallocateHeapBuffer, ///< E5 .. After the heap manager calls out to deallocate a buffer
TpIfBeforeLocateHeapBuffer, ///< E6 .. Before the heap manager calls out to locate a buffer
TpIfAfterLocateHeapBuffer, ///< E7 .. After the heap manager calls out to locate a buffer
TpIfBeforeRunApFromAllAps, ///< E8 .. Before the BSP calls out to run code on an AP
TpIfAfterRunApFromAllAps, ///< E9 .. After the BSP calls out to run code on an AP
TpIfBeforeRunApFromAllCore0s, ///< EA .. Before the BSP calls out to run code on an AP
TpIfAfterRunApFromAllCore0s, ///< EB .. After the BSP calls out to run code on an AP
TpIfBeforeAllocateS3SaveBuffer, ///< EC .. Before the S3 save code calls out to allocate a buffer
TpIfAfterAllocateS3SaveBuffer, ///< ED .. After the S3 save code calls out to allocate a buffer
TpIfBeforeAllocateMemoryS3SaveBuffer, ///< EE .. Before the memory S3 save code calls out to allocate a buffer
TpIfAfterAllocateMemoryS3SaveBuffer, ///< EF .. After the memory S3 save code calls out to allocate a buffer
TpIfBeforeLocateS3PciBuffer, ///< F0 .. Before the memory code calls out to locate a buffer
TpIfAfterLocateS3PciBuffer, ///< F1 .. After the memory code calls out to locate a buffer
TpIfBeforeLocateS3CPciBuffer, ///< F2 .. Before the memory code calls out to locate a buffer
TpIfAfterLocateS3CPciBuffer, ///< F3 .. After the memory code calls out to locate a buffer
TpIfBeforeLocateS3MsrBuffer, ///< F4 .. Before the memory code calls out to locate a buffer
TpIfAfterLocateS3MsrBuffer, ///< F5 .. After the memory code calls out to locate a buffer
TpIfBeforeLocateS3CMsrBuffer, ///< F6 .. Before the memory code calls out to locate a buffer
TpIfAfterLocateS3CMsrBuffer, ///< F7 .. After the memory code calls out to locate a buffer
TpPerfUnit, ///< F8 .. The Unit of performance measure.
EndAgesaTps = 0xFF, ///< Last defined AGESA TP
} AGESA_TP;
///Ids Feat description
typedef enum {
IDS_FEAT_UCODE_UPDATE = 0x0000, ///< Feat for Ucode Update
IDS_FEAT_TARGET_PSTATE, ///< Feat for Target Pstate
IDS_FEAT_POSTPSTATE, ///< Feat for Post Pstate
IDS_FEAT_ECC_CTRL, ///< Feat for Ecc Control
IDS_FEAT_ECC_SYMBOL_SIZE, ///< Feat for Ecc symbol size
IDS_FEAT_DCT_ALLMEMCLK, ///< Feat for all memory clock
IDS_FEAT_DCT_GANGMODE, ///< Feat for Dct gang mode
IDS_FEAT_DCT_BURSTLENGTH, ///< Feat for dct burst length
IDS_FEAT_DCT_POWERDOWN, ///< Feat for dct power down
IDS_FEAT_DCT_DLLSHUTDOWN, ///< Feat for dct dll shut down
IDS_FEAT_PROBE_FILTER, ///< Feat for probe filter
IDS_FEAT_HDTOUT, ///< Feat for hdt out
IDS_FEAT_HT_SETTING, ///< Feat for Ht setting
IDS_FEAT_GNB_PLATFORMCFG, ///< Feat for override GNB platform config
IDS_FEAT_END ///< End of Common feat
} IDS_FEAT;
typedef IDS_STATUS IDS_COMMON_FUNC (
IN OUT VOID *DataPtr,
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN IDS_NV_ITEM *IdsNvPtr
);
typedef IDS_COMMON_FUNC *PIDS_COMMON_FUNC;
/// Data Structure of IDS Feature block
typedef struct _IDS_FEAT_STRUCT {
IDS_FEAT IdsFeat; ///< Ids Feat ID
BOOLEAN IsBsp; ///< swith for Bsp check
AGESA_IDS_OPTION IdsOption; ///< IDS option
UINT64 CpuFamily; ///<
PIDS_COMMON_FUNC pf_idsoption; ///<pointer to function
} IDS_FEAT_STRUCT;
/// Data Structure of IDS option
typedef struct _IDS_OPTION_STRUCT {
AGESA_IDS_OPTION idsoption; ///< IDS option
PIDS_COMMON_FUNC pf_idsoption; ///<pointer to function
} IDS_OPTION_STRUCT;
/// Data Structure of IDS option table
typedef struct _IDS_OPTION_STRUCT_TBL {
UINT8 version; ///<Version of IDS option table
UINT16 size; ///<Size of IDS option table
CONST IDS_OPTION_STRUCT *pIdsOptionStruct; ///<pointer to array of structure
} IDS_OPTION_STRUCT_TBL;
IDS_STATUS
AmdIdsCtrlDispatcher (
IN AGESA_IDS_OPTION IdsOption,
IN OUT VOID *DataPtr,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
VOID
AmdIdsConsoleInit (
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
VOID
AmdIdsConsolePrint (
IN CHAR8 *Format,
IN ...
);
VOID
AmdIdsConsoleExit (
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
VOID
IdsMemTimeOut (
IN OUT VOID *DataPtr
);
VOID
IdsAgesaTestPoint (
IN AGESA_TP TestPoint,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
/**
* The engine code for ASSERT MACRO
*
* Halt execution with stop code display. Stop Code is displayed on port 80, with rotation so that
* it is visible on 8, 16, or 32 bit display. The stop code is alternated with 0xDEAD on the display,
* to help distinguish the stop code from a post code loop.
* Additional features may be available if using simulation.
*
* @param[in] FileCode File code(define in FILECODE.h) mix with assert Line num.
*
*/
BOOLEAN
IdsErrorStop (
IN UINT32 FileCode
);
VOID
IdsDelay (
IN VOID
);
BOOLEAN
AmdHeapIntactCheck (
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID
IdsCarCorruptionCheck (
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
#endif // _IDS_H_

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@ -1,123 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD IDS HyperTransport Definitions
*
* Contains AMD AGESA Integrated Debug HT related items.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: IDS
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _IDS_HT_H_
#define _IDS_HT_H_
// Frequency equates for call backs which take an actual frequency setting
#define HT_FREQUENCY_200M 0
#define HT_FREQUENCY_400M 2
#define HT_FREQUENCY_600M 4
#define HT_FREQUENCY_800M 5
#define HT_FREQUENCY_1000M 6
#define HT_FREQUENCY_1200M 7
#define HT_FREQUENCY_1400M 8
#define HT_FREQUENCY_1600M 9
#define HT_FREQUENCY_1800M 10
#define HT_FREQUENCY_2000M 11
#define HT_FREQUENCY_2200M 12
#define HT_FREQUENCY_2400M 13
#define HT_FREQUENCY_2600M 14
#define HT_FREQUENCY_2800M 17
#define HT_FREQUENCY_3000M 18
#define HT_FREQUENCY_3200M 19
#define HT_FREQUENCY_3600M 20
/**
* HT IDS: HT Link Port Override params.
*
* Provide an absolute override of HT Link Port settings. No checking is done that
* the settings obey limits or capabilities, this responsibility rests with the user.
*
* Rules for values of structure items:
* - Socket
* - HT_LIST_TERMINAL == end of port override list, rest of item is not accessed
* - HT_LIST_MATCH_ANY == Match Any Socket
* - 0 .. 7 == The matching socket
* - Link
* - HT_LIST_MATCH_ANY == Match Any package link (that is not the internal links)
* - HT_LIST_MATCH_INTERNAL_LINK == Match the internal links
* - 0 .. 7 == The matching package link. 0 .. 3 are the ganged links or sublink 0's, 4 .. 7 are the sublink1's.
* - Frequency
* - HT_LIST_TERMINAL == Do not override the frequency, AUTO setting
* - HT_FREQUENCY_200M .. HT_FREQUENCY_3600M = The frequency value to use
* - Widthin
* - HT_LIST_TERMINAL == Do not override the width, AUTO setting
* - 2, 4, 8, 16, 32 == The width value to use
* - Widthout
* - HT_LIST_TERMINAL == Do not override the width, AUTO setting
* - 2, 4, 8, 16, 32 == The width value to use
*/
typedef struct {
// Match Fields
UINT8 Socket; ///< The Socket which this port is on.
UINT8 Link; ///< The port for this package link on that socket.
// Override fields
UINT8 Frequency; ///< Absolutely override the port's frequency.
UINT8 WidthIn; ///< Absolutely override the port's width.
UINT8 WidthOut; ///< Absolutely override the port's width.
} HTIDS_PORT_OVERRIDE;
/**
* A list of port overrides to search.
*/
typedef HTIDS_PORT_OVERRIDE *HTIDS_PORT_OVERRIDE_LIST;
VOID
HtIdsGetPortOverride (
IN BOOLEAN IsSourcePort,
IN OUT PORT_DESCRIPTOR *Port0,
IN OUT PORT_DESCRIPTOR *Port1,
IN OUT HTIDS_PORT_OVERRIDE_LIST *PortOverrideList,
IN STATE_DATA *State
);
typedef
VOID
F_HtIdsGetPortOverride (
IN BOOLEAN IsSourcePort,
IN OUT PORT_DESCRIPTOR *Port0,
IN OUT PORT_DESCRIPTOR *Port1,
IN OUT HTIDS_PORT_OVERRIDE_LIST *PortOverrideList,
IN STATE_DATA *State
);
typedef F_HtIdsGetPortOverride* PF_HtIdsGetPortOverride;
#endif // _IDS_HT_H

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/**
* @file
*
* Install of build option: C6 C-state
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#ifndef _OPTION_C6_STATE_INSTALL_H_
#define _OPTION_C6_STATE_INSTALL_H_
#include "cpuC6State.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_C6_STATE_FEAT
#define F12_C6_STATE_SUPPORT
#if OPTION_C6_STATE == TRUE
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE)
#ifdef OPTION_FAMILY12H
#if OPTION_FAMILY12H == TRUE
#if OPTION_FAMILY12H_LN == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State;
#undef OPTION_C6_STATE_FEAT
#define OPTION_C6_STATE_FEAT &CpuFeatureC6State,
extern CONST C6_FAMILY_SERVICES ROMDATA F12C6Support;
#undef F12_C6_STATE_SUPPORT
#define F12_C6_STATE_SUPPORT {AMD_FAMILY_12_LN, &F12C6Support},
#endif
#endif
#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA C6FamilyServiceArray[] =
{
F12_C6_STATE_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA C6FamilyServiceTable =
{
(sizeof (C6FamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&C6FamilyServiceArray[0]
};
#endif // _OPTION_C6_STATE_INSTALL_H_

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src/vendorcode/amd/agesa/f10/Include/OptionCpuCacheFlushOnHaltInstall.h
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/**
* @file
*
* Install of build option: CPU Cache Flush On Halt
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 17487 $ @e \$Date: 2009-08-06 14:17:58 -0500 (Thu, 06 Aug 2009) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#ifndef _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_
#define _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_
#include "cpuPostInit.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
#define F10_BL_CPU_CFOH_SUPPORT
#define F10_DA_CPU_CFOH_SUPPORT
#define F10_CPU_CFOH_SUPPORT
#if OPTION_CPU_CFOH == TRUE
#if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE)
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCacheFlushOnHalt;
#undef OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
#define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT &CpuFeatureCacheFlushOnHalt,
#if OPTION_FAMILY10H_BL == TRUE
extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10BlCacheFlushOnHalt;
#undef F10_BL_CPU_CFOH_SUPPORT
#define F10_BL_CPU_CFOH_SUPPORT {AMD_FAMILY_10_BL, &F10BlCacheFlushOnHalt},
#endif
#if OPTION_FAMILY10H_DA == TRUE
extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10DaCacheFlushOnHalt;
#undef F10_DA_CPU_CFOH_SUPPORT
#define F10_DA_CPU_CFOH_SUPPORT {AMD_FAMILY_10_DA, &F10DaCacheFlushOnHalt},
#endif
#if (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_HY == TRUE)
extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10CacheFlushOnHalt;
#undef F10_CPU_CFOH_SUPPORT
#define F10_CPU_CFOH_SUPPORT {AMD_FAMILY_10_RB | AMD_FAMILY_10_HY, &F10CacheFlushOnHalt},
#endif
#endif
#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CacheFlushOnHaltFamilyServiceArray[] =
{
F10_BL_CPU_CFOH_SUPPORT
F10_DA_CPU_CFOH_SUPPORT
F10_CPU_CFOH_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CacheFlushOnHaltFamilyServiceTable =
{
(sizeof (CacheFlushOnHaltFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&CacheFlushOnHaltFamilyServiceArray[0]
};
#endif // _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_

92
src/vendorcode/amd/agesa/f10/Include/OptionCpuCoreLevelingInstall.h
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@ -1,92 +0,0 @@
/**
* @file
*
* Install of build option: CPU Core Leveling
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 17487 $ @e \$Date: 2009-08-06 14:17:58 -0500 (Thu, 06 Aug 2009) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#ifndef _OPTION_CPU_CORELEVELING_INSTALL_H_
#define _OPTION_CPU_CORELEVELING_INSTALL_H_
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_CPU_CORE_LEVELING_FEAT
#define F10_REVD_CPU_CORELEVELING_SUPPORT
#define F10_REVC_CPU_CORELEVELING_SUPPORT
#if OPTION_CPU_CORELEVLING == TRUE
#if (AGESA_ENTRY_INIT_EARLY == TRUE)
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling;
#undef OPTION_CPU_CORE_LEVELING_FEAT
#define OPTION_CPU_CORE_LEVELING_FEAT &CpuFeatureCoreLeveling,
#if OPTION_FAMILY10H_HY == TRUE
extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevDCoreLeveling;
#undef F10_REVD_CPU_CORELEVELING_SUPPORT
#define F10_REVD_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_HY, &F10RevDCoreLeveling},
#endif
#if (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE)
extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevCCoreLeveling;
#undef F10_REVC_CPU_CORELEVELING_SUPPORT
#define F10_REVC_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_RB | AMD_FAMILY_10_BL | AMD_FAMILY_10_DA, &F10RevCCoreLeveling},
#endif
#endif
#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CoreLevelingFamilyServiceArray[] =
{
F10_REVD_CPU_CORELEVELING_SUPPORT
F10_REVC_CPU_CORELEVELING_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CoreLevelingFamilyServiceTable =
{
(sizeof (CoreLevelingFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&CoreLevelingFamilyServiceArray[0]
};
#endif // _OPTION_CPU_CORELEVELING_INSTALL_H_

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src/vendorcode/amd/agesa/f10/Include/OptionCpuFeaturesInstall.h
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@ -1,67 +0,0 @@
/**
* @file
*
* Install of multiple CPU features.
*
* Aggregates enabled CPU features into a list for the dispatcher to process.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#ifndef _OPTION_CPU_FEATURES_INSTALL_H_
#define _OPTION_CPU_FEATURES_INSTALL_H_
#include "OptionHwC1eInstall.h"
#include "OptionMsgBasedC1eInstall.h"
#include "OptionHtAssistInstall.h"
#include "OptionCpuCoreLevelingInstall.h"
#include "OptionC6Install.h"
#include "OptionCpuCacheFlushOnHaltInstall.h"
#include "OptionPreserveMailboxInstall.h"
CONST CPU_FEATURE_DESCRIPTOR* ROMDATA SupportedCpuFeatureList[] =
{
OPTION_HW_C1E_FEAT
OPTION_MSG_BASED_C1E_FEAT
OPTION_HT_ASSIST_FEAT
OPTION_CPU_CORE_LEVELING_FEAT
OPTION_C6_STATE_FEAT
OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
OPTION_PRESERVE_MAILBOX_FEAT
NULL
};
#endif // _OPTION_CPU_FEATURES_INSTALL_H_

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src/vendorcode/amd/agesa/f10/Include/OptionDanubeMicrocodeInstall.h
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@ -1,63 +0,0 @@
/**
* @file
*
* Install microcode build options for a Danube platform solution
*
* This file generates the defaults tables for the "Danube" platform solution
* set of processors. The documented build options are imported from a user
* controlled file for processing.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#ifndef _OPTION_DANUBE_MICROCODE_INSTALL_H_
#define _OPTION_DANUBE_MICROCODE_INSTALL_H_
extern CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000b6;
// 'NULL' must be put at the end of MicroCodePatchArray[]
CONST MICROCODE_PATCHES ROMDATA *CpuF10BlMicroCodePatchArray[] =
{
&CpuF10MicrocodePatch010000b6,
NULL
};
CONST MICROCODE_PATCHES ROMDATA *CpuF10DaMicroCodePatchArray[] =
{
&CpuF10MicrocodePatch010000b6,
NULL
};
#endif

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src/vendorcode/amd/agesa/f10/Include/OptionDmi.h
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@ -1,89 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD DMI option API.
*
* Contains structures and values used to control the DMI option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_DMI_H_
#define _OPTION_DMI_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
typedef AGESA_STATUS OPTION_DMI_FEATURE (
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN OUT DMI_INFO **DmiPtr
);
typedef AGESA_STATUS OPTION_DMI_RELEASE_BUFFER (
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
#define DMI_STRUCT_VERSION 0x01
/// DMI option configuration. Determine the item of structure when compiling.
typedef struct {
UINT16 OptDmiVersion; ///< Dmi version.
OPTION_DMI_FEATURE *DmiFeature; ///< Feature main routine, otherwise dummy.
OPTION_DMI_RELEASE_BUFFER *DmiReleaseBuffer; ///< Release buffer
UINT16 NumEntries; ///< Number of entry.
VOID *((*FamilyList)[]); ///< Family service.
} OPTION_DMI_CONFIGURATION;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_DMI_H_

138
src/vendorcode/amd/agesa/f10/Include/OptionDmiInstall.h
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/**
* @file
*
* Install of build option: DMI
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#ifndef _OPTION_DMI_INSTALL_H_
#define _OPTION_DMI_INSTALL_H_
#include "cpuLateInit.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#if AGESA_ENTRY_INIT_LATE == TRUE
#ifndef OPTION_DMI
#error BLDOPT: Option not defined: "OPTION_DMI"
#endif
#if OPTION_DMI == TRUE
OPTION_DMI_FEATURE GetDmiInfoMain;
OPTION_DMI_RELEASE_BUFFER ReleaseDmiBuffer;
#define USER_DMI_OPTION &GetDmiInfoMain
#define USER_DMI_RELEASE_BUFFER &ReleaseDmiBuffer
#define CPU_DMI_AP_GET_TYPE4_TYPE7 {AP_LATE_TASK_GET_TYPE4_TYPE7, (IMAGE_ENTRY) GetType4Type7Info},
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
extern PROC_FAMILY_TABLE ProcFamily10DmiTable;
#define FAM10_DMI_SUPPORT FAM10_ENABLED,
#define FAM10_DMI_TABLE &ProcFamily10DmiTable,
#else
#define FAM10_DMI_SUPPORT
#define FAM10_DMI_TABLE
#endif
#else
#define FAM10_DMI_SUPPORT
#define FAM10_DMI_TABLE
#endif
#ifdef OPTION_FAMILY12H
#if OPTION_FAMILY12H == TRUE
extern PROC_FAMILY_TABLE ProcFamily12DmiTable;
#define FAM12_DMI_SUPPORT FAM12_ENABLED,
#define FAM12_DMI_TABLE &ProcFamily12DmiTable,
#else
#define FAM12_DMI_SUPPORT
#define FAM12_DMI_TABLE
#endif
#else
#define FAM12_DMI_SUPPORT
#define FAM12_DMI_TABLE
#endif
#else
OPTION_DMI_FEATURE GetDmiInfoStub;
OPTION_DMI_RELEASE_BUFFER ReleaseDmiBufferStub;
#define USER_DMI_OPTION GetDmiInfoStub
#define USER_DMI_RELEASE_BUFFER ReleaseDmiBufferStub
#define FAM10_DMI_SUPPORT
#define FAM10_DMI_TABLE
#define FAM12_DMI_SUPPORT
#define FAM12_DMI_TABLE
#define CPU_DMI_AP_GET_TYPE4_TYPE7
#endif
#else
OPTION_DMI_FEATURE GetDmiInfoStub;
OPTION_DMI_RELEASE_BUFFER ReleaseDmiBufferStub;
#define USER_DMI_OPTION GetDmiInfoStub
#define USER_DMI_RELEASE_BUFFER ReleaseDmiBufferStub
#define FAM10_DMI_SUPPORT
#define FAM10_DMI_TABLE
#define FAM12_DMI_SUPPORT
#define FAM12_DMI_TABLE
#define CPU_DMI_AP_GET_TYPE4_TYPE7
#endif
/// DMI supported families enum
typedef enum {
FAM10_DMI_SUPPORT ///< Conditionally define F10 support
FAM12_DMI_SUPPORT ///< Conditionally define F12 support
NUM_DMI_FAMILIES ///< Number of installed families
} AGESA_DMI_SUPPORTED_FAM;
/* Declare the Family List. An array of pointers to tables that each describe a family */
CONST PROC_FAMILY_TABLE ROMDATA *ProcTables[] = {
FAM10_DMI_TABLE
FAM12_DMI_TABLE
NULL
};
/* Declare the instance of the DMI option configuration structure */
CONST OPTION_DMI_CONFIGURATION ROMDATA OptionDmiConfiguration = {
DMI_STRUCT_VERSION,
USER_DMI_OPTION,
USER_DMI_RELEASE_BUFFER,
NUM_DMI_FAMILIES,
(VOID *((*)[])) &ProcTables // Compiler says array size must match struct decl
};
#endif // _OPTION_DMI_INSTALL_H_

73
src/vendorcode/amd/agesa/f10/Include/OptionDragonMicrocodeInstall.h
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@ -1,73 +0,0 @@
/**
* @file
*
* Install microcode build options for a Dragon platform solution
*
* This file generates the defaults tables for the "Dragon" platform solution
* set of processors. The documented build options are imported from a user
* controlled file for processing.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#ifndef _OPTION_DRAGON_MICROCODE_INSTALL_H_
#define _OPTION_DRAGON_MICROCODE_INSTALL_H_
extern CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch01000086;
extern CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch01000085;
extern CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000b6;
// 'NULL' must be put at the end of MicroCodePatchArray[]
CONST MICROCODE_PATCHES ROMDATA *CpuF10BlMicroCodePatchArray[] =
{
&CpuF10MicrocodePatch010000b6,
NULL
};
CONST MICROCODE_PATCHES ROMDATA *CpuF10DaMicroCodePatchArray[] =
{
&CpuF10MicrocodePatch010000b6,
NULL
};
CONST MICROCODE_PATCHES ROMDATA *CpuF10RbMicroCodePatchArray[] =
{
&CpuF10MicrocodePatch01000086,
&CpuF10MicrocodePatch01000085,
&CpuF10MicrocodePatch010000b6,
NULL
};
#endif

91
src/vendorcode/amd/agesa/f10/Include/OptionFamily10h.h
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/**
* @file
*
* Structures and definitions for family 10h support
*
* This file defines the structures and definitions needed for installation
* of family 10h processors.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#ifndef _OPTION_FAMILY_10H_H_
#define _OPTION_FAMILY_10H_H_
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
extern F_CPU_GET_PSTATE_POWER F10GetPstatePower;
extern F_CPU_GET_PSTATE_FREQ F10GetPstateFrequency;
extern F_CPU_DISABLE_PSTATE F10DisablePstate;
extern F_CPU_TRANSITION_PSTATE F10TransitionPstate;
extern F_CPU_GET_TSC_RATE F10GetTscRate;
extern F_CPU_PSTATE_TRANSITION_LATENCY F10GetPstateTransLatency;
extern F_CPU_GET_PSTATE_REGISTER_INFO F10GetPstateRegisterInfo;
extern F_CPU_GET_PSTATE_MAX_STATE F10GetPstateMaxState;
extern F_CPU_SET_PSTATE_LEVELING_REG F10PstateLevelingCoreMsrModify;
extern F_CPU_GET_NB_FREQ F10GetNbFrequency;
extern F_CPU_AP_INITIAL_LAUNCH F10LaunchApCore;
extern F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE F10GetApMailboxFromHardware;
extern F_CPU_SET_AP_CORE_NUMBER F10SetApCoreNumber;
extern F_CPU_GET_AP_CORE_NUMBER F10GetApCoreNumber;
extern F_CPU_TRANSFER_AP_CORE_NUMBER F10TransferApCoreNumber;
extern F_CORE_ID_POSITION_IN_INITIAL_APIC_ID F10CpuAmdCoreIdPositionInInitialApicId;
extern F_CPU_SAVE_FEATURES F10SaveFeatures;
extern F_CPU_WRITE_FEATURES F10WriteFeatures;
extern F_CPU_SET_WARM_RESET_FLAG F10SetAgesaWarmResetFlag;
extern F_CPU_GET_WARM_RESET_FLAG F10GetAgesaWarmResetFlag;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10BrandIdString1;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10BrandIdString2;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10CacheInfo;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10SysPmTable;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10WheaInitData;
//extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetEmptyArray;
extern F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO F10GetPlatformTypeSpecificInfo;
extern F_DOES_LINK_HAVE_HTFPY_FEATS F10DoesLinkHaveHtPhyFeats;
extern F_SET_HT_PHY_REGISTER F10SetHtPhyRegister;
extern F_GET_HT_LINK_FEATURES F10GetHtLinkFeatures;
extern F_DO_TABLE_ENTRY F10SetRegisterForHtLinkTokenEntry;
extern CONST REGISTER_TABLE ROMDATA F10PciRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F10MsrRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F10HtPhyRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F10MultiLinkPciRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F10SingleLinkPciRegisterTable;
extern F_GET_EARLY_INIT_TABLE GetCommonEarlyInitOnCoreTable;
#endif // OPTION_FAMILY10H == TRUE
#endif // defined (OPTION_FAMILY10H)
#endif // _OPTION_FAMILY_10H_H_

354
src/vendorcode/amd/agesa/f10/Include/OptionFamily10hBlInstall.h
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@ -1,354 +0,0 @@
/**
* @file
*
* Install of family 10h model 5 support
*
* This file generates the defaults tables for family 10h model 5 processors.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
#ifdef OPTION_FAMILY10H_BL
#if OPTION_FAMILY10H_BL == TRUE
extern CONST REGISTER_TABLE ROMDATA F10RevCPciRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F10RevCMsrRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F10RevCHtPhyRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F10BlPciRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F10BlMsrRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F10BlHtPhyRegisterTable;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10BlMicroCodePatchesStruct;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10BlMicrocodeEquivalenceTable;
extern F_CPU_GET_IDD_MAX F10CommonRevCGetProcIddMax;
extern F_CPU_GET_NB_FREQ F10CommonRevCGetNbFrequency;
extern F_CPU_IS_NBCOF_INIT_NEEDED F10CommonRevCGetNbCofVidUpdate;
extern F_IS_NB_PSTATE_ENABLED F10CommonRevCIsNbPstateEnabled;
extern F_CPU_NUMBER_OF_BRANDSTRING_CORES F10CommonRevCGetNumberOfCoresForBrandstring;
#if USES_REGISTER_TABLES == TRUE
CONST REGISTER_TABLE ROMDATA *F10BlRegisterTables[] =
{
#if BASE_FAMILY_PCI == TRUE
&F10PciRegisterTable,
#endif
#if MODEL_SPECIFIC_PCI == TRUE
&F10SingleLinkPciRegisterTable,
#endif
#if MODEL_SPECIFIC_PCI == TRUE
&F10RevCPciRegisterTable,
#endif
#if MODEL_SPECIFIC_PCI == TRUE
&F10BlPciRegisterTable,
#endif
#if BASE_FAMILY_MSR == TRUE
&F10MsrRegisterTable,
#endif
#if MODEL_SPECIFIC_MSR == TRUE
&F10RevCMsrRegisterTable,
#endif
#if MODEL_SPECIFIC_MSR == TRUE
&F10BlMsrRegisterTable,
#endif
#if MODEL_SPECIFIC_HT_PCI == TRUE
&F10HtPhyRegisterTable,
#endif
#if MODEL_SPECIFIC_HT_PCI == TRUE
&F10RevCHtPhyRegisterTable,
#endif
#if MODEL_SPECIFIC_HT_PCI == TRUE
&F10BlHtPhyRegisterTable,
#endif
// the end.
NULL
};
#endif
#if USES_REGISTER_TABLES == TRUE
CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10BlTableEntryTypeDescriptors[] =
{
{MSRREGISTER, SetRegisterForMsrEntry},
{PCIREGISTER, SetRegisterForPciEntry},
{ErrataWorkaround, SetRegisterForErrataWorkaroundEntry},
{HtPhyRegister, SetRegisterForHtPhyEntry},
{HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
{DeemphasisRegister, SetRegisterForDeemphasisEntry},
{ProfileFixup, SetRegisterForPerformanceProfileEntry},
{HtHostPciRegister, SetRegisterForHtHostEntry},
{HtTokenPciRegister, (PF_DO_TABLE_ENTRY)CommonVoid},
{CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
{ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
{HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
{HtPhyProfileRegister, SetRegisterForHtPhyProfileEntry},
// End
{TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
};
#endif
CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10BlServices =
{
0,
#if GET_PSTATE_POWER == TRUE
F10GetPstatePower,
#else
(PF_CPU_GET_PSTATE_POWER) CommonAssert,
#endif
#if GET_PSTATE_FREQ == TRUE
F10GetPstateFrequency,
#else
(PF_CPU_GET_PSTATE_FREQ) CommonAssert,
#endif
#if DISABLE_PSTATE == TRUE
F10DisablePstate,
#else
(PF_CPU_DISABLE_PSTATE) CommonAssert,
#endif
#if TRANSITION_PSTATE == TRUE
F10TransitionPstate,
#else
(PF_CPU_TRANSITION_PSTATE) CommonAssert,
#endif
#if PROC_IDD_MAX == TRUE
F10CommonRevCGetProcIddMax,
#else
(PF_CPU_GET_IDD_MAX) CommonAssert,
#endif
#if GET_TSC_RATE == TRUE
F10GetTscRate,
#else
(PF_CPU_GET_TSC_RATE) CommonAssert,
#endif
#if PSTATE_TRANSITION_LATENCY == TRUE
F10GetPstateTransLatency,
#else
(PF_CPU_PSTATE_TRANSITION_LATENCY) CommonAssert,
#endif
#if GET_PSTATE_REGISTER_INFO == TRUE
F10GetPstateRegisterInfo,
#else
(PF_CPU_GET_PSTATE_REGISTER_INFO) CommonAssert,
#endif
#if GET_PSTATE_MAX_STATE == TRUE
F10GetPstateMaxState,
#else
(PF_CPU_GET_PSTATE_MAX_STATE) CommonAssert,
#endif
#if SET_PSTATE_LEVELING_REG == TRUE
F10PstateLevelingCoreMsrModify,
#else
(PF_CPU_SET_PSTATE_LEVELING_REG) CommonAssert,
#endif
#if GET_NB_FREQ == TRUE
F10CommonRevCGetNbFrequency,
#else
(PF_CPU_GET_NB_FREQ) CommonAssert,
#endif
#if IS_NBCOF_INIT_NEEDED == TRUE
F10CommonRevCGetNbCofVidUpdate,
#else
(PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
#endif
#if AP_INITIAL_LAUNCH == TRUE
F10LaunchApCore,
#else
(PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
#endif
#if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
F10CommonRevCGetNumberOfCoresForBrandstring,
#else
(PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
#endif
#if GET_AP_MAILBOX_FROM_HW == TRUE
F10GetApMailboxFromHardware,
#else
(PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
#endif
#if SET_AP_CORE_NUMBER == TRUE
F10SetApCoreNumber,
#else
(PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
#endif
#if GET_AP_CORE_NUMBER == TRUE
F10GetApCoreNumber,
#else
(PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
#endif
#if TRANSFER_AP_CORE_NUMBER == TRUE
F10TransferApCoreNumber,
#else
(PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
#endif
#if ID_POSITION_INITIAL_APICID == TRUE
F10CpuAmdCoreIdPositionInInitialApicId,
#else
(PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
#endif
#if SAVE_FEATURES == TRUE
F10SaveFeatures,
#else
(PF_CPU_SAVE_FEATURES) CommonAssert,
#endif
#if WRITE_FEATURES == TRUE
F10WriteFeatures,
#else
(PF_CPU_WRITE_FEATURES) CommonAssert,
#endif
#if SET_WARM_RESET_FLAG == TRUE
F10SetAgesaWarmResetFlag,
#else
(PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
#endif
#if GET_WARM_RESET_FLAG == TRUE
F10GetAgesaWarmResetFlag,
#else
(PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
#endif
#if BRAND_STRING1 == TRUE
GetF10BrandIdString1,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if BRAND_STRING2 == TRUE
GetF10BrandIdString2,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PATCHES == TRUE
GetF10BlMicroCodePatchesStruct,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
GetF10BlMicrocodeEquivalenceTable,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_CACHE_INFO == TRUE
GetF10CacheInfo,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_SYSTEM_PM_TABLE == TRUE
GetF10SysPmTable,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_WHEA_INIT == TRUE
GetF10WheaInitData,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
F10GetPlatformTypeSpecificInfo,
#else
(PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
#endif
#if IS_NB_PSTATE_ENABLED == TRUE
F10CommonRevCIsNbPstateEnabled,
#else
(PF_IS_NB_PSTATE_ENABLED) CommonAssert,
#endif
#if (BASE_FAMILY_HT_PCI == TRUE)
F10DoesLinkHaveHtPhyFeats,
#else
(PF_DOES_LINK_HAVE_HTFPY_FEATS) CommonReturnFalse,
#endif
#if (BASE_FAMILY_HT_PCI == TRUE)
F10SetHtPhyRegister,
#else
(PF_SET_HT_PHY_REGISTER) CommonAssert,
#endif
#if BASE_FAMILY_PCI == TRUE
F10GetHtLinkFeatures,
#else
(PF_GET_HT_LINK_FEATURES) CommonAssert,
#endif
#if USES_REGISTER_TABLES == TRUE
(REGISTER_TABLE **) F10BlRegisterTables,
#else
NULL,
#endif
#if USES_REGISTER_TABLES == TRUE
(TABLE_ENTRY_TYPE_DESCRIPTOR *) F10BlTableEntryTypeDescriptors,
#else
NULL,
#endif
NULL,
#if AGESA_ENTRY_INIT_EARLY == TRUE
GetCommonEarlyInitOnCoreTable
#else
(PF_GET_EARLY_INIT_TABLE) CommonVoid
#endif
};
#define BL_SOCKETS 1
#define BL_MODULES 1
#define BL_RECOVERY_SOCKETS 1
#define BL_RECOVERY_MODULES 1
extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF10BlLogicalIdAndRev;
#define OPT_F10_BL_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF10BlLogicalIdAndRev,
#ifndef ADVCFG_PLATFORM_SOCKETS
#define ADVCFG_PLATFORM_SOCKETS BL_SOCKETS
#else
#if ADVCFG_PLATFORM_SOCKETS < BL_SOCKETS
#undef ADVCFG_PLATFORM_SOCKETS
#define ADVCFG_PLATFORM_SOCKETS BL_SOCKETS
#endif
#endif
#ifndef ADVCFG_PLATFORM_MODULES
#define ADVCFG_PLATFORM_MODULES BL_MODULES
#else
#if ADVCFG_PLATFORM_MODULES < BL_MODULES
#undef ADVCFG_PLATFORM_MODULES
#define ADVCFG_PLATFORM_MODULES BL_MODULES
#endif
#endif
#define OPT_F10_BL_CPU {AMD_FAMILY_10_BL, &cpuF10BlServices},
#else
#define OPT_F10_BL_CPU
#define OPT_F10_BL_ID
#endif
#else
#define OPT_F10_BL_CPU
#define OPT_F10_BL_ID
#endif
#else
#define OPT_F10_BL_CPU
#define OPT_F10_BL_ID
#endif
#else
#define OPT_F10_BL_CPU
#define OPT_F10_BL_ID
#endif

354
src/vendorcode/amd/agesa/f10/Include/OptionFamily10hDaInstall.h
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@ -1,354 +0,0 @@
/**
* @file
*
* Install of family 10h model 6 support
*
* This file generates the defaults tables for family 10h model 6 processors.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
#ifdef OPTION_FAMILY10H_DA
#if OPTION_FAMILY10H_DA == TRUE
extern CONST REGISTER_TABLE ROMDATA F10RevCPciRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F10RevCMsrRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F10RevCHtPhyRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F10DaPciRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F10DaMsrRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F10DaHtPhyRegisterTable;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10DaMicroCodePatchesStruct;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10DaMicrocodeEquivalenceTable;
extern F_CPU_GET_IDD_MAX F10CommonRevCGetProcIddMax;
extern F_CPU_GET_NB_FREQ F10CommonRevCGetNbFrequency;
extern F_CPU_IS_NBCOF_INIT_NEEDED F10CommonRevCGetNbCofVidUpdate;
extern F_IS_NB_PSTATE_ENABLED F10CommonRevCIsNbPstateEnabled;
extern F_CPU_NUMBER_OF_BRANDSTRING_CORES F10CommonRevCGetNumberOfCoresForBrandstring;
#if USES_REGISTER_TABLES == TRUE
CONST REGISTER_TABLE ROMDATA *F10DaRegisterTables[] =
{
#if BASE_FAMILY_PCI == TRUE
&F10PciRegisterTable,
#endif
#if MODEL_SPECIFIC_PCI == TRUE
&F10SingleLinkPciRegisterTable,
#endif
#if MODEL_SPECIFIC_PCI == TRUE
&F10RevCPciRegisterTable,
#endif
#if MODEL_SPECIFIC_PCI == TRUE
&F10DaPciRegisterTable,
#endif
#if BASE_FAMILY_MSR == TRUE
&F10MsrRegisterTable,
#endif
#if MODEL_SPECIFIC_MSR == TRUE
&F10RevCMsrRegisterTable,
#endif
#if MODEL_SPECIFIC_MSR == TRUE
&F10DaMsrRegisterTable,
#endif
#if MODEL_SPECIFIC_HT_PCI == TRUE
&F10HtPhyRegisterTable,
#endif
#if MODEL_SPECIFIC_HT_PCI == TRUE
&F10RevCHtPhyRegisterTable,
#endif
#if MODEL_SPECIFIC_HT_PCI == TRUE
&F10DaHtPhyRegisterTable,
#endif
// the end.
NULL
};
#endif
#if USES_REGISTER_TABLES == TRUE
CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10DaTableEntryTypeDescriptors[] =
{
{MsrRegister, SetRegisterForMsrEntry},
{PciRegister, SetRegisterForPciEntry},
{ErrataWorkaround, SetRegisterForErrataWorkaroundEntry},
{HtPhyRegister, SetRegisterForHtPhyEntry},
{HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
{DeemphasisRegister, SetRegisterForDeemphasisEntry},
{ProfileFixup, SetRegisterForPerformanceProfileEntry},
{HtHostPciRegister, SetRegisterForHtHostEntry},
{HtTokenPciRegister, (PF_DO_TABLE_ENTRY)CommonVoid},
{CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
{ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
{HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
{HtPhyProfileRegister, SetRegisterForHtPhyProfileEntry},
// End
{TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
};
#endif
CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10DaServices =
{
0,
#if GET_PSTATE_POWER == TRUE
F10GetPstatePower,
#else
(PF_CPU_GET_PSTATE_POWER) CommonAssert,
#endif
#if GET_PSTATE_FREQ == TRUE
F10GetPstateFrequency,
#else
(PF_CPU_GET_PSTATE_FREQ) CommonAssert,
#endif
#if DISABLE_PSTATE == TRUE
F10DisablePstate,
#else
(PF_CPU_DISABLE_PSTATE) CommonAssert,
#endif
#if TRANSITION_PSTATE == TRUE
F10TransitionPstate,
#else
(PF_CPU_TRANSITION_PSTATE) CommonAssert,
#endif
#if PROC_IDD_MAX == TRUE
F10CommonRevCGetProcIddMax,
#else
(PF_CPU_GET_IDD_MAX) CommonAssert,
#endif
#if GET_TSC_RATE == TRUE
F10GetTscRate,
#else
(PF_CPU_GET_TSC_RATE) CommonAssert,
#endif
#if PSTATE_TRANSITION_LATENCY == TRUE
F10GetPstateTransLatency,
#else
(PF_CPU_PSTATE_TRANSITION_LATENCY) CommonAssert,
#endif
#if GET_PSTATE_REGISTER_INFO == TRUE
F10GetPstateRegisterInfo,
#else
(PF_CPU_GET_PSTATE_REGISTER_INFO) CommonAssert,
#endif
#if GET_PSTATE_MAX_STATE == TRUE
F10GetPstateMaxState,
#else
(PF_CPU_GET_PSTATE_MAX_STATE) CommonAssert,
#endif
#if SET_PSTATE_LEVELING_REG == TRUE
F10PstateLevelingCoreMsrModify,
#else
(PF_CPU_SET_PSTATE_LEVELING_REG) CommonAssert,
#endif
#if GET_NB_FREQ == TRUE
F10CommonRevCGetNbFrequency,
#else
(PF_CPU_GET_NB_FREQ) CommonAssert,
#endif
#if IS_NBCOF_INIT_NEEDED == TRUE
F10CommonRevCGetNbCofVidUpdate,
#else
(PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
#endif
#if AP_INITIAL_LAUNCH == TRUE
F10LaunchApCore,
#else
(PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
#endif
#if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
F10CommonRevCGetNumberOfCoresForBrandstring,
#else
(PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
#endif
#if GET_AP_MAILBOX_FROM_HW == TRUE
F10GetApMailboxFromHardware,
#else
(PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
#endif
#if SET_AP_CORE_NUMBER == TRUE
F10SetApCoreNumber,
#else
(PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
#endif
#if GET_AP_CORE_NUMBER == TRUE
F10GetApCoreNumber,
#else
(PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
#endif
#if TRANSFER_AP_CORE_NUMBER == TRUE
F10TransferApCoreNumber,
#else
(PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
#endif
#if ID_POSITION_INITIAL_APICID == TRUE
F10CpuAmdCoreIdPositionInInitialApicId,
#else
(PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
#endif
#if SAVE_FEATURES == TRUE
F10SaveFeatures,
#else
(PF_CPU_SAVE_FEATURES) CommonAssert,
#endif
#if WRITE_FEATURES == TRUE
F10WriteFeatures,
#else
(PF_CPU_WRITE_FEATURES) CommonAssert,
#endif
#if SET_WARM_RESET_FLAG == TRUE
F10SetAgesaWarmResetFlag,
#else
(PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
#endif
#if GET_WARM_RESET_FLAG == TRUE
F10GetAgesaWarmResetFlag,
#else
(PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
#endif
#if BRAND_STRING1 == TRUE
GetF10BrandIdString1,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if BRAND_STRING2 == TRUE
GetF10BrandIdString2,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PATCHES == TRUE
GetF10DaMicroCodePatchesStruct,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
GetF10DaMicrocodeEquivalenceTable,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_CACHE_INFO == TRUE
GetF10CacheInfo,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_SYSTEM_PM_TABLE == TRUE
GetF10SysPmTable,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_WHEA_INIT == TRUE
GetF10WheaInitData,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
F10GetPlatformTypeSpecificInfo,
#else
(PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
#endif
#if IS_NB_PSTATE_ENABLED == TRUE
F10CommonRevCIsNbPstateEnabled,
#else
(PF_IS_NB_PSTATE_ENABLED) CommonAssert,
#endif
#if (BASE_FAMILY_HT_PCI == TRUE)
F10DoesLinkHaveHtPhyFeats,
#else
(PF_DOES_LINK_HAVE_HTFPY_FEATS) CommonReturnFalse,
#endif
#if (BASE_FAMILY_HT_PCI == TRUE)
F10SetHtPhyRegister,
#else
(PF_SET_HT_PHY_REGISTER) CommonAssert,
#endif
#if BASE_FAMILY_PCI == TRUE
F10GetHtLinkFeatures,
#else
(PF_GET_HT_LINK_FEATURES) CommonAssert,
#endif
#if USES_REGISTER_TABLES == TRUE
(REGISTER_TABLE **) F10DaRegisterTables,
#else
NULL,
#endif
#if USES_REGISTER_TABLES == TRUE
(TABLE_ENTRY_TYPE_DESCRIPTOR *) F10DaTableEntryTypeDescriptors,
#else
NULL,
#endif
NULL,
#if AGESA_ENTRY_INIT_EARLY == TRUE
GetCommonEarlyInitOnCoreTable
#else
(PF_GET_EARLY_INIT_TABLE) CommonVoid
#endif
};
#define DA_SOCKETS 1
#define DA_MODULES 1
#define DA_RECOVERY_SOCKETS 1
#define DA_RECOVERY_MODULES 1
extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF10DaLogicalIdAndRev;
#define OPT_F10_DA_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF10DaLogicalIdAndRev,
#ifndef ADVCFG_PLATFORM_SOCKETS
#define ADVCFG_PLATFORM_SOCKETS DA_SOCKETS
#else
#if ADVCFG_PLATFORM_SOCKETS < DA_SOCKETS
#undef ADVCFG_PLATFORM_SOCKETS
#define ADVCFG_PLATFORM_SOCKETS DA_SOCKETS
#endif
#endif
#ifndef ADVCFG_PLATFORM_MODULES
#define ADVCFG_PLATFORM_MODULES DA_MODULES
#else
#if ADVCFG_PLATFORM_MODULES < DA_MODULES
#undef ADVCFG_PLATFORM_MODULES
#define ADVCFG_PLATFORM_MODULES DA_MODULES
#endif
#endif
#define OPT_F10_DA_CPU {AMD_FAMILY_10_DA, &cpuF10DaServices},
#else
#define OPT_F10_DA_CPU
#define OPT_F10_DA_ID
#endif
#else
#define OPT_F10_DA_CPU
#define OPT_F10_DA_ID
#endif
#else
#define OPT_F10_DA_CPU
#define OPT_F10_DA_ID
#endif
#else
#define OPT_F10_DA_CPU
#define OPT_F10_DA_ID
#endif

353
src/vendorcode/amd/agesa/f10/Include/OptionFamily10hHyInstall.h
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@ -1,353 +0,0 @@
/**
* @file
*
* Install of family 10h model 9 support
*
* This file generates the defaults tables for family 10h model 9 processors.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
#ifdef OPTION_FAMILY10H_HY
#if OPTION_FAMILY10H_HY == TRUE
extern CONST REGISTER_TABLE ROMDATA F10HyPciRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F10HyMsrRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F10HyHtPhyRegisterTable;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10HyMicroCodePatchesStruct;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10HyMicrocodeEquivalenceTable;
extern F_CPU_GET_IDD_MAX F10CommonRevDGetProcIddMax;
extern F_CPU_GET_NB_FREQ F10CommonRevDGetNbFrequency;
extern F_CPU_IS_NBCOF_INIT_NEEDED F10CommonRevDGetNbCofVidUpdate;
extern CONST PACKAGE_HTLINK_MAP_ITEM ROMDATA HtFam10RevDPackageLinkMap[];
extern F_CPU_NUMBER_OF_BRANDSTRING_CORES F10CommonRevDGetNumberOfCoresForBrandstring;
extern F_GET_EARLY_INIT_TABLE GetF10HyEarlyInitOnCoreTable;
#if USES_REGISTER_TABLES == TRUE
CONST REGISTER_TABLE ROMDATA *F10HyRegisterTables[] =
{
#if BASE_FAMILY_PCI == TRUE
&F10PciRegisterTable,
#endif
#if MODEL_SPECIFIC_PCI == TRUE
&F10MultiLinkPciRegisterTable,
#endif
#if MODEL_SPECIFIC_PCI == TRUE
&F10HyPciRegisterTable,
#endif
#if BASE_FAMILY_MSR == TRUE
&F10MsrRegisterTable,
#endif
#if MODEL_SPECIFIC_MSR == TRUE
&F10HyMsrRegisterTable,
#endif
#if MODEL_SPECIFIC_HT_PCI == TRUE
&F10HtPhyRegisterTable,
#endif
#if MODEL_SPECIFIC_HT_PCI == TRUE
&F10HyHtPhyRegisterTable,
#endif
// the end.
NULL
};
#endif
#if USES_REGISTER_TABLES == TRUE
CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10HyTableEntryTypeDescriptors[] =
{
{MSRREGISTER, SetRegisterForMsrEntry},
{PCIREGISTER, SetRegisterForPciEntry},
{ErrataWorkaround, SetRegisterForErrataWorkaroundEntry},
{HtPhyRegister, SetRegisterForHtPhyEntry},
{HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
{DeemphasisRegister, SetRegisterForDeemphasisEntry},
{HtPhyFreqRegister, SetRegisterForHtPhyFreqEntry},
{ProfileFixup, SetRegisterForPerformanceProfileEntry},
{HtHostPciRegister, SetRegisterForHtHostEntry},
{HtTokenPciRegister, F10SetRegisterForHtLinkTokenEntry},
{CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
{ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
{TokenPciRegister, SetRegisterForTokenPciEntry},
{HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
{HtLinkPciRegister, SetRegisterForHtLinkPciEntry},
// End
{TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
};
#endif
CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10HyServices =
{
0,
#if GET_PSTATE_POWER == TRUE
F10GetPstatePower,
#else
(PF_CPU_GET_PSTATE_POWER) CommonAssert,
#endif
#if GET_PSTATE_FREQ == TRUE
F10GetPstateFrequency,
#else
(PF_CPU_GET_PSTATE_FREQ) CommonAssert,
#endif
#if DISABLE_PSTATE == TRUE
F10DisablePstate,
#else
(PF_CPU_DISABLE_PSTATE) CommonAssert,
#endif
#if TRANSITION_PSTATE == TRUE
F10TransitionPstate,
#else
(PF_CPU_TRANSITION_PSTATE) CommonAssert,
#endif
#if PROC_IDD_MAX == TRUE
F10CommonRevDGetProcIddMax,
#else
(PF_CPU_GET_IDD_MAX) CommonAssert,
#endif
#if GET_TSC_RATE == TRUE
F10GetTscRate,
#else
(PF_CPU_GET_TSC_RATE) CommonAssert,
#endif
#if PSTATE_TRANSITION_LATENCY == TRUE
F10GetPstateTransLatency,
#else
(PF_CPU_PSTATE_TRANSITION_LATENCY) CommonAssert,
#endif
#if GET_PSTATE_REGISTER_INFO == TRUE
F10GetPstateRegisterInfo,
#else
(PF_CPU_GET_PSTATE_REGISTER_INFO) CommonAssert,
#endif
#if GET_PSTATE_MAX_STATE == TRUE
F10GetPstateMaxState,
#else
(PF_CPU_GET_PSTATE_MAX_STATE) CommonAssert,
#endif
#if SET_PSTATE_LEVELING_REG == TRUE
F10PstateLevelingCoreMsrModify,
#else
(PF_CPU_SET_PSTATE_LEVELING_REG) CommonAssert,
#endif
#if GET_NB_FREQ == TRUE
F10CommonRevDGetNbFrequency,
#else
(PF_CPU_GET_NB_FREQ) CommonAssert,
#endif
#if IS_NBCOF_INIT_NEEDED == TRUE
F10CommonRevDGetNbCofVidUpdate,
#else
(PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
#endif
#if AP_INITIAL_LAUNCH == TRUE
F10LaunchApCore,
#else
(PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
#endif
#if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
F10CommonRevDGetNumberOfCoresForBrandstring,
#else
(PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
#endif
#if GET_AP_MAILBOX_FROM_HW == TRUE
F10GetApMailboxFromHardware,
#else
(PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
#endif
#if SET_AP_CORE_NUMBER == TRUE
F10SetApCoreNumber,
#else
(PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
#endif
#if GET_AP_CORE_NUMBER == TRUE
F10GetApCoreNumber,
#else
(PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
#endif
#if TRANSFER_AP_CORE_NUMBER == TRUE
F10TransferApCoreNumber,
#else
(PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
#endif
#if ID_POSITION_INITIAL_APICID == TRUE
F10CpuAmdCoreIdPositionInInitialApicId,
#else
(PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
#endif
#if SAVE_FEATURES == TRUE
F10SaveFeatures,
#else
(PF_CPU_SAVE_FEATURES) CommonAssert,
#endif
#if WRITE_FEATURES == TRUE
F10WriteFeatures,
#else
(PF_CPU_WRITE_FEATURES) CommonAssert,
#endif
#if SET_WARM_RESET_FLAG == TRUE
F10SetAgesaWarmResetFlag,
#else
(PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
#endif
#if GET_WARM_RESET_FLAG == TRUE
F10GetAgesaWarmResetFlag,
#else
(PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
#endif
#if BRAND_STRING1 == TRUE
GetF10BrandIdString1,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if BRAND_STRING2 == TRUE
GetF10BrandIdString2,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PATCHES == TRUE
GetF10HyMicroCodePatchesStruct,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
GetF10HyMicrocodeEquivalenceTable,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_CACHE_INFO == TRUE
GetF10CacheInfo,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_SYSTEM_PM_TABLE == TRUE
GetF10SysPmTable,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_WHEA_INIT == TRUE
GetF10WheaInitData,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
F10GetPlatformTypeSpecificInfo,
#else
(PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
#endif
#if IS_NB_PSTATE_ENABLED == TRUE
(PF_IS_NB_PSTATE_ENABLED) CommonReturnFalse,
#else
(PF_IS_NB_PSTATE_ENABLED) CommonAssert,
#endif
#if (BASE_FAMILY_HT_PCI == TRUE)
F10DoesLinkHaveHtPhyFeats,
#else
(PF_DOES_LINK_HAVE_HTFPY_FEATS) CommonReturnFalse,
#endif
#if (BASE_FAMILY_HT_PCI == TRUE)
F10SetHtPhyRegister,
#else
(PF_SET_HT_PHY_REGISTER) CommonAssert,
#endif
#if BASE_FAMILY_PCI == TRUE
F10GetHtLinkFeatures,
#else
(PF_GET_HT_LINK_FEATURES) CommonAssert,
#endif
#if USES_REGISTER_TABLES == TRUE
(REGISTER_TABLE **) F10HyRegisterTables,
#else
NULL,
#endif
#if USES_REGISTER_TABLES == TRUE
(TABLE_ENTRY_TYPE_DESCRIPTOR *) F10HyTableEntryTypeDescriptors,
#else
NULL,
#endif
#if MODEL_SPECIFIC_HT_PCI == TRUE
(PACKAGE_HTLINK_MAP) &HtFam10RevDPackageLinkMap,
#else
NULL,
#endif
#if AGESA_ENTRY_INIT_EARLY == TRUE
#if OPTION_MEMCTLR_C32 == TRUE
GetF10HyEarlyInitOnCoreTable
#else
GetCommonEarlyInitOnCoreTable
#endif
#else
(PF_GET_EARLY_INIT_TABLE) CommonVoid
#endif
};
#define HY_SOCKETS 8
#define HY_MODULES 2
#define HY_RECOVERY_SOCKETS 1
#define HY_RECOVERY_MODULES 1
extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF10HyLogicalIdAndRev;
#define OPT_F10_HY_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF10HyLogicalIdAndRev,
#ifndef ADVCFG_PLATFORM_SOCKETS
#define ADVCFG_PLATFORM_SOCKETS HY_SOCKETS
#else
#if ADVCFG_PLATFORM_SOCKETS < HY_SOCKETS
#undef ADVCFG_PLATFORM_SOCKETS
#define ADVCFG_PLATFORM_SOCKETS HY_SOCKETS
#endif
#endif
#ifndef ADVCFG_PLATFORM_MODULES
#define ADVCFG_PLATFORM_MODULES HY_MODULES
#else
#if ADVCFG_PLATFORM_MODULES < HY_MODULES
#undef ADVCFG_PLATFORM_MODULES
#define ADVCFG_PLATFORM_MODULES HY_MODULES
#endif
#endif
#define OPT_F10_HY_CPU {AMD_FAMILY_10_HY, &cpuF10HyServices},
#else
#define OPT_F10_HY_CPU
#define OPT_F10_HY_ID
#endif
#else
#define OPT_F10_HY_CPU
#define OPT_F10_HY_ID
#endif
#else
#define OPT_F10_HY_CPU
#define OPT_F10_HY_ID
#endif
#else
#define OPT_F10_HY_CPU
#define OPT_F10_HY_ID
#endif

345
src/vendorcode/amd/agesa/f10/Include/OptionFamily10hInstall.h
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@ -1,345 +0,0 @@
/**
* @file
*
* Install of family 10h support
*
* This file generates the defaults tables for family 10h processors.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
#if USES_REGISTER_TABLES == TRUE
CONST REGISTER_TABLE ROMDATA *F10UnknownRegisterTables[] =
{
#if BASE_FAMILY_PCI == TRUE
&F10PciRegisterTable,
#endif
#if BASE_FAMILY_MSR == TRUE
&F10MsrRegisterTable,
#endif
#if BASE_FAMILY_HT_PCI == TRUE
&F10HtPhyRegisterTable,
#endif
#if OPTION_MULTISOCKET == TRUE
#if MODEL_SPECIFIC_PCI == TRUE
&F10MultiLinkPciRegisterTable,
#endif
#endif
#if OPTION_MULTISOCKET == FALSE
#if MODEL_SPECIFIC_PCI == TRUE
&F10SingleLinkPciRegisterTable,
#endif
#endif
// the end.
NULL
};
#endif
#if USES_REGISTER_TABLES == TRUE
CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10UnknownTableEntryTypeDescriptors[] =
{
{MSRREGISTER, SetRegisterForMsrEntry},
{PCIREGISTER, SetRegisterForPciEntry},
{ErrataWorkaround, SetRegisterForErrataWorkaroundEntry},
{HtPhyRegister, SetRegisterForHtPhyEntry},
{HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
{DeemphasisRegister, SetRegisterForDeemphasisEntry},
{ProfileFixup, SetRegisterForPerformanceProfileEntry},
{HtHostPciRegister, SetRegisterForHtHostEntry},
{HtTokenPciRegister, (PF_DO_TABLE_ENTRY)CommonVoid},
{CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
{ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
{HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
// End
{TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
};
#endif
CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10UnknownServices =
{
0,
#if GET_PSTATE_POWER == TRUE
F10GetPstatePower,
#else
(PF_CPU_GET_PSTATE_POWER) CommonAssert,
#endif
#if GET_PSTATE_FREQ == TRUE
F10GetPstateFrequency,
#else
(PF_CPU_GET_PSTATE_FREQ) CommonAssert,
#endif
#if DISABLE_PSTATE == TRUE
F10DisablePstate,
#else
(PF_CPU_DISABLE_PSTATE) CommonAssert,
#endif
#if TRANSITION_PSTATE == TRUE
F10TransitionPstate,
#else
(PF_CPU_TRANSITION_PSTATE) CommonAssert,
#endif
#if PROC_IDD_MAX == TRUE
(PF_CPU_GET_IDD_MAX) CommonReturnFalse,
#else
(PF_CPU_GET_IDD_MAX) CommonAssert,
#endif
#if GET_TSC_RATE == TRUE
F10GetTscRate,
#else
(PF_CPU_GET_TSC_RATE) CommonAssert,
#endif
#if PSTATE_TRANSITION_LATENCY == TRUE
F10GetPstateTransLatency,
#else
(PF_CPU_PSTATE_TRANSITION_LATENCY) CommonAssert,
#endif
#if GET_PSTATE_REGISTER_INFO == TRUE
F10GetPstateRegisterInfo,
#else
(PF_CPU_GET_PSTATE_REGISTER_INFO) CommonAssert,
#endif
#if GET_PSTATE_MAX_STATE == TRUE
F10GetPstateMaxState,
#else
(PF_CPU_GET_PSTATE_MAX_STATE) CommonAssert,
#endif
#if SET_PSTATE_LEVELING_REG == TRUE
F10PstateLevelingCoreMsrModify,
#else
(PF_CPU_SET_PSTATE_LEVELING_REG) CommonAssert,
#endif
#if GET_NB_FREQ == TRUE
F10GetNbFrequency,
#else
(PF_CPU_GET_NB_FREQ) CommonAssert,
#endif
#if IS_NBCOF_INIT_NEEDED == TRUE
(PF_CPU_IS_NBCOF_INIT_NEEDED) CommonReturnFalse,
#else
(PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
#endif
#if AP_INITIAL_LAUNCH == TRUE
F10LaunchApCore,
#else
(PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
#endif
#if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
(PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonReturnZero8,
#else
(PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
#endif
#if GET_AP_MAILBOX_FROM_HW == TRUE
F10GetApMailboxFromHardware,
#else
(PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
#endif
#if SET_AP_CORE_NUMBER == TRUE
F10SetApCoreNumber,
#else
(PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
#endif
#if GET_AP_CORE_NUMBER == TRUE
F10GetApCoreNumber,
#else
(PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
#endif
#if TRANSFER_AP_CORE_NUMBER == TRUE
F10TransferApCoreNumber,
#else
(PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
#endif
#if ID_POSITION_INITIAL_APICID == TRUE
F10CpuAmdCoreIdPositionInInitialApicId,
#else
(PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
#endif
#if SAVE_FEATURES == TRUE
F10SaveFeatures,
#else
(PF_CPU_SAVE_FEATURES) CommonAssert,
#endif
#if WRITE_FEATURES == TRUE
F10WriteFeatures,
#else
(PF_CPU_WRITE_FEATURES) CommonAssert,
#endif
#if SET_WARM_RESET_FLAG == TRUE
F10SetAgesaWarmResetFlag,
#else
(PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
#endif
#if GET_WARM_RESET_FLAG == TRUE
F10GetAgesaWarmResetFlag,
#else
(PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
#endif
#if BRAND_STRING1 == TRUE
GetF10BrandIdString1,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if BRAND_STRING2 == TRUE
GetF10BrandIdString2,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PATCHES == TRUE
GetEmptyArray,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
GetEmptyArray,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_CACHE_INFO == TRUE
GetF10CacheInfo,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_SYSTEM_PM_TABLE == TRUE
GetF10SysPmTable,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_WHEA_INIT == TRUE
GetF10WheaInitData,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
F10GetPlatformTypeSpecificInfo,
#else
(PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
#endif
#if IS_NB_PSTATE_ENABLED == TRUE
(PF_IS_NB_PSTATE_ENABLED) CommonReturnFalse,
#else
(PF_IS_NB_PSTATE_ENABLED) CommonAssert,
#endif
#if (BASE_FAMILY_HT_PCI == TRUE)
F10DoesLinkHaveHtPhyFeats,
#else
(PF_DOES_LINK_HAVE_HTFPY_FEATS) CommonVoid,
#endif
#if (BASE_FAMILY_HT_PCI == TRUE)
F10SetHtPhyRegister,
#else
(PF_SET_HT_PHY_REGISTER) CommonVoid,
#endif
#if BASE_FAMILY_PCI == TRUE
F10GetHtLinkFeatures,
#else
(PF_GET_HT_LINK_FEATURES) CommonAssert,
#endif
#if USES_REGISTER_TABLES == TRUE
(REGISTER_TABLE **) F10UnknownRegisterTables,
#else
NULL,
#endif
#if USES_REGISTER_TABLES == TRUE
(TABLE_ENTRY_TYPE_DESCRIPTOR *) F10UnknownTableEntryTypeDescriptors,
#else
NULL,
#endif
NULL,
#if AGESA_ENTRY_INIT_EARLY == TRUE
GetCommonEarlyInitOnCoreTable
#else
(PF_GET_EARLY_INIT_TABLE) CommonVoid
#endif
};
// Family 10h maximum base address is 48 bits. Limit BLDCFG to 48 bits, if appropriate.
#if (FAMILY_MMIO_BASE_MASK < 0xFFFF000000000000ull)
#undef FAMILY_MMIO_BASE_MASK
#define FAMILY_MMIO_BASE_MASK (0xFFFF000000000000ull)
#endif
#define OPT_F10_ID_TABLE {0x10, {AMD_FAMILY_10, AMD_F10_UNKNOWN}, F10LogicalIdTable, (sizeof (F10LogicalIdTable) / sizeof (F10LogicalIdTable[0]))},
#define OPT_F10_UNKNOWN_CPU {AMD_FAMILY_10, &cpuF10UnknownServices},
#else
#define OPT_F10_ID_TABLE
#define OPT_F10_BL_CPU
#define OPT_F10_BL_ID
#define OPT_F10_DA_CPU
#define OPT_F10_DA_ID
#define OPT_F10_HY_CPU
#define OPT_F10_HY_ID
#define OPT_F10_RB_CPU
#define OPT_F10_RB_ID
#define OPT_F10_UNKNOWN_CPU
#endif
#else
#define OPT_F10_ID_TABLE
#define OPT_F10_BL_CPU
#define OPT_F10_BL_ID
#define OPT_F10_DA_CPU
#define OPT_F10_DA_ID
#define OPT_F10_HY_CPU
#define OPT_F10_HY_ID
#define OPT_F10_RB_CPU
#define OPT_F10_RB_ID
#define OPT_F10_UNKNOWN_CPU
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CpuSupportedFamiliesArray[] =
{
OPT_F10_BL_CPU
OPT_F10_DA_CPU
OPT_F10_HY_CPU
OPT_F10_RB_CPU
OPT_F10_UNKNOWN_CPU
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CpuSupportedFamiliesTable =
{
(sizeof (CpuSupportedFamiliesArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&CpuSupportedFamiliesArray[0]
};
CONST PF_CPU_GET_SUBFAMILY_ID_ARRAY ROMDATA F10LogicalIdTable[] =
{
OPT_F10_BL_ID
OPT_F10_DA_ID
OPT_F10_HY_ID
OPT_F10_RB_ID
};

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@ -1,355 +0,0 @@
/**
* @file
*
* Install of family 10h model 4 support
*
* This file generates the defaults tables for family 10h model 4 processors.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
#ifdef OPTION_FAMILY10H_RB
#if OPTION_FAMILY10H_RB == TRUE
extern CONST REGISTER_TABLE ROMDATA F10RevCPciRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F10RevCMsrRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F10RevCHtPhyRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F10RbPciRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F10RbMsrRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F10RbHtPhyRegisterTable;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10RbMicroCodePatchesStruct;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10RbMicrocodeEquivalenceTable;
extern F_CPU_GET_IDD_MAX F10CommonRevCGetProcIddMax;
extern F_CPU_GET_NB_FREQ F10CommonRevCGetNbFrequency;
extern F_CPU_IS_NBCOF_INIT_NEEDED F10CommonRevCGetNbCofVidUpdate;
extern F_IS_NB_PSTATE_ENABLED F10CommonRevCIsNbPstateEnabled;
extern F_CPU_NUMBER_OF_BRANDSTRING_CORES F10CommonRevCGetNumberOfCoresForBrandstring;
#if USES_REGISTER_TABLES == TRUE
CONST REGISTER_TABLE ROMDATA *F10RbRegisterTables[] =
{
#if BASE_FAMILY_PCI == TRUE
&F10PciRegisterTable,
#endif
#if MODEL_SPECIFIC_PCI == TRUE
&F10MultiLinkPciRegisterTable,
#endif
#if MODEL_SPECIFIC_PCI == TRUE
&F10RevCPciRegisterTable,
#endif
#if MODEL_SPECIFIC_PCI == TRUE
&F10RbPciRegisterTable,
#endif
#if BASE_FAMILY_MSR == TRUE
&F10MsrRegisterTable,
#endif
#if MODEL_SPECIFIC_MSR == TRUE
&F10RevCMsrRegisterTable,
#endif
#if MODEL_SPECIFIC_MSR == TRUE
&F10RbMsrRegisterTable,
#endif
#if MODEL_SPECIFIC_HT_PCI == TRUE
&F10HtPhyRegisterTable,
#endif
#if MODEL_SPECIFIC_HT_PCI == TRUE
&F10RevCHtPhyRegisterTable,
#endif
#if MODEL_SPECIFIC_HT_PCI == TRUE
&F10RbHtPhyRegisterTable,
#endif
// the end.
NULL
};
#endif
#if USES_REGISTER_TABLES == TRUE
CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10RbTableEntryTypeDescriptors[] =
{
{MsrRegister, SetRegisterForMsrEntry},
{PciRegister, SetRegisterForPciEntry},
{ErrataWorkaround, SetRegisterForErrataWorkaroundEntry},
{HtPhyRegister, SetRegisterForHtPhyEntry},
{HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
{DeemphasisRegister, SetRegisterForDeemphasisEntry},
{ProfileFixup, SetRegisterForPerformanceProfileEntry},
{HtHostPciRegister, SetRegisterForHtHostEntry},
{HtTokenPciRegister, F10SetRegisterForHtLinkTokenEntry},
{CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
{ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
{TokenPciRegister, SetRegisterForTokenPciEntry},
{HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
{HtPhyProfileRegister, SetRegisterForHtPhyProfileEntry},
// End
{TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
};
#endif
CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10RbServices =
{
0,
#if GET_PSTATE_POWER == TRUE
F10GetPstatePower,
#else
(PF_CPU_GET_PSTATE_POWER) CommonAssert,
#endif
#if GET_PSTATE_FREQ == TRUE
F10GetPstateFrequency,
#else
(PF_CPU_GET_PSTATE_FREQ) CommonAssert,
#endif
#if DISABLE_PSTATE == TRUE
F10DisablePstate,
#else
(PF_CPU_DISABLE_PSTATE) CommonAssert,
#endif
#if TRANSITION_PSTATE == TRUE
F10TransitionPstate,
#else
(PF_CPU_TRANSITION_PSTATE) CommonAssert,
#endif
#if PROC_IDD_MAX == TRUE
F10CommonRevCGetProcIddMax,
#else
(PF_CPU_GET_IDD_MAX) CommonAssert,
#endif
#if GET_TSC_RATE == TRUE
F10GetTscRate,
#else
(PF_CPU_GET_TSC_RATE) CommonAssert,
#endif
#if PSTATE_TRANSITION_LATENCY == TRUE
F10GetPstateTransLatency,
#else
(PF_CPU_PSTATE_TRANSITION_LATENCY) CommonAssert,
#endif
#if GET_PSTATE_REGISTER_INFO == TRUE
F10GetPstateRegisterInfo,
#else
(PF_CPU_GET_PSTATE_REGISTER_INFO) CommonAssert,
#endif
#if GET_PSTATE_MAX_STATE == TRUE
F10GetPstateMaxState,
#else
(PF_CPU_GET_PSTATE_MAX_STATE) CommonAssert,
#endif
#if SET_PSTATE_LEVELING_REG == TRUE
F10PstateLevelingCoreMsrModify,
#else
(PF_CPU_SET_PSTATE_LEVELING_REG) CommonAssert,
#endif
#if GET_NB_FREQ == TRUE
F10CommonRevCGetNbFrequency,
#else
(PF_CPU_GET_NB_FREQ) CommonAssert,
#endif
#if IS_NBCOF_INIT_NEEDED == TRUE
F10CommonRevCGetNbCofVidUpdate,
#else
(PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
#endif
#if AP_INITIAL_LAUNCH == TRUE
F10LaunchApCore,
#else
(PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
#endif
#if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
F10CommonRevCGetNumberOfCoresForBrandstring,
#else
(PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
#endif
#if GET_AP_MAILBOX_FROM_HW == TRUE
F10GetApMailboxFromHardware,
#else
(PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
#endif
#if SET_AP_CORE_NUMBER == TRUE
F10SetApCoreNumber,
#else
(PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
#endif
#if GET_AP_CORE_NUMBER == TRUE
F10GetApCoreNumber,
#else
(PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
#endif
#if TRANSFER_AP_CORE_NUMBER == TRUE
F10TransferApCoreNumber,
#else
(PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
#endif
#if ID_POSITION_INITIAL_APICID == TRUE
F10CpuAmdCoreIdPositionInInitialApicId,
#else
(PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
#endif
#if SAVE_FEATURES == TRUE
F10SaveFeatures,
#else
(PF_CPU_SAVE_FEATURES) CommonAssert,
#endif
#if WRITE_FEATURES == TRUE
F10WriteFeatures,
#else
(PF_CPU_WRITE_FEATURES) CommonAssert,
#endif
#if SET_WARM_RESET_FLAG == TRUE
F10SetAgesaWarmResetFlag,
#else
(PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
#endif
#if GET_WARM_RESET_FLAG == TRUE
F10GetAgesaWarmResetFlag,
#else
(PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
#endif
#if BRAND_STRING1 == TRUE
GetF10BrandIdString1,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if BRAND_STRING2 == TRUE
GetF10BrandIdString2,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PATCHES == TRUE
GetF10RbMicroCodePatchesStruct,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
GetF10RbMicrocodeEquivalenceTable,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_CACHE_INFO == TRUE
GetF10CacheInfo,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_SYSTEM_PM_TABLE == TRUE
GetF10SysPmTable,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_WHEA_INIT == TRUE
GetF10WheaInitData,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
F10GetPlatformTypeSpecificInfo,
#else
(PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
#endif
#if IS_NB_PSTATE_ENABLED == TRUE
F10CommonRevCIsNbPstateEnabled,
#else
(PF_IS_NB_PSTATE_ENABLED) CommonAssert,
#endif
#if (BASE_FAMILY_HT_PCI == TRUE)
F10DoesLinkHaveHtPhyFeats,
#else
(PF_DOES_LINK_HAVE_HTFPY_FEATS) CommonReturnFalse,
#endif
#if (BASE_FAMILY_HT_PCI == TRUE)
F10SetHtPhyRegister,
#else
(PF_SET_HT_PHY_REGISTER) CommonAssert,
#endif
#if BASE_FAMILY_PCI == TRUE
F10GetHtLinkFeatures,
#else
(PF_GET_HT_LINK_FEATURES) CommonAssert,
#endif
#if USES_REGISTER_TABLES == TRUE
(REGISTER_TABLE **) F10RbRegisterTables,
#else
NULL,
#endif
#if USES_REGISTER_TABLES == TRUE
(TABLE_ENTRY_TYPE_DESCRIPTOR *) F10RbTableEntryTypeDescriptors,
#else
NULL,
#endif
NULL,
#if AGESA_ENTRY_INIT_EARLY == TRUE
GetCommonEarlyInitOnCoreTable
#else
(PF_GET_EARLY_INIT_TABLE) CommonVoid
#endif
};
#define RB_SOCKETS 8
#define RB_MODULES 1
#define RB_RECOVERY_SOCKETS 1
#define RB_RECOVERY_MODULES 1
extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF10RbLogicalIdAndRev;
#define OPT_F10_RB_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF10RbLogicalIdAndRev,
#ifndef ADVCFG_PLATFORM_SOCKETS
#define ADVCFG_PLATFORM_SOCKETS RB_SOCKETS
#else
#if ADVCFG_PLATFORM_SOCKETS < RB_SOCKETS
#undef ADVCFG_PLATFORM_SOCKETS
#define ADVCFG_PLATFORM_SOCKETS RB_SOCKETS
#endif
#endif
#ifndef ADVCFG_PLATFORM_MODULES
#define ADVCFG_PLATFORM_MODULES RB_MODULES
#else
#if ADVCFG_PLATFORM_MODULES < RB_MODULES
#undef ADVCFG_PLATFORM_MODULES
#define ADVCFG_PLATFORM_MODULES RB_MODULES
#endif
#endif
#define OPT_F10_RB_CPU {AMD_FAMILY_10_RB, &cpuF10RbServices},
#else
#define OPT_F10_RB_CPU
#define OPT_F10_RB_ID
#endif
#else
#define OPT_F10_RB_CPU
#define OPT_F10_RB_ID
#endif
#else
#define OPT_F10_RB_CPU
#define OPT_F10_RB_ID
#endif
#else
#define OPT_F10_RB_CPU
#define OPT_F10_RB_ID
#endif

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/**
* @file
*
* Install of build option: HT Assist
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#ifndef _OPTION_HT_ASSIST_INSTALL_H_
#define _OPTION_HT_ASSIST_INSTALL_H_
#include "cpuHtAssist.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_HT_ASSIST_FEAT
#define F10_HT_ASSIST_SUPPORT
#define HT_ASSIST_AP_DISABLE_CACHE
#define HT_ASSIST_AP_ENABLE_CACHE
#if OPTION_HT_ASSIST == TRUE
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
#if OPTION_FAMILY10H_HY == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHtAssist;
#undef OPTION_HT_ASSIST_FEAT
#define OPTION_HT_ASSIST_FEAT &CpuFeatureHtAssist,
extern CONST HT_ASSIST_FAMILY_SERVICES ROMDATA F10HtAssist;
#undef F10_HT_ASSIST_SUPPORT
#define F10_HT_ASSIST_SUPPORT {AMD_FAMILY_10_HY, &F10HtAssist},
#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA HtAssistFamilyServiceArray[] =
{
F10_HT_ASSIST_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA HtAssistFamilyServiceTable =
{
(sizeof (HtAssistFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&HtAssistFamilyServiceArray[0]
};
#undef HT_ASSIST_AP_DISABLE_CACHE
#define HT_ASSIST_AP_DISABLE_CACHE {AP_LATE_TASK_DISABLE_CACHE, (IMAGE_ENTRY) DisableAllCaches},
#undef HT_ASSIST_AP_ENABLE_CACHE
#define HT_ASSIST_AP_ENABLE_CACHE {AP_LATE_TASK_ENABLE_CACHE, (IMAGE_ENTRY) EnableAllCaches},
#endif
#endif
#endif // _OPTION_HT_ASSIST_INSTALL_H_

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/**
* @file
*
* Install of build option: Ht
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#ifndef _OPTION_HT_INSTALL_H_
#define _OPTION_HT_INSTALL_H_
#include "Topology.h"
#include "htFeat.h"
#include "htInterface.h"
#include "htNb.h"
#include "htTopologies.h"
/*
* Advanced Option only, hardware socket naming is the preferred method.
*/
#ifdef BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP
#define CFG_SYSTEM_PHYSICAL_SOCKET_MAP (BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP)
#else
#define CFG_SYSTEM_PHYSICAL_SOCKET_MAP (NULL)
#endif
/*
* OPTION_IS_RECOVERY_HT is true if Basic API is being used.
*/
#ifndef OPTION_IS_RECOVERY_HT
#define OPTION_IS_RECOVERY_HT TRUE
#endif
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition.
*/
#ifndef OPTION_MULTISOCKET
#error BLDOPT: Option not defined: "OPTION_MULTISOCKET"
#endif
#ifndef OPTION_FAMILY10H
#ifndef OPTION_FAMILY12H
#ifndef OPTION_FAMILY14H
#error BLDOPT: No supported Family is defined (OPTION_FAMILYnnH)
#endif
#define OPTION_FAMILY12H FALSE
#endif
#define OPTION_FAMILY10H FALSE
#endif
#ifndef OPTION_FAMILY12H
#define OPTION_FAMILY12H FALSE
#endif
#ifndef OPTION_FAMILY14H
#define OPTION_FAMILY14H FALSE
#endif
/*
* Based on user level options, set Ht internal options.
* For now, Family 10h support will assume single module. For multi module,
* this will have to be changed to not set non-coherent only.
*/
#define OPTION_HT_NON_COHERENT_ONLY FALSE
#if (OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE)
/* Fusion Families do not need a non-coherent only option. */
#else
#if OPTION_MULTISOCKET == FALSE
#if OPTION_FAMILY10H == TRUE
#undef OPTION_HT_NON_COHERENT_ONLY
#define OPTION_HT_NON_COHERENT_ONLY TRUE
#endif
#endif
#endif
/*
* Macros will generate the correct item reference based on options
*/
#if AGESA_ENTRY_INIT_EARLY == TRUE
#if OPTION_HT_NON_COHERENT_ONLY == FALSE
#if OPTION_FAMILY10H == FALSE
#define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL
#define INTERNAL_HT_OPTION_FEATURES &HtFeaturesNone
#define INTERNAL_HT_OPTION_INTERFACE &HtInterfaceMapsOnly
#else
#define INTERNAL_HT_OPTION_FEATURES &HtFeaturesDefault
#define INTERNAL_HT_OPTION_INTERFACE &HtInterfaceDefault
#endif
#if OPTION_FAMILY10H == TRUE
#define INTERNAL_HT_OPTION_FAM10_NB &HtFam10NbDefault, &HtFam10RevDNbDefault,
#else
#define INTERNAL_HT_OPTION_FAM10_NB
#endif
#if OPTION_FAMILY12H == TRUE
#define INTERNAL_HT_OPTION_FAM12_NB &HtFam12Nb,
#else
#define INTERNAL_HT_OPTION_FAM12_NB
#endif
#if OPTION_FAMILY14H == TRUE
#define INTERNAL_HT_OPTION_FAM14_NB &HtFam14Nb,
#else
#define INTERNAL_HT_OPTION_FAM14_NB
#endif
#else
#define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL
#if (OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE)
#define INTERNAL_HT_OPTION_FEATURES &HtFeaturesNone
#define INTERNAL_HT_OPTION_INTERFACE &HtInterfaceMapsOnly
#else
#define INTERNAL_HT_OPTION_FEATURES &HtFeaturesNonCoherentOnly
#define INTERNAL_HT_OPTION_INTERFACE &HtInterfaceNonCoherentOnly
#endif
#if OPTION_FAMILY10H == TRUE
#define INTERNAL_HT_OPTION_FAM10_NB &HtFam10NbNonCoherentOnly,
#else
#define INTERNAL_HT_OPTION_FAM10_NB
#endif
#if OPTION_FAMILY12H == TRUE
#define INTERNAL_HT_OPTION_FAM12_NB &HtFam12Nb,
#else
#define INTERNAL_HT_OPTION_FAM12_NB
#endif
#if OPTION_FAMILY14H == TRUE
#define INTERNAL_HT_OPTION_FAM14_NB &HtFam14Nb,
#else
#define INTERNAL_HT_OPTION_FAM14_NB
#endif
#endif
#define INTERNAL_ONLY_NB_LIST_ITEM INTERNAL_ONLY_HT_OPTION_SUPPORTED_NBS,
#ifndef INTERNAL_ONLY_HT_OPTION_SUPPORTED_NBS
#undef INTERNAL_ONLY_NB_LIST_ITEM
#define INTERNAL_ONLY_NB_LIST_ITEM
#endif
/* Install the correct set of northbridge implementations. Each item provides its own comma, the last item
* is ok to have a comma because the final item (NULL) is added below.
*/
#define INTERNAL_HT_OPTION_SUPPORTED_NBS \
INTERNAL_ONLY_NB_LIST_ITEM \
INTERNAL_HT_OPTION_FAM10_NB \
INTERNAL_HT_OPTION_FAM12_NB \
INTERNAL_HT_OPTION_FAM14_NB
#else
#define INTERNAL_HT_OPTION_FEATURES NULL
#define INTERNAL_HT_OPTION_INTERFACE NULL
#define INTERNAL_HT_OPTION_SUPPORTED_NBS NULL
#define HT_OPTIONS_PLATFORM NULL
#define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL
#endif
#ifdef AGESA_ENTRY_INIT_EARLY
#if AGESA_ENTRY_INIT_EARLY == TRUE
extern HT_FEATURES HtFeaturesDefault;
extern HT_FEATURES HtFeaturesNonCoherentOnly;
extern HT_FEATURES HtFeaturesNone;
extern HT_INTERFACE HtInterfaceDefault;
extern HT_INTERFACE HtInterfaceNonCoherentOnly;
extern HT_INTERFACE HtInterfaceMapsOnly;
extern HT_INTERFACE HtInterfaceNone;
extern NORTHBRIDGE HtFam10NbDefault;
extern NORTHBRIDGE HtFam10RevDNbDefault;
extern NORTHBRIDGE HtFam10NbNonCoherentOnly;
extern NORTHBRIDGE HtFam12Nb;
extern NORTHBRIDGE HtFam14Nb;
extern NORTHBRIDGE HtFam10NbNone;
CONST VOID * CONST ROMDATA HtInstalledFamilyNorthbridgeList[] = {
INTERNAL_HT_OPTION_SUPPORTED_NBS
NULL
};
STATIC CONST AMD_HT_INTERFACE ROMDATA HtOptionsPlatform =
{
CFG_STARTING_BUSNUM, CFG_MAXIMUM_BUSNUM, CFG_ALLOCATED_BUSNUM,
(MANUAL_BUID_SWAP_LIST *)CFG_BUID_SWAP_LIST,
(DEVICE_CAP_OVERRIDE *)CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST,
(CPU_TO_CPU_PCB_LIMITS *)CFG_HTFABRIC_LIMITS_LIST,
(IO_PCB_LIMITS *)CFG_HTCHAIN_LIMITS_LIST,
(OVERRIDE_BUS_NUMBERS *)CFG_BUS_NUMBERS_LIST,
(IGNORE_LINK *)CFG_IGNORE_LINK_LIST,
(SKIP_REGANG *)CFG_LINK_SKIP_REGANG_LIST,
(UINT8 **)CFG_ADDITIONAL_TOPOLOGIES_LIST,
(SYSTEM_PHYSICAL_SOCKET_MAP *)CFG_SYSTEM_PHYSICAL_SOCKET_MAP
};
#ifndef HT_OPTIONS_PLATFORM
#define HT_OPTIONS_PLATFORM &HtOptionsPlatform
#endif
/**
* A list of all the supported topologies.
*
*/
#ifndef INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES
CONST UINT8 *CONST ROMDATA AmdTopolist[] =
{
amdHtTopologySingleNode,
amdHtTopologyDualNode,
amdHtTopologyThreeLine,
amdHtTopologyTriangle,
amdHtTopologyFourLine,
amdHtTopologyFourStar,
amdHtTopologyFourDegenerate,
amdHtTopologyFourSquare,
amdHtTopologyFourKite,
amdHtTopologyFourFully,
amdHtTopologyFiveFully,
amdHtTopologyFiveTwistedLadder,
amdHtTopologySixFully,
amdHtTopologySixDoubloonLower,
amdHtTopologySixDoubloonUpper,
amdHtTopologySixTwistedLadder,
amdHtTopologySevenFully,
amdHtTopologySevenTwistedLadder,
amdHtTopologyEightFully,
amdHtTopologyEightDoubloon,
amdHtTopologyEightTwistedLadder,
amdHtTopologyEightStraightLadder,
amdHtTopologySixTwinTriangles,
amdHtTopologyEightTwinFullyFourWays,
NULL
};
#define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES AmdTopolist
#endif
/**
* Declare the instance of the Ht option configuration structure
*/
CONST OPTION_HT_CONFIGURATION ROMDATA OptionHtConfiguration = {
OPTION_IS_RECOVERY_HT,
CFG_SET_HTCRC_SYNC_FLOOD,
CFG_USE_UNIT_ID_CLUMPING,
HT_OPTIONS_PLATFORM,
INTERNAL_HT_OPTION_INTERFACE,
INTERNAL_HT_OPTION_FEATURES,
&HtInstalledFamilyNorthbridgeList,
INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES
};
#endif
#endif
#ifndef OPTION_HT_INIIT_RESET_ENTRY
#define OPTION_HT_INIIT_RESET_ENTRY AmdHtInitReset
#if (OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE)
#undef OPTION_HT_INIIT_RESET_ENTRY
#define OPTION_HT_INIIT_RESET_ENTRY NULL
#endif
#if OPTION_FAMILY10H == TRUE
#undef OPTION_HT_INIIT_RESET_ENTRY
#define OPTION_HT_INIIT_RESET_ENTRY AmdHtInitReset
#endif
#endif
#ifdef AGESA_ENTRY_INIT_RESET
#if AGESA_ENTRY_INIT_RESET == TRUE
CONST AMD_HT_RESET_INTERFACE ROMDATA HtOptionResetDefaults = {
(MANUAL_BUID_SWAP_LIST *)CFG_BUID_SWAP_LIST,
0 // Unused by options
};
CONST OPTION_HT_INIT_RESET ROMDATA HtOptionInitReset = {
OPTION_HT_INIIT_RESET_ENTRY
};
#endif
#endif
#endif // _OPTION_HT_INSTALL_H_

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/**
* @file
*
* Install of build option: HW C1e
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#ifndef _OPTION_HW_C1E_INSTALL_H_
#define _OPTION_HW_C1E_INSTALL_H_
#include "cpuHwC1e.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_HW_C1E_FEAT
#define F10_HW_C1E_SUPPORT
#if AGESA_ENTRY_INIT_EARLY == TRUE
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
#if (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE) || (OPTION_FAMILY10H_RB == TRUE)
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHwC1e;
#undef OPTION_HW_C1E_FEAT
#define OPTION_HW_C1E_FEAT &CpuFeatureHwC1e,
extern CONST HW_C1E_FAMILY_SERVICES ROMDATA F10HwC1e;
#undef F10_HW_C1E_SUPPORT
#define F10_HW_C1E_SUPPORT {(AMD_FAMILY_10_BL | AMD_FAMILY_10_DA | AMD_FAMILY_10_RB), &F10HwC1e},
#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA HwC1eFamilyServiceArray[] =
{
F10_HW_C1E_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA HwC1eFamilyServiceTable =
{
(sizeof (HwC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&HwC1eFamilyServiceArray[0]
};
#endif
#endif // _OPTION_HW_C1E_INSTALL_H_

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@ -1,320 +0,0 @@
/**
* @file
*
* IDS Option Install File
*
* This file generates the defaults tables for family 10h model 5 processors.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#ifndef _OPTION_IDS_INSTALL_H_
#define _OPTION_IDS_INSTALL_H_
#include "Ids.h"
#include "IdsHt.h"
#include "IdsLib.h"
#ifdef __IDS_EXTENDED__
#include IDS_EXT_INCLUDE (OptionIdsInternalInstall)
#endif
#define IDS_LATE_RUN_AP_TASK
#define M_HTIDS_PORT_OVERRIDE_HOOK (PF_HtIdsGetPortOverride)CommonVoid
#if (IDSOPT_IDS_ENABLED == TRUE)
#if (IDSOPT_CONTROL_ENABLED == TRUE)
// Check for all families which include HT Features.
#if (OPTION_FAMILY10H == TRUE) && (AGESA_ENTRY_INIT_POST == TRUE)
#undef M_HTIDS_PORT_OVERRIDE_HOOK
#define M_HTIDS_PORT_OVERRIDE_HOOK HtIdsGetPortOverride
#endif
#endif
#endif // OPTION_IDS_LEVEL
CONST PF_HtIdsGetPortOverride ROMDATA pf_HtIdsGetPortOverride = M_HTIDS_PORT_OVERRIDE_HOOK;
#if (IDSOPT_IDS_ENABLED == TRUE)
#if (AGESA_ENTRY_INIT_LATE == TRUE)
#undef IDS_LATE_RUN_AP_TASK
#define IDS_LATE_RUN_AP_TASK {IDS_LATE_RUN_AP_TASK_ID, (IMAGE_ENTRY)AmdIdsRunApTaskLate},
#endif
#endif // OPTION_IDS_LEVEL
#if (IDSOPT_TRACING_ENABLED == TRUE)
#if (AGESA_ENTRY_INIT_POST == TRUE)
#include <mu.h>
CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
{ (UINTN) MemUWriteCachelines, "WriteCl(PhyAddrLo,BufferAddr,ClCnt)"},
{ (UINTN) MemUReadCachelines, "ReadCl(BufferAddr,PhyAddrLo,ClCnt)"},
{ (UINTN) MemUFlushPattern, "FlushCl(PhyAddrLo,ClCnt)"}
};
#elif (AGESA_ENTRY_INIT_RECOVERY == TRUE)
#include <mru.h>
CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
{ (UINTN) MemRecUWrite1CL, "Write1Cl(PhyAddrLo,BufferAddr)"},
{ (UINTN) MemRecURead1CL, "Read1Cl(BufferAddr,PhyAddrLo)"},
{ (UINTN) MemRecUFlushPattern, "Flush1Cl(PhyAddrLo)"}
};
#else
CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
{ (UINTN) CommonReturnFalse, "DefRet()"},
{ (UINTN) CommonReturnFalse, "DefRet()"},
{ (UINTN) CommonReturnFalse, "DefRet()"}
};
#endif
#endif
///Ids Feat Options
#if (IDSOPT_IDS_ENABLED == TRUE)
#if (IDSOPT_CONTROL_ENABLED == TRUE)
#ifndef OPTION_IDS_EXTEND_FEATS
#define OPTION_IDS_EXTEND_FEATS
#endif
#define OPTION_IDS_FEAT_ECCCTRL\
OPTION_IDS_FEAT_ECCCTRL_F10 \
OPTION_IDS_FEAT_ECCCTRL_F12
#define OPTION_IDS_FEAT_ECCSYMBOLSIZE
#define OPTION_IDS_FEAT_ECCCTRL_F10
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
//Ecc symbol size
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccSymbolSizeBlock =
{
IDS_FEAT_ECC_SYMBOL_SIZE,
IDS_BSP_ONLY,
IDS_ECCSYMBOLSIZE,
AMD_FAMILY_10,
IdsSubEccSymbolSize
};
#undef OPTION_IDS_FEAT_ECCSYMBOLSIZE
#define OPTION_IDS_FEAT_ECCSYMBOLSIZE &IdsFeatEccSymbolSizeBlock,
//ECC scrub control
extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF10;
#undef OPTION_IDS_FEAT_ECCCTRL_F10
#define OPTION_IDS_FEAT_ECCCTRL_F10 &IdsFeatEccCtrlBlockF10,
#endif
#endif
#define OPTION_IDS_FEAT_GNB_PLATFORMCFG
#ifdef OPTION_FAMILY12H
#if OPTION_FAMILY12H == TRUE
extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlock;
#undef OPTION_IDS_FEAT_GNB_PLATFORMCFG
#define OPTION_IDS_FEAT_GNB_PLATFORMCFG &IdsFeatGnbPlatformCfgBlock,
#endif
#endif
//Ids Feat for F12 only
#define OPTION_IDS_FEAT_ECCCTRL_F12
#ifdef OPTION_FAMILY12H
#if OPTION_FAMILY12H == TRUE
//ECC scrub control
extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF12;
#undef OPTION_IDS_FEAT_ECCCTRL_F12
#define OPTION_IDS_FEAT_ECCCTRL_F12 &IdsFeatEccCtrlBlockF12,
#endif
#endif
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatUcodeBlock =
{
IDS_FEAT_UCODE_UPDATE,
IDS_ALL_CORES,
IDS_UCODE,
IDS_FAMILY_ALL,
IdsSubUCode
};
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatTargetPstateBlock =
{
IDS_FEAT_TARGET_PSTATE,
IDS_BSP_ONLY,
IDS_INIT_LATE_AFTER,
IDS_FAMILY_ALL,
IdsSubTargetPstate
};
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatPostPstateBlock =
{
IDS_FEAT_POSTPSTATE,
IDS_ALL_CORES,
IDS_CPU_Early_Override,
IDS_FAMILY_ALL,
IdsSubPostPState
};
//Dram controller Features
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctAllMemClkBlock =
{
IDS_FEAT_DCT_ALLMEMCLK,
IDS_BSP_ONLY,
IDS_ALL_MEMORY_CLOCK,
AMD_FAMILY_10,
IdsSubAllMemClkEn
};
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctGangModeBlock =
{
IDS_FEAT_DCT_GANGMODE,
IDS_BSP_ONLY,
IDS_GANGING_MODE,
AMD_FAMILY_10,
IdsSubGangingMode
};
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctBurstLengthBlock =
{
IDS_FEAT_DCT_BURSTLENGTH,
IDS_BSP_ONLY,
IDS_BURST_LENGTH32,
AMD_FAMILY_10,
IdsSubBurstLength32
};
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctPowerDownCtrlBlock =
{
IDS_FEAT_DCT_POWERDOWN,
IDS_BSP_ONLY,
IDS_INIT_POST_BEFORE,
AMD_FAMILY_10,
IdsSubPowerDownCtrl
};
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctDllShutDownBlock =
{
IDS_FEAT_DCT_DLLSHUTDOWN,
IDS_BSP_ONLY,
IDS_DLL_SHUT_DOWN,
AMD_FAMILY_10,
IdsSubDllShutDownSR
};
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctPowerDownModeBlock =
{
IDS_FEAT_DCT_POWERDOWN,
IDS_BSP_ONLY,
IDS_POWERDOWN_MODE,
AMD_FAMILY_10,
IdsSubPowerDownMode
};
//Misc Features
#define OPTION_IDS_FEAT_PROBEFILTER
#ifdef OPTION_FAMILY10H_HY
#if OPTION_FAMILY10H_HY == TRUE
#undef OPTION_IDS_FEAT_PROBEFILTER
extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatProbeFilterBlockPlatformCfg;
extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatProbeFilterBlockEarlyBefore;
extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatProbeFilterBlockLateBefore;
#define OPTION_IDS_FEAT_PROBEFILTER \
&IdsFeatProbeFilterBlockPlatformCfg, \
&IdsFeatProbeFilterBlockEarlyBefore, \
&IdsFeatProbeFilterBlockLateBefore,
#endif
#endif
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHdtOutBlock =
{
IDS_FEAT_HDTOUT,
IDS_BSP_ONLY,
IDS_INIT_EARLY_BEFORE,
AMD_FAMILY_10,
IdsSubHdtOut
};
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtSettingBlock =
{
IDS_FEAT_HT_SETTING,
IDS_BSP_ONLY,
IDS_HT_CONTROL,
IDS_FAMILY_ALL,
IdsSubHtLinkControl
};
CONST IDS_FEAT_STRUCT* ROMDATA IdsCommonFeats[] =
{
&IdsFeatUcodeBlock,
&IdsFeatTargetPstateBlock,
&IdsFeatPostPstateBlock,
OPTION_IDS_FEAT_ECCSYMBOLSIZE
OPTION_IDS_FEAT_ECCCTRL
&IdsFeatDctAllMemClkBlock,
&IdsFeatDctGangModeBlock,
&IdsFeatDctBurstLengthBlock,
&IdsFeatDctPowerDownCtrlBlock,
&IdsFeatDctPowerDownModeBlock,
&IdsFeatDctPowerDownModeBlock,
OPTION_IDS_FEAT_PROBEFILTER
&IdsFeatHdtOutBlock,
&IdsFeatHtSettingBlock,
OPTION_IDS_FEAT_GNB_PLATFORMCFG
OPTION_IDS_EXTEND_FEATS
NULL
};
#else
CONST IDS_FEAT_STRUCT* ROMDATA IdsCommonFeats[] =
{
NULL
};
#endif//IDSOPT_CONTROL_ENABLED
#else
CONST IDS_FEAT_STRUCT* ROMDATA IdsCommonFeats[] =
{
NULL
};
#endif// IDSOPT_IDS_ENABLED
#endif

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/**
* @file
*
* Install microcode build options for a Lynx platform solution
*
* This file generates the defaults tables for the "Lynx" platform solution
* set of processors. The documented build options are imported from a user
* controlled file for processing.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#ifndef _OPTION_LYNX_MICROCODE_INSTALL_H_
#define _OPTION_LYNX_MICROCODE_INSTALL_H_
// Code goes here
#endif

57
src/vendorcode/amd/agesa/f10/Include/OptionMaranelloMicrocodeInstall.h
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@ -1,57 +0,0 @@
/**
* @file
*
* Install microcode build options for a Maranello platform solution
*
* This file generates the defaults tables for the "Maranello" platform solution
* set of processors. The documented build options are imported from a user
* controlled file for processing.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#ifndef _OPTION_MARANELLO_MICROCODE_INSTALL_H_
#define _OPTION_MARANELLO_MICROCODE_INSTALL_H_
extern CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c4;
// 'NULL' must be put at the end of MicroCodePatchArray[]
CONST MICROCODE_PATCHES ROMDATA *CpuF10HyMicroCodePatchArray[] =
{
&CpuF10MicrocodePatch010000c4,
NULL
};
#endif

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src/vendorcode/amd/agesa/f10/Include/OptionMemory.h
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/**
* @file
*
* AMD Memory option API.
*
* Contains structures and values used to control the Memory option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 5937 $ @e \$Date: 2008-04-25 03:59:36 -0700 (Fri, 25 Apr 2008) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef _OPTION_MEMORY_H_
#define _OPTION_MEMORY_H_
/* Memory Includes */
#include "mm.h"
#include "mn.h"
#include "mt.h"
#include "ma.h"
#include "mp.h"
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
#define MAX_FF_TYPES 6 ///< Maximum number of DDR Form factors (UDIMMs, RDIMMMs, SODIMMS) supported
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
/*
* STANDARD MEMORY FEATURE FUNCTION POINTER
*/
typedef BOOLEAN OPTION_MEM_FEATURE_NB (
IN OUT MEM_NB_BLOCK *NBPtr
);
typedef BOOLEAN MEM_TECH_FEAT (
IN OUT MEM_TECH_BLOCK *TechPtr
);
typedef UINT8 MEM_TABLE_FEAT (
IN OUT MEM_TABLE_ALIAS **MTPtr
);
#define MEM_FEAT_BLOCK_NB_STRUCT_VERSION 0x01
/**
* MEMORY FEATURE BLOCK - This structure serves as a vector table for standard
* memory feature implementation functions. It contains vectors for all of the
* features that are supported by the various Northbridge devices supported by
* AGESA.
*/
typedef struct _MEM_FEAT_BLOCK_NB {
UINT16 OptMemFeatVersion; ///< Version of memory feature block.
OPTION_MEM_FEATURE_NB *OnlineSpare; ///< Online spare support.
OPTION_MEM_FEATURE_NB *InterleaveBanks; ///< Bank (Chip select) interleaving support.
OPTION_MEM_FEATURE_NB *UndoInterleaveBanks; ///< Undo Bank (Chip Select) interleaving.
OPTION_MEM_FEATURE_NB *CheckInterleaveNodes; ///< Check for Node interleaving support.
OPTION_MEM_FEATURE_NB *InterleaveNodes; ///< Node interleaving support.
OPTION_MEM_FEATURE_NB *InterleaveChannels; ///< Channel interleaving support.
OPTION_MEM_FEATURE_NB *InterleaveRegion; ///< Interleave Region support.
OPTION_MEM_FEATURE_NB *CheckEcc; ///< Check for ECC support.
OPTION_MEM_FEATURE_NB *InitEcc; ///< ECC support.
OPTION_MEM_FEATURE_NB *Training; ///< Choose the type of training (Parallel, standard or hardcoded).
OPTION_MEM_FEATURE_NB *LvDdr3; ///< Low voltage DDR3 dimm support
OPTION_MEM_FEATURE_NB *OnDimmThermal; ///< On-Dimm thermal management
MEM_TECH_FEAT *DramInit; ///< Choose the type of Dram init (hardware based or software based).
OPTION_MEM_FEATURE_NB *ExcludeDIMM; ///< Exclude a dimm.
OPTION_MEM_FEATURE_NB *InitCPG; ///< Continuous pattern generation.
} MEM_FEAT_BLOCK_NB;
typedef AGESA_STATUS MEM_MAIN_FLOW_CONTROL (
IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
);
typedef BOOLEAN OPTION_MEM_FEATURE_MAIN (
IN MEM_MAIN_DATA_BLOCK *MMPtr
);
typedef BOOLEAN MEM_NB_CONSTRUCTOR (
IN OUT MEM_NB_BLOCK *NBPtr,
IN OUT MEM_DATA_STRUCT *MemPtr,
IN MEM_FEAT_BLOCK_NB *FeatPtr,
IN MEM_SHARED_DATA *mmSharedPtr, ///< Pointer to Memory scratchpad
IN UINT8 NodeID
);
typedef BOOLEAN MEM_TECH_CONSTRUCTOR (
IN OUT MEM_TECH_BLOCK *TechPtr,
IN OUT MEM_NB_BLOCK *NBPtr
);
typedef VOID MEM_INITIALIZER (
IN OUT MEM_DATA_STRUCT *MemPtr
);
typedef AGESA_STATUS MEM_PLATFORM_CFG (
IN struct _MEM_DATA_STRUCT *MemData,
IN UINT8 SocketID,
IN CH_DEF_STRUCT *CurrentChannel
);
typedef BOOLEAN MEM_IDENDIMM_CONSTRUCTOR (
IN OUT MEM_NB_BLOCK *NBPtr,
IN OUT MEM_DATA_STRUCT *MemPtr,
IN UINT8 NodeID
);
typedef VOID MEM_TECH_TRAINING_FEAT (
IN OUT MEM_TECH_BLOCK *TechPtr,
IN UINT8 Pass
);
typedef BOOLEAN MEM_RESUME_CONSTRUCTOR (
IN OUT VOID *S3NBPtr,
IN OUT MEM_DATA_STRUCT *MemPtr,
IN UINT8 NodeID
);
typedef AGESA_STATUS MEM_PLAT_SPEC_CFG (
IN struct _MEM_DATA_STRUCT *MemData,
IN OUT CH_DEF_STRUCT *CurrentChannel,
IN OUT MEM_PS_BLOCK *PsPtr
);
#define MEM_FEAT_BLOCK_MAIN_STRUCT_VERSION 0x01
/**
* MAIN FEATURE BLOCK - This structure serves as vector table for memory features
* that shared between all northbridge devices.
*/
typedef struct _MEM_FEAT_BLOCK_MAIN {
UINT16 OptMemFeatVersion; ///< Version of main feature block.
OPTION_MEM_FEATURE_MAIN *Training; ///< Training features.
OPTION_MEM_FEATURE_MAIN *ExcludeDIMM; ///< Exclude a dimm.
OPTION_MEM_FEATURE_MAIN *OnlineSpare; ///< On-line spare.
OPTION_MEM_FEATURE_MAIN *InterleaveNodes; ///< Node interleave.
OPTION_MEM_FEATURE_MAIN *InitEcc; ///< Initialize ECC on all nodes if they all support it.
OPTION_MEM_FEATURE_MAIN *MemClr; ///< Memory Clear.
OPTION_MEM_FEATURE_MAIN *MemDmi; ///< Memory DMI Support.
OPTION_MEM_FEATURE_MAIN *LvDDR3; ///< Low voltage DDR3 support.
OPTION_MEM_FEATURE_MAIN *UmaAllocation; ///< Uma Allocation.
OPTION_MEM_FEATURE_MAIN *MemSave; ///< Memory Context Save
OPTION_MEM_FEATURE_MAIN *MemRestore; ///< Memory Context Restore
} MEM_FEAT_BLOCK_MAIN;
#define MEM_NB_SUPPORT_STRUCT_VERSION 0x01
#define MEM_TECH_FEAT_BLOCK_STRUCT_VERSION 0x01
/**
* MEMORY TECHNOLOGY FEATURE BLOCK - This structure serves as a vector table for standard
* memory feature implementation functions. It contains vectors for all of the
* features that are supported by the various Technology features supported by
* AGESA.
*/
typedef struct _MEM_TECH_FEAT_BLOCK {
UINT16 OptMemTechFeatVersion; ///< Version of memory Tech feature block.
MEM_TECH_FEAT *EnterHardwareTraining; ///<Enter HW WL Training
MEM_TECH_FEAT *SwWLTraining; ///<SW Write Levelization training
MEM_TECH_FEAT *HwBasedWLTrainingPart1; ///<HW based write levelization Training Part 1
MEM_TECH_FEAT *HwBasedDQSReceiverEnableTrainingPart1; ///<HW based DQS receiver Enabled Training Part 1
MEM_TECH_FEAT *HwBasedWLTrainingPart2; ///<HW based write levelization Training Part 2
MEM_TECH_FEAT *HwBasedDQSReceiverEnableTrainingPart2; ///<HW based DQS receiver Enabled Training Part 2
MEM_TECH_FEAT *TrainExitHwTrn; ///<Exit HW WL Training
MEM_TECH_FEAT *NonOptimizedSWDQSRecEnTrainingPart1; ///< Non-Optimized Software based receiver Enable Training part 1
MEM_TECH_FEAT *OptimizedSwDqsRecEnTrainingPart1; ///< Optimized Software based receiver Enable Training part 1
MEM_TECH_FEAT *NonOptimizedSRdWrPosTraining; ///< Non-Optimized Rd Wr Position training
MEM_TECH_FEAT *OptimizedSRdWrPosTraining; ///< Optimized Rd Wr Position training
MEM_TECH_FEAT *MaxRdLatencyTraining; ///< MaxReadLatency Training
} MEM_TECH_FEAT_BLOCK;
/**
* MEMORY NORTHBRIDGE SUPPORT STRUCT - This structure groups the Northbridge dependent
* options together in a list to provide a single access point for all code to use
* and to ensure that everything corresponding to the same NB type is grouped together.
*
* The Technology Block pointers are not included in this structure because DRAM technology
* needs to be decoupled from the northbridge type.
*
*/
typedef struct _MEM_NB_SUPPORT {
UINT16 MemNBSupportVersion; ///< Version of northbridge support.
MEM_NB_CONSTRUCTOR *MemConstructNBBlock; ///< NorthBridge block constructor.
MEM_INITIALIZER *MemNInitDefaults; ///< Default value initialization for MEM_DATA_STRUCT.
MEM_FEAT_BLOCK_NB *MemFeatBlock; ///< Memory feature block.
MEM_RESUME_CONSTRUCTOR *MemS3ResumeConstructNBBlock; ///< S3 memory initialization northbridge block constructor.
MEM_IDENDIMM_CONSTRUCTOR *MemIdentifyDimmConstruct; ///< Constructor for address to dimm identification.
} MEM_NB_SUPPORT;
/*
* MEMORY Non-Training FEATURES - This structure serves as a vector table for standard
* memory non-training feature implementation functions. It contains vectors for all of the
* features that are supported by the various Technology devices supported by
* AGESA.
*/
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
/* Feature Default Return */
BOOLEAN MemFDefRet (
IN OUT MEM_NB_BLOCK *NBPtr
);
BOOLEAN MemMDefRet (
IN MEM_MAIN_DATA_BLOCK *MMPtr
);
/* Table Feature Default Return */
UINT8 MemFTableDefRet (
IN OUT MEM_TABLE_ALIAS **MTPtr
);
/* S3 Feature Default Return */
BOOLEAN MemFS3DefConstructorRet (
IN OUT VOID *S3NBPtr,
IN OUT MEM_DATA_STRUCT *MemPtr,
IN UINT8 NodeID
);
BOOLEAN
MemProcessConditionalOverrides (
IN PSO_TABLE *PlatformMemoryConfiguration,
IN OUT MEM_NB_BLOCK *NBPtr,
IN UINT8 PsoAction,
IN UINT8 Dimm
);
#endif // _OPTION_MEMORY_H_

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src/vendorcode/amd/agesa/f10/Include/OptionMemoryInstall.h
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/* $NoKeywords:$ */
/**
* @file
*
* AMD Memory option API.
*
* Contains structures and values used to control the Memory option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_MEMORY_RECOVERY_H_
#define _OPTION_MEMORY_RECOVERY_H_
#include "mm.h"
#include "mn.h"
#include "mt.h"
typedef BOOLEAN MEM_REC_NB_CONSTRUCTOR (
IN OUT MEM_NB_BLOCK *NBPtr,
IN OUT MEM_DATA_STRUCT *MemPtr,
IN UINT8 NodeID
);
typedef VOID MEM_REC_TECH_CONSTRUCTOR (
IN OUT MEM_TECH_BLOCK *TechPtr,
IN OUT MEM_NB_BLOCK *NBPtr
);
#endif // _OPTION_MEMORY_H_

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/**
* @file
*
* Install of build option: Memory
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 6049 $ @e \$Date: 2008-05-14 01:58:02 -0500 (Wed, 14 May 2008) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#ifndef _OPTION_MEMORY_RECOVERY_INSTALL_H_
#define _OPTION_MEMORY_RECOVERY_INSTALL_H_
#if (AGESA_ENTRY_INIT_RECOVERY == TRUE)
#define MEM_REC_NB_SUPPORT_OR
#if (OPTION_MEMCTLR_DR == TRUE)
extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockDR;
#define MEM_REC_NB_SUPPORT_DR MemRecConstructNBBlockDR,
#else
#define MEM_REC_NB_SUPPORT_DR
#endif
#if (OPTION_MEMCTLR_DA == TRUE)
extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockDA;
#define MEM_REC_NB_SUPPORT_DA MemRecConstructNBBlockDA,
#else
#define MEM_REC_NB_SUPPORT_DA
#endif
#if (OPTION_MEMCTLR_HY == TRUE)
extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockHY;
#define MEM_REC_NB_SUPPORT_HY MemRecConstructNBBlockHY,
#else
#define MEM_REC_NB_SUPPORT_HY
#endif
#if (OPTION_MEMCTLR_C32 == TRUE)
extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockC32;
#define MEM_REC_NB_SUPPORT_C32 MemRecConstructNBBlockC32,
#else
#define MEM_REC_NB_SUPPORT_C32
#endif
#if (OPTION_MEMCTLR_LN == TRUE)
extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockLN;
#define MEM_REC_NB_SUPPORT_LN MemRecConstructNBBlockLN,
#else
#define MEM_REC_NB_SUPPORT_LN
#endif
#if (OPTION_MEMCTLR_ON == TRUE)
extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockON;
#define MEM_REC_NB_SUPPORT_ON MemRecConstructNBBlockON,
#else
#define MEM_REC_NB_SUPPORT_ON
#endif
MEM_REC_NB_CONSTRUCTOR* MemRecNBInstalled[] = {
MEM_REC_NB_SUPPORT_DR
MEM_REC_NB_SUPPORT_DA
MEM_REC_NB_SUPPORT_HY
MEM_REC_NB_SUPPORT_C32
MEM_REC_NB_SUPPORT_LN
MEM_REC_NB_SUPPORT_OR
MEM_REC_NB_SUPPORT_ON
{0, NULL, NULL, NULL, NULL, NULL,},
};
#define MEM_REC_TECH_CONSTRUCTOR_DDR2
#if (OPTION_DDR3 == TRUE)
extern MEM_REC_TECH_CONSTRUCTOR MemRecConstructTechBlock3;
#define MEM_REC_TECH_CONSTRUCTOR_DDR3 MemRecConstructTechBlock3,
#else
#define MEM_REC_TECH_CONSTRUCTOR_DDR3
#endif
MEM_REC_TECH_CONSTRUCTOR* MemRecTechInstalled[] = {
MEM_REC_TECH_CONSTRUCTOR_DDR3
MEM_REC_TECH_CONSTRUCTOR_DDR2
NULL
};
#else
/*---------------------------------------------------------------------------------------------------
* DEFAULT TECHNOLOGY BLOCK
*
*
*---------------------------------------------------------------------------------------------------
*/
MEM_TECH_CONSTRUCTOR* MemRecTechInstalled[] = { // Types of technology installed
NULL
};
/*---------------------------------------------------------------------------------------------------
* DEFAULT NORTHBRIDGE SUPPORT LIST
*
*
*---------------------------------------------------------------------------------------------------
*/
MEM_NB_SUPPORT MemRecNBInstalled[] = {
{0, NULL, NULL, NULL, NULL, NULL,},
};
#endif
#endif // _OPTION_MEMORY_RECOVERY_INSTALL_H_

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/**
* @file
*
* Install of build option: Message-Based C1e
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#ifndef _OPTION_MSG_BASED_C1E_INSTALL_H_
#define _OPTION_MSG_BASED_C1E_INSTALL_H_
#include "cpuMsgBasedC1e.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_MSG_BASED_C1E_FEAT
#define F10_MSG_BASED_C1E_SUPPORT
#if OPTION_MSG_BASED_C1E == TRUE
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE)
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
#if OPTION_FAMILY10H_HY == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureMsgBasedC1e;
#undef OPTION_MSG_BASED_C1E_FEAT
#define OPTION_MSG_BASED_C1E_FEAT &CpuFeatureMsgBasedC1e,
extern CONST MSG_BASED_C1E_FAMILY_SERVICES ROMDATA F10MsgBasedC1e;
#undef F10_MSG_BASED_C1E_SUPPORT
#define F10_MSG_BASED_C1E_SUPPORT {AMD_FAMILY_10_HY, &F10MsgBasedC1e},
#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA MsgBasedC1eFamilyServiceArray[] =
{
F10_MSG_BASED_C1E_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA MsgBasedC1eFamilyServiceTable =
{
(sizeof (MsgBasedC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&MsgBasedC1eFamilyServiceArray[0]
};
#endif
#endif
#endif // _OPTION_MSG_BASED_C1E_INSTALL_H_

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src/vendorcode/amd/agesa/f10/Include/OptionMultiSocket.h
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/**
* @file
*
* AMD Multi-socket option API.
*
* Contains structures and values used to control the multi-socket option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 5937 $ @e \$Date: 2008-04-25 03:59:36 -0700 (Fri, 25 Apr 2008) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef _OPTION_MULTISOCKET_H_
#define _OPTION_MULTISOCKET_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
/**
* This function loops through all possible socket locations, gathering the number
* of power management steps each populated socket requires, and returns the
* highest number.
*
* @param[out] NumSystemSteps Maximum number of system steps required
* @param[in] StdHeader Config handle for library and services
*
*/
typedef VOID OPTION_MULTISOCKET_PM_STEPS (
OUT UINT8 *NumSystemSteps,
IN AMD_CONFIG_PARAMS *StdHeader
);
/**
* This function loops through all possible socket locations, starting core 0 of
* each populated socket to perform the passed in AP_TASK. After starting all
* other core 0s, the BSC will perform the AP_TASK as well. This must be run by
* the system BSC only.
*
* @param[in] TaskPtr Function descriptor
* @param[in] StdHeader Config handle for library and services
* @param[in] ConfigParams AMD entry point's CPU parameter structure
*
*/
typedef VOID OPTION_MULTISOCKET_PM_CORE0_TASK (
IN VOID *TaskPtr,
IN AMD_CONFIG_PARAMS *StdHeader,
IN VOID *ConfigParams
);
/**
* This function loops through all possible socket locations, comparing the
* maximum NB frequencies to determine the slowest. This function also
* determines if all coherent NB frequencies are equivalent.
*
* @param[out] SystemNbCof NB frequency for the system in MHz
* @param[out] SystemNbCofsMatch Whether or not all NB frequencies are equivalent
* @param[in] StdHeader Config handle for library and services
*
*/
typedef AGESA_STATUS OPTION_MULTISOCKET_PM_NB_COF (
OUT UINT32 *SystemNbCof,
OUT BOOLEAN *SystemNbCofsMatch,
IN AMD_CONFIG_PARAMS *StdHeader
);
/**
* This function loops through all possible socket locations, checking whether
* any populated sockets require NB COF VID programming.
*
* @param[in] StdHeader Config handle for library and services
*
*/
typedef BOOLEAN OPTION_MULTISOCKET_PM_NB_COF_UPDATE (
IN AMD_CONFIG_PARAMS *StdHeader
);
/**
* This function loops through all possible socket locations, collecting any
* power management initialization errors that may have occurred. These errors
* are transferred from the core 0s of the socket in which the errors occurred
* to the BSC's heap. The BSC's heap is then searched for the most severe error
* that occurred, and returns it. This function must be called by the BSC only.
*
* @param[in] StdHeader Config handle for library and services
*
*/
typedef AGESA_STATUS OPTION_MULTISOCKET_PM_GET_EVENTS (
IN AMD_CONFIG_PARAMS *StdHeader
);
#define MULTISOCKET_STRUCT_VERSION 0x01
/**
* Provide build configuration of cpu multi-socket or single socket support.
*
*/
typedef struct {
UINT16 OptMultiSocketVersion; ///< Table version
OPTION_MULTISOCKET_PM_STEPS *GetNumberOfSystemPmSteps; ///< Method: Get number of power mgt tasks
OPTION_MULTISOCKET_PM_CORE0_TASK *BscRunCodeOnAllSystemCore0s; ///< Method: Perform tasks on Core 0 of each processor
OPTION_MULTISOCKET_PM_NB_COF *GetSystemNbCof; ///< Method: Find the limiting Northbridge frequency in the system.
OPTION_MULTISOCKET_PM_NB_COF_UPDATE *GetSystemNbCofVidUpdate; ///< Method: Determine if any Northbridges in the system need to update their COF/VID.
OPTION_MULTISOCKET_PM_GET_EVENTS *BscRetrievePmEarlyInitErrors; ///< Method: Gathers error information from all Core 0s.
} OPTION_MULTISOCKET_CONFIGURATION;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_MULTISOCKET_H_

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/**
* @file
*
* Install of build option: Multiple Socket Support
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 6049 $ @e \$Date: 2008-05-14 01:58:02 -0500 (Wed, 14 May 2008) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#ifndef _OPTION_MULTISOCKET_INSTALL_H_
#define _OPTION_MULTISOCKET_INSTALL_H_
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#ifndef OPTION_MULTISOCKET
#error BLDOPT: Option not defined: "OPTION_MULTISOCKET"
#endif
#if OPTION_MULTISOCKET == TRUE
OPTION_MULTISOCKET_PM_STEPS GetNumberOfSystemPmStepsPtrMulti;
#define GET_NUM_PM_STEPS GetNumberOfSystemPmStepsPtrMulti
OPTION_MULTISOCKET_PM_CORE0_TASK RunCodeOnAllSystemCore0sMulti;
#define CORE0_PM_TASK RunCodeOnAllSystemCore0sMulti
OPTION_MULTISOCKET_PM_NB_COF GetSystemNbCofMulti;
#define GET_SYS_NB_COF GetSystemNbCofMulti
OPTION_MULTISOCKET_PM_NB_COF_UPDATE GetSystemNbCofVidUpdateMulti;
#define GET_SYS_NB_COF_UPDATE GetSystemNbCofVidUpdateMulti
OPTION_MULTISOCKET_PM_GET_EVENTS GetEarlyPmErrorsMulti;
#define GET_EARLY_PM_ERRORS GetEarlyPmErrorsMulti
#else
OPTION_MULTISOCKET_PM_STEPS GetNumberOfSystemPmStepsPtrSingle;
#define GET_NUM_PM_STEPS GetNumberOfSystemPmStepsPtrSingle
OPTION_MULTISOCKET_PM_CORE0_TASK RunCodeOnAllSystemCore0sSingle;
#define CORE0_PM_TASK RunCodeOnAllSystemCore0sSingle
OPTION_MULTISOCKET_PM_NB_COF GetSystemNbCofSingle;
#define GET_SYS_NB_COF GetSystemNbCofSingle
OPTION_MULTISOCKET_PM_NB_COF_UPDATE GetSystemNbCofVidUpdateSingle;
#define GET_SYS_NB_COF_UPDATE GetSystemNbCofVidUpdateSingle
OPTION_MULTISOCKET_PM_GET_EVENTS GetEarlyPmErrorsSingle;
#define GET_EARLY_PM_ERRORS GetEarlyPmErrorsSingle
#endif
/* Declare the instance of the DMI option configuration structure */
OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration = {
MULTISOCKET_STRUCT_VERSION,
GET_NUM_PM_STEPS,
CORE0_PM_TASK,
GET_SYS_NB_COF,
GET_SYS_NB_COF_UPDATE,
GET_EARLY_PM_ERRORS
};
#endif // _OPTION_MULTISOCKET_INSTALL_H_

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src/vendorcode/amd/agesa/f10/Include/OptionNileMicrocodeInstall.h
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@ -1,63 +0,0 @@
/**
* @file
*
* Install microcode build options for a Nile platform solution
*
* This file generates the defaults tables for the "Nile" platform solution
* set of processors. The documented build options are imported from a user
* controlled file for processing.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#ifndef _OPTION_NILE_MICROCODE_INSTALL_H_
#define _OPTION_NILE_MICROCODE_INSTALL_H_
extern CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000b6;
// 'NULL' must be put at the end of MicroCodePatchArray[]
CONST MICROCODE_PATCHES ROMDATA *CpuF10BlMicroCodePatchArray[] =
{
&CpuF10MicrocodePatch010000b6,
NULL
};
CONST MICROCODE_PATCHES ROMDATA *CpuF10DaMicroCodePatchArray[] =
{
&CpuF10MicrocodePatch010000b6,
NULL
};
#endif

87
src/vendorcode/amd/agesa/f10/Include/OptionPreserveMailboxInstall.h
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@ -1,87 +0,0 @@
/**
* @file
*
* Install of build option: Preserve Mailbox
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#ifndef _OPTION_PRESERVE_MAILBOX_INSTALL_H_
#define _OPTION_PRESERVE_MAILBOX_INSTALL_H_
#include "PreserveMailbox.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_PRESERVE_MAILBOX_FEAT
#define F10_PRESERVE_MAILBOX_SUPPORT
#if ((AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE))
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePreserveAroundMailbox;
#undef OPTION_PRESERVE_MAILBOX_FEAT
#define OPTION_PRESERVE_MAILBOX_FEAT &CpuFeaturePreserveAroundMailbox,
CONST PCI_ADDR ROMDATA F10PreserveMailboxRegisters [] = {
{MAKE_SBDFO (0, 0, 0, 3, 0x168)},
{MAKE_SBDFO (0, 0, 0, 3, 0x170)},
{ILLEGAL_SBDFO}
};
CONST PRESERVE_MAILBOX_FAMILY_SERVICES ROMDATA F10PreserveMailboxServices = {
0,
TRUE,
(PCI_ADDR *)&F10PreserveMailboxRegisters
};
#undef F10_PRESERVE_MAILBOX_SUPPORT
#define F10_PRESERVE_MAILBOX_SUPPORT {AMD_FAMILY_10, &F10PreserveMailboxServices},
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PreserveMailboxFamilyServiceArray[] =
{
F10_PRESERVE_MAILBOX_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PreserveMailboxFamilyServiceTable =
{
(sizeof (PreserveMailboxFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&PreserveMailboxFamilyServiceArray[0]
};
#endif
#endif // _OPTION_PRESERVE_MAILBOX_INSTALL_H_

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src/vendorcode/amd/agesa/f10/Include/OptionPstate.h
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@ -1,103 +0,0 @@
/**
* @file
*
* AMD ACPI PState option API.
*
* Contains structures and values used to control the PStates option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 5937 $ @e \$Date: 2008-04-25 03:59:36 -0700 (Fri, 25 Apr 2008) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef _OPTION_PSTATE_H_
#define _OPTION_PSTATE_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
typedef AGESA_STATUS OPTION_PSTATE_FEATURE (
IN AMD_CONFIG_PARAMS *StdHeader,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN OUT VOID **AcpiPstatePtr
);
typedef AGESA_STATUS OPTION_PSTATE_GATHER (
IN AMD_CONFIG_PARAMS *StdHeader,
IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr
);
typedef AGESA_STATUS OPTION_PSTATE_LEVELING (
IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr,
IN AMD_CONFIG_PARAMS *StdHeader
);
#define PSTATE_STRUCT_VERSION 0x01
/// Indirection vectors for POST/PEI PState code
typedef struct {
UINT16 OptPstateVersion; ///< revision of this structure
OPTION_PSTATE_GATHER *PstateGather; ///< vector for data gathering routine
OPTION_PSTATE_LEVELING *PstateLeveling; ///< vector for leveling routine
} OPTION_PSTATE_POST_CONFIGURATION;
/// Indirection vectors for LATE/DXE PState code
typedef struct {
UINT16 OptPstateVersion; ///< revision of this structure
OPTION_PSTATE_FEATURE *PstateFeature; ///< vector for main routine
BOOLEAN CfgPstatePpc; ///< boolean for creating _PPC method
BOOLEAN CfgPstatePct; ///< boolean for creating _PCT method
BOOLEAN CfgPstatePsd; ///< boolean for creating _PSD method
BOOLEAN CfgPstatePss; ///< boolean for creating _PSS method
BOOLEAN CfgPstateXpss; ///< boolean for creating _XPSS method
} OPTION_PSTATE_LATE_CONFIGURATION;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_PSTATE_H_

209
src/vendorcode/amd/agesa/f10/Include/OptionPstateInstall.h
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@ -1,209 +0,0 @@
/**
* @file
*
* Install of build option: PState
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 6049 $ @e \$Date: 2008-05-14 01:58:02 -0500 (Wed, 14 May 2008) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#ifndef _OPTION_PSTATE_INSTALL_H_
#define _OPTION_PSTATE_INSTALL_H_
#include "cpuPstateTables.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define F10_PSTATE_SERVICE_SUPPORT
#define F12_PSTATE_SERVICE_SUPPORT
#define F14_PSTATE_SERVICE_SUPPORT
#define F15_PSTATE_SERVICE_SUPPORT
#if ((AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE))
//
//Define Pstate CPU Family service
//
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F10PstateServices;
#undef F10_PSTATE_SERVICE_SUPPORT
#define F10_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_10, &F10PstateServices},
#endif
#endif
#ifdef OPTION_FAMILY12H
#if OPTION_FAMILY12H == TRUE
extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F12PstateServices;
#undef F12_PSTATE_SERVICE_SUPPORT
#define F12_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_12, &F12PstateServices},
#endif
#endif
#ifdef OPTION_FAMILY14H
#if OPTION_FAMILY14H == TRUE
extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F14PstateServices;
#undef F14_PSTATE_SERVICE_SUPPORT
#define F14_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_14, &F14PstateServices},
#endif
#endif
#ifdef OPTION_FAMILY15H
#if OPTION_FAMILY15H == TRUE
extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F15PstateServices;
#undef F15_PSTATE_SERVICE_SUPPORT
#define F15_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_15, &F15PstateServices},
#endif
#endif
//
//Define ACPI Pstate objects.
//
#ifndef OPTION_ACPI_PSTATES
#error BLDOPT: Option not defined: "OPTION_ACPI_PSTATES"
#endif
#if OPTION_ACPI_PSTATES == TRUE
#ifndef OPTION_MULTISOCKET
#error BLDOPT: Option not defined: "OPTION_MULTISOCKET"
#endif
OPTION_PSTATE_FEATURE CreateAcpiTablesMain;
OPTION_PSTATE_GATHER PStateGatherMain;
#if ((OPTION_MULTISOCKET == TRUE) && (AGESA_ENTRY_INIT_POST == TRUE))
OPTION_PSTATE_LEVELING PStateLevelingMain;
#define USER_PSTATE_OPTION_LEVEL PStateLevelingMain
#else
OPTION_PSTATE_LEVELING PStateLevelingStub;
#define USER_PSTATE_OPTION_LEVEL PStateLevelingStub
#endif
#if AGESA_ENTRY_INIT_LATE == TRUE
#define USER_PSTATE_OPTION_MAIN CreateAcpiTablesMain
#else
OPTION_PSTATE_FEATURE CreateAcpiTablesStub;
#define USER_PSTATE_OPTION_MAIN CreateAcpiTablesStub
#endif
#if AGESA_ENTRY_INIT_POST == TRUE
#define USER_PSTATE_OPTION_GATHER PStateGatherMain
#else
OPTION_PSTATE_GATHER PStateGatherStub;
#define USER_PSTATE_OPTION_GATHER PStateGatherStub
#endif
#if CFG_ACPI_PSTATES_PPC == TRUE
#define USER_PSTATE_CFG_PPC TRUE
#else
#define USER_PSTATE_CFG_PPC FALSE
#endif
#if CFG_ACPI_PSTATES_PCT == TRUE
#define USER_PSTATE_CFG_PCT TRUE
#else
#define USER_PSTATE_CFG_PCT FALSE
#endif
#if CFG_ACPI_PSTATES_PSD == TRUE
#define USER_PSTATE_CFG_PSD TRUE
#else
#define USER_PSTATE_CFG_PSD FALSE
#endif
#if CFG_ACPI_PSTATES_PSS == TRUE
#define USER_PSTATE_CFG_PSS TRUE
#else
#define USER_PSTATE_CFG_PSS FALSE
#endif
#if CFG_ACPI_PSTATES_XPSS == TRUE
#define USER_PSTATE_CFG_XPSS TRUE
#else
#define USER_PSTATE_CFG_XPSS FALSE
#endif
#else
OPTION_PSTATE_FEATURE CreateAcpiTablesStub;
OPTION_PSTATE_GATHER PStateGatherStub;
OPTION_PSTATE_LEVELING PStateLevelingStub;
#define USER_PSTATE_OPTION_MAIN CreateAcpiTablesStub
#define USER_PSTATE_OPTION_GATHER PStateGatherStub
#define USER_PSTATE_OPTION_LEVEL PStateLevelingStub
#define USER_PSTATE_CFG_PPC FALSE
#define USER_PSTATE_CFG_PCT FALSE
#define USER_PSTATE_CFG_PSD FALSE
#define USER_PSTATE_CFG_PSS FALSE
#define USER_PSTATE_CFG_XPSS FALSE
#endif
#else
OPTION_PSTATE_FEATURE CreateAcpiTablesStub;
OPTION_PSTATE_GATHER PStateGatherStub;
OPTION_PSTATE_LEVELING PStateLevelingStub;
#define USER_PSTATE_OPTION_MAIN CreateAcpiTablesStub
#define USER_PSTATE_OPTION_GATHER PStateGatherStub
#define USER_PSTATE_OPTION_LEVEL PStateLevelingStub
#define USER_PSTATE_CFG_PPC FALSE
#define USER_PSTATE_CFG_PCT FALSE
#define USER_PSTATE_CFG_PSD FALSE
#define USER_PSTATE_CFG_PSS FALSE
#define USER_PSTATE_CFG_XPSS FALSE
#endif
/* Declare the instance of the PSTATE option configuration structure */
OPTION_PSTATE_POST_CONFIGURATION OptionPstatePostConfiguration = {
PSTATE_STRUCT_VERSION,
USER_PSTATE_OPTION_GATHER,
USER_PSTATE_OPTION_LEVEL
};
OPTION_PSTATE_LATE_CONFIGURATION OptionPstateLateConfiguration = {
PSTATE_STRUCT_VERSION,
USER_PSTATE_OPTION_MAIN,
USER_PSTATE_CFG_PPC,
USER_PSTATE_CFG_PCT,
USER_PSTATE_CFG_PSD,
USER_PSTATE_CFG_PSS,
USER_PSTATE_CFG_XPSS
};
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PstateCpuFamilyServiceArray[] =
{
F10_PSTATE_SERVICE_SUPPORT
F12_PSTATE_SERVICE_SUPPORT
F14_PSTATE_SERVICE_SUPPORT
F15_PSTATE_SERVICE_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PstateFamilyServiceTable =
{
(sizeof (PstateCpuFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&PstateCpuFamilyServiceArray[0]
};
#endif // _OPTION_PSTATE_INSTALL_H_

91
src/vendorcode/amd/agesa/f10/Include/OptionS3ScriptInstall.h
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@ -1,91 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: S3SCRIPT
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_S3SCRIPT_INSTALL_H_
#define _OPTION_S3SCRIPT_INSTALL_H_
#include "S3SaveState.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#ifndef OPTION_S3SCRIPT
#define OPTION_S3SCRIPT FALSE //if not define assume PI not use script
#endif
#if (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_ENV == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE)
#if OPTION_S3SCRIPT == TRUE
#define P_S3_SCRIPT_INIT S3ScriptInitState
#endif
#endif
#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
#if OPTION_S3SCRIPT == TRUE
#define P_S3_SCRIPT_RESTORE S3ScriptRestoreState
#endif
#endif
#ifndef P_S3_SCRIPT_INIT
#define P_S3_SCRIPT_INIT S3ScriptInitStateStub
#endif
#ifndef P_S3_SCRIPT_RESTORE
#define P_S3_SCRIPT_RESTORE S3ScriptInitStateStub
#undef GNB_S3_DISPATCH_FUNCTION_TABLE
#endif
#ifndef GNB_S3_DISPATCH_FUNCTION_TABLE
#define GNB_S3_DISPATCH_FUNCTION_TABLE
#endif
/* Declare the instance of the S3SCRIPT option configuration structure */
S3_SCRIPT_CONFIGURATION OptionS3ScriptConfiguration = {
P_S3_SCRIPT_INIT,
P_S3_SCRIPT_RESTORE
};
S3_DISPATCH_FUNCTION_ENTRY S3DispatchFunctionTable [] = {
GNB_S3_DISPATCH_FUNCTION_TABLE
{0, NULL}
};
#endif // _OPTION_S3SCRIPT_INSTALL_H_

60
src/vendorcode/amd/agesa/f10/Include/OptionSanMarinoMicrocodeInstall.h
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@ -1,60 +0,0 @@
/**
* @file
*
* Install microcode build options for a SanMarino platform solution
*
* This file generates the defaults tables for the "SanMarino" platform solution
* set of processors. The documented build options are imported from a user
* controlled file for processing.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#ifndef _OPTION_SANMARINO_MICROCODE_INSTALL_H_
#define _OPTION_SANMARINO_MICROCODE_INSTALL_H_
extern CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c4;
extern CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c5;
// 'NULL' must be put at the end of MicroCodePatchArray[]
CONST MICROCODE_PATCHES ROMDATA *CpuF10HyMicroCodePatchArray[] =
{
&CpuF10MicrocodePatch010000c4,
&CpuF10MicrocodePatch010000c5,
NULL
};
#endif

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src/vendorcode/amd/agesa/f10/Include/OptionSlit.h
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@ -1,96 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD SLIT option API.
*
* Contains structures and values used to control the SLIT option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_SLIT_H_
#define _OPTION_SLIT_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
/**
* Create the ACPI System Locality Distance Information Table.
*
*/
typedef AGESA_STATUS OPTION_SLIT_FEATURE (
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN OUT VOID **SlitPtr
);
/**
* Clean up DRAM used during SLIT creation.
*
*/
typedef AGESA_STATUS OPTION_SLIT_RELEASE_BUFFER (
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
#define SLIT_STRUCT_VERSION 0x01
/// The Option Configuration of SLIT
typedef struct {
UINT16 OptSlitVersion; ///< The version number of SLIT
OPTION_SLIT_FEATURE *SlitFeature; ///< The Option Feature of SLIT
OPTION_SLIT_RELEASE_BUFFER *SlitReleaseBuffer; ///< Release buffer
} OPTION_SLIT_CONFIGURATION;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_SLIT_H_

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: SLIT
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_SLIT_INSTALL_H_
#define _OPTION_SLIT_INSTALL_H_
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#if AGESA_ENTRY_INIT_LATE == TRUE
#ifndef OPTION_SLIT
#error BLDOPT: Option not defined: "OPTION_SLIT"
#endif
#if OPTION_SLIT == TRUE
OPTION_SLIT_FEATURE GetAcpiSlitMain;
OPTION_SLIT_RELEASE_BUFFER ReleaseSlitBuffer;
#define USER_SLIT_OPTION GetAcpiSlitMain
#define USER_SLIT_RELEASE_BUFFER ReleaseSlitBuffer
#else
OPTION_SLIT_FEATURE GetAcpiSlitStub;
OPTION_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub;
#define USER_SLIT_OPTION GetAcpiSlitStub
#define USER_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub
#endif
#else
OPTION_SLIT_FEATURE GetAcpiSlitStub;
OPTION_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub;
#define USER_SLIT_OPTION GetAcpiSlitStub
#define USER_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub
#endif
/* Declare the instance of the SLIT option configuration structure */
OPTION_SLIT_CONFIGURATION OptionSlitConfiguration = {
SLIT_STRUCT_VERSION,
USER_SLIT_OPTION,
USER_SLIT_RELEASE_BUFFER
};
#endif // _OPTION_SLIT_INSTALL_H_

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@ -1,82 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD SRAT option API.
*
* Contains structures and values used to control the SRAT option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_SRAT_H_
#define _OPTION_SRAT_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
typedef AGESA_STATUS OPTION_SRAT_FEATURE (
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN OUT VOID **SratPtr
);
#define SRAT_STRUCT_VERSION 0x01
/// The Option Configuration of SRAT
typedef struct {
UINT16 OptSratVersion; ///< The version number of SRAT
OPTION_SRAT_FEATURE *SratFeature; ///< The Option Feature of SRAT
} OPTION_SRAT_CONFIGURATION;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_SRAT_H_

73
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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: SRAT
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_SRAT_INSTALL_H_
#define _OPTION_SRAT_INSTALL_H_
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#if AGESA_ENTRY_INIT_LATE == TRUE
#ifndef OPTION_SRAT
#error BLDOPT: Option not defined: "OPTION_SRAT"
#endif
#if OPTION_SRAT == TRUE
OPTION_SRAT_FEATURE GetAcpiSratMain;
#define USER_SRAT_OPTION GetAcpiSratMain
#else
OPTION_SRAT_FEATURE GetAcpiSratStub;
#define USER_SRAT_OPTION GetAcpiSratStub
#endif
#else
OPTION_SRAT_FEATURE GetAcpiSratStub;
#define USER_SRAT_OPTION GetAcpiSratStub
#endif
/* Declare the instance of the WHEA option configuration structure */
OPTION_SRAT_CONFIGURATION OptionSratConfiguration = {
SRAT_STRUCT_VERSION,
USER_SRAT_OPTION
};
#endif // _OPTION_WHEA_INSTALL_H_

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/**
* @file
*
* Install microcode build options for a Tigris platform solution
*
* This file generates the defaults tables for the "Tigris" platform solution
* set of processors. The documented build options are imported from a user
* controlled file for processing.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#ifndef _OPTION_TIGRIS_MICROCODE_INSTALL_H_
#define _OPTION_TIGRIS_MICROCODE_INSTALL_H_
extern CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch01000098;
// 'NULL' must be put at the end of MicroCodePatchArray[]
CONST MICROCODE_PATCHES ROMDATA *CpuF10BlMicroCodePatchArray[] =
{
&CpuF10MicrocodePatch01000098,
NULL
};
CONST MICROCODE_PATCHES ROMDATA *CpuF10DaMicroCodePatchArray[] =
{
&CpuF10MicrocodePatch01000098,
NULL
};
#endif

83
src/vendorcode/amd/agesa/f10/Include/OptionWhea.h
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@ -1,83 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD WHEA option API.
*
* Contains structures and values used to control the WHEA option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_WHEA_H_
#define _OPTION_WHEA_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
typedef AGESA_STATUS OPTION_WHEA_FEATURE (
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN OUT VOID **WheaMcePtr,
IN OUT VOID **WheaCmcPtr
);
#define WHEA_STRUCT_VERSION 0x01
/// The Option Configuration of WHEA
typedef struct {
UINT16 OptWheaVersion; ///< The version number of WHEA
OPTION_WHEA_FEATURE *WheaFeature; ///< The Option Feature of WHEA
} OPTION_WHEA_CONFIGURATION;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_WHEA_H_

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: WHEA
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_WHEA_INSTALL_H_
#define _OPTION_WHEA_INSTALL_H_
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#if AGESA_ENTRY_INIT_LATE == TRUE
#ifndef OPTION_WHEA
#error BLDOPT: Option not defined: "OPTION_WHEA"
#endif
#if OPTION_WHEA == TRUE
OPTION_WHEA_FEATURE GetAcpiWheaMain;
#define USER_WHEA_OPTION GetAcpiWheaMain
#else
OPTION_WHEA_FEATURE GetAcpiWheaStub;
#define USER_WHEA_OPTION GetAcpiWheaStub
#endif
#else
OPTION_WHEA_FEATURE GetAcpiWheaStub;
#define USER_WHEA_OPTION GetAcpiWheaStub
#endif
/* Declare the instance of the WHEA option configuration structure */
OPTION_WHEA_CONFIGURATION OptionWheaConfiguration = {
WHEA_STRUCT_VERSION,
USER_WHEA_OPTION
};
#endif // _OPTION_WHEA_INSTALL_H_

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src/vendorcode/amd/agesa/f10/Include/Options.h
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/**
* @file
*
* AGESA options structures
*
* Contains options control structures for the AGESA build options
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 6104 $ @e \$Date: 2008-05-19 06:54:08 -0500 (Mon, 19 May 2008) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#ifndef _OPTIONS_H_
#define _OPTIONS_H_
/**
* Provide topology limits for loops and runtime, based on supported families.
*/
typedef struct {
UINT32 PlatformNumberOfSockets; ///< The limit to the number of processors based on
///< supported families and other build options.
UINT32 PlatformNumberOfModules; ///< The limit to the number of modules in a processor, based
///< on supported families.
} OPTIONS_CONFIG_TOPOLOGY;
/**
* Dispatch Table.
*
* The push high dispatcher uses this table to find what entries are currently in the build image.
*/
typedef struct {
UINT32 FunctionId; ///< The function id specified.
IMAGE_ENTRY EntryPoint; ///< The corresponding entry point to call.
} DISPATCH_TABLE;
#endif // _OPTIONS_H_

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@ -1,100 +0,0 @@
/**
* @file
*
* AMD HyperTransport option API.
*
* Contains option pre-compile logic. This file is used by the options
* installer and internally by the HT code initializers.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef _OPTION_HT_H_
#define _OPTION_HT_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
/**
* Provide HT build option results
*/
typedef struct {
CONST BOOLEAN IsUsingRecoveryHt; ///< Manual BUID Swap List processing should assume that HT Recovery was used.
CONST BOOLEAN IsSetHtCrcFlood; ///< Enable setting of HT CRC Flood.
///< Build-time only customizable - @BldCfgItem{BLDCFG_SET_HTCRC_SYNC_FLOOD}
CONST BOOLEAN IsUsingUnitIdClumping; ///< Enable automatically HT Spec compliant Unit Id Clumping.
///< Build-time only customizable - @BldCfgItem{BLDCFG_USE_UNIT_ID_CLUMPING}
CONST AMD_HT_INTERFACE *HtOptionPlatformDefaults; ///< A set of build time options for HT constructor.
CONST VOID *HtOptionInternalInterface; ///< Use this internal interface initializer.
CONST VOID *HtOptionInternalFeatures; ///< Use this internal feature set initializer.
CONST VOID *HtOptionFamilyNorthbridgeList; ///< Use this list of northbridge initializers.
CONST UINT8 *CONST *HtOptionBuiltinTopologies; ///< Use this list of built-in topologies.
} OPTION_HT_CONFIGURATION;
typedef AGESA_STATUS
F_OPTION_HT_INIT_RESET (
IN AMD_CONFIG_PARAMS *StdHeader,
IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface
);
typedef F_OPTION_HT_INIT_RESET *PF_OPTION_HT_INIT_RESET;
/**
* Provide HT reset initialization build option results
*/
typedef struct {
PF_OPTION_HT_INIT_RESET HtInitReset; ///< Method: HT reset initialization.
} OPTION_HT_INIT_RESET;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_HT_H_

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/**
* @file
*
* Create outline and references for Build Configuration and Options Component mainpage documentation.
*
* Design guides, maintenance guides, and general documentation, are
* collected using this file onto the documentation mainpage.
* This file contains doxygen comment blocks, only.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Documentation
* @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/**
* @page optionmain Build Configuration and Options Documentation
*
* Additional documentation for the Build Configuration and Options component consists of
*
* - Introduction and Overview to Build Options
* - @subpage platforminstall "Platform Build Options"
* - @subpage bldcfg "Build Configuration Item Cross Reference"
* - @subpage examplecustomizations "Customization Examples"
* - Maintenance Guides:
* - For debug of the Options system, use compiler options
* @n <tt> /P /EP /C /FAs </tt> @n
* PreProcessor output is produced in an .i file in the directory where the project
* file is located.
* - Design Guides:
* - add here >>>
*
*/
/**
* @page platforminstall Platform Build Options.
*
* Build options are boolean constants. The purpose of build options is to remove code
* from the build to reduce the overall code size present in the ROM image. Unless
* otherwise specified, the default action is to include all options. If a build option is
* not specifically listed as disabled, then it is included into the build.
*
* The documented build options are imported from a user controlled file for
* processing. The build options for all platform solutions are listed below:
*
* @anchor BLDOPT_REMOVE_UDIMMS_SUPPORT
* @li @e BLDOPT_REMOVE_UDIMMS_SUPPORT @n
* If unbuffered DIMMs are NOT expected to be required in the system, the code that
* handles unbuffered DIMMs can be removed from the build.
*
* @anchor BLDOPT_REMOVE_RDIMMS_SUPPORT
* @li @e BLDOPT_REMOVE_RDIMMS_SUPPORT @n
* If registered DIMMs are NOT expected to be required in the system, the code
* that handles registered DIMMs can be removed from the build.
*
* @note The above two options operate independently from each other; however, at
* least one of the unbuffered or registered options must be present in the build.
*
* @anchor BLDOPT_REMOVE_ECC_SUPPORT
* @li @e BLDOPT_REMOVE_ECC_SUPPORT @n
* Use this option to remove the code for Error Checking & Correction.
*
* @anchor BLDOPT_REMOVE_BANK_INTERLEAVE
* @li @e BLDOPT_REMOVE_BANK_INTERLEAVE @n
* Interleaving is a mechanism to do performance fine tuning. This option
* interleaves memory between banks on a DIMM.
*
* @anchor BLDOPT_REMOVE_DCT_INTERLEAVE
* @li @e BLDOPT_REMOVE_DCT_INTERLEAVE @n
* Interleaving is a mechanism to do performance fine tuning. This option
* interleaves memory from two DRAM controllers.
*
* @anchor BLDOPT_REMOVE_NODE_INTERLEAVE
* @li @e BLDOPT_REMOVE_NODE_INTERLEAVE @n
* Interleaving is a mechanism to do performance fine tuning. This option
* interleaves memory from two HyperTransport nodes.
*
* @anchor BLDOPT_REMOVE_PARALLEL_TRAINING
* @li @e BLDOPT_REMOVE_PARALLEL_TRAINING @n
* For multi-socket systems, training memory in parallel can reduce the time
* needed to boot.
*
* @anchor BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT
* @li @e BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT @n
* Online Spare support is removed by this option.
*
* @anchor BLDOPT_REMOVE_MULTISOCKET_SUPPORT
* @li @e BLDOPT_REMOVE_MULTISOCKET_SUPPORT @n
* Many systems use only a single socket and may benefit in code space to remove
* this code. However, certain processors have multiple HyperTransport nodes
* within a single socket. For these processors, the multi-node support is
* required and this option has no effect.
*
* @anchor BLDOPT_REMOVE_ACPI_PSTATES
* @li @e BLDOPT_REMOVE_ACPI_PSTATES @n
* This option removes the code that generates the ACPI tables used in power
* management.
*
* @anchor BLDOPT_REMOVE_SRAT
* @li @e BLDOPT_REMOVE_SRAT @n
* This option removes the code that generates the SRAT tables used in performance
* tuning.
*
* @anchor BLDOPT_REMOVE_SLIT
* @li @e BLDOPT_REMOVE_SLIT @n
* This option removes the code that generates the SLIT tables used in performance
* tuning.
*
* @anchor BLDOPT_REMOVE_WHEA
* @li @e BLDOPT_REMOVE_WHEA @n
* This option removes the code that generates the WHEA tables used in error
* handling and reporting.
*
* @anchor BLDOPT_REMOVE_DMI
* @li @e BLDOPT_REMOVE_DMI @n
* This option removes the code that generates the DMI tables used in system
* management.
*
* @anchor BLDOPT_REMOVE_DQS_TRAINING
* @li @e BLDOPT_REMOVE_DQS_TRAINING @n
* This option removes the code used in memory performance tuning.
*
* @anchor BLDOPT_REMOVE_EARLY_SAMPLES
* @li @e BLDOPT_REMOVE_EARLY_SAMPLES @n
* Special support for Early Samples is included. Default setting is FALSE.
*
* @anchor BLDOPT_REMOVE_HT_ASSIST
* @li @e BLDOPT_REMOVE_HT_ASSIST @n
* This option removes the code which implements the HT Assist feature.
*
* @anchor BLDOPT_REMOVE_MSG_BASED_C1E
* @li @e BLDOPT_REMOVE_MSG_BASED_C1E @n
* This option removes the code which implements the Message Based C1e feature.
*
* @anchor BLDOPT_REMOVE_C6_STATE
* @li @e BLDOPT_REMOVE_C6_STATE @n
* This option removes the code which implements the C6 C-state feature.
*
* @anchor BLDOPT_REMOVE_MEM_RESTORE_SUPPORT
* @li @e BLDOPT_REMOVE_MEM_RESTORE_SUPPORT @n
* This option removes the memory context restore feature.
*
*/
/**
* @page examplecustomizations Customization Examples
*
* The Addendum \<plat\>Options.c file for each platform contains the minimum required
* customizations for that platform. That is, it contains settings which would be needed
* to boot a SimNow! bsd for that platform.
* However, each individual product based on that platform will have customizations necessary for
* that hardware. Since the actual customizations needed vary so much, they are not included in
* the \<plat\>Options.c. This section provides examples of useful customizations that you can use or
* modify to suit your needs.
*
* @par
*
* Source for the examples shown can be found at Addendum\\Examples. @n
*
* - @ref DeemphasisExamples "Deemphasis List Examples"
* - @ref FrequencyLimitExamples "Frequency Limit Examples"
* - @ref PerfPerWattHt "A performance-per-watt optimization Example"
*
* @anchor DeemphasisExamples
* @par Deemphasis List Examples
*
* These examples customize ::PLATFORM_CONFIGURATION::PlatformDeemphasisList.
* Source for the deemphasis list examples can be found in DeemphasisExamples.c. @n
* @dontinclude DeemphasisExamples.c
* <ul>
* <li>
* The following deemphasis list provides an example for a 2P MCM Max Performance configuration.
* High Speed HT frequencies are supported. There is only one non-coherent chain. Note the technique of
* putting specified link matches before all uses of match any. It often works well to specify the non-coherent links
* and use match any for the coherent links.
* @skip DinarDeemphasisList
* @until {
* The non-coherent chain can run up to 2600 MHz. The chain is located on Socket 0, package Link 2.
* @until {
* @line }
* @line {
* @line }
* The coherent links can run up to 3200 MHz.
* @until HT_FREQUENCY_MAX
* @line }
* end of list:
* @until }
* Make this list the build time customized deemphasis list.
* @line define
*
* </li><li>
*
* The following deemphasis list provides an example for a 4P MCM Max Performance configuration.
* This system has a backplane with connectors for CPU cards and an IO board. So trace lengths are long.
* There can be one to four IO Chains, depending on the IO board.
* @skipline DoubloonDeemphasisList
* @until DoubloonDeemphasisList
*
* </ul>
*
* @anchor FrequencyLimitExamples
* @par Frequency Limit Examples
*
* These examples customize ::AMD_HT_INTERFACE::CpuToCpuPcbLimitsList and ::AMD_HT_INTERFACE::IoPcbLimitsList.
* Source for the frequency limit examples can be found in FrequencyLimitExamples.c. @n
* @dontinclude FrequencyLimitExamples.c
* <ul>
* <li>
* The following list provides an example for limiting all coherent links to non-extended frequencies,
* that is, to 2600 MHz or less.
* @skipline NonExtendedCpuToCpuLimitList
* @until {
* Provide the limit customization. Match links from any socket, any package link, to any socket, any package link. Width is not limited.
* @until HT_FREQUENCY_LIMIT_2600M
* End of list:
* @until ;
* Customize the build to use this cpu to cpu frequency limit.
* @until NonExtendedCpuToCpuLimitList
* @n </li>
* <li>
* The following list provides an example for limiting all coherent links to HT 1 frequencies,
* that is, to 1000 MHz or less. This is sometimes useful for test and debug.
* @skipline Ht1CpuToCpuLimitList
* @until Ht1CpuToCpuLimitList
* @n </li>
* <li>
* The following list provides an example for limiting all non-coherent links to 2400 MHz or less.
* The chain is matched by host processor Socket and package Link. The depth can be used to select a particular device
* to device link on the chain. In this example, the chain consists of a single cave device and depth can be set to match any.
* @skipline No2600MhzIoLimitList
* @until No2600MhzIoLimitList
* @n </li>
* <li>
* The following list provides an example for limiting all non-coherent links to the minimum HT 3 frequency,
* that is, to 1200 MHz or less. This can be useful for test and debug.
* @skipline MinHt3IoLimitList
* @until MinHt3IoLimitList
* @n </li>
*
* </ul>
*
* @anchor PerfPerWattHt
* @par Performance-per-Watt Optimization Example
*
* This example customizes ::AMD_HT_INTERFACE::SkipRegangList.
* Source for the Performance-per-watt Optimization example can be found in PerfPerWatt.c. @n
* @dontinclude PerfPerWatt.c
* To implement a performance-per-watt optimization for MCM processors, use the skip regang structure shown. @n
* @skipline PerfPerWatt
* @until PerfPerWatt
*
*/

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/**
* @file
*
* AMD Platform Specific Memory Configuration
*
* Contains Definitions and Macros for control of AGESA Memory code on a per platform basis
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 5937 $ @e \$Date: 2009-12-02 03:59:36 -0700 (Wed, 02 Dec 2009) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef _PLATFORM_MEMORY_CONFIGURATION_H_
#define _PLATFORM_MEMORY_CONFIGURATION_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
#ifndef PSO_ENTRY
#define PSO_ENTRY UINT8
#endif
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* PLATFORM SPECIFIC MEMORY DEFINITIONS
*----------------------------------------------------------------------------------------
*/
///
/// Memory Speed and DIMM Population Masks
///
///< DDR Speed Masks
///< Specifies the DDR Speed on a memory channel
///
#define ANY_SPEED 0xFFFFFFFF
#define DDR400 ((UINT32) 1 << (DDR400_FREQUENCY / 66))
#define DDR533 ((UINT32) 1 << (DDR533_FREQUENCY / 66))
#define DDR667 ((UINT32) 1 << (DDR667_FREQUENCY / 66))
#define DDR800 ((UINT32) 1 << (DDR800_FREQUENCY / 66))
#define DDR1066 ((UINT32) 1 << (DDR1066_FREQUENCY / 66))
#define DDR1333 ((UINT32) 1 << (DDR1333_FREQUENCY / 66))
#define DDR1600 ((UINT32) 1 << (DDR1600_FREQUENCY / 66))
#define DDR1866 ((UINT32) 1 << (DDR1866_FREQUENCY / 66))
///
///< DIMM POPULATION MASKS
///< Specifies the DIMM Population on a channel (can be added together to specify configuration).
///< ex. SR_DIMM0 + SR_DIMM1 : Single Rank Dimm in slot 0 AND Slot 1
///< SR_DIMM0 + DR_DIMM0 + SR_DIMM1 +DR_DIMM1 : Single OR Dual rank in Slot 0 AND Single OR Dual rank in Slot 1
///
#define ANY_ 0xFF ///< Any dimm configuration the current channel
#define SR_DIMM0 0x0001 ///< Single rank dimm in slot 0 on the current channel
#define SR_DIMM1 0x0010 ///< Single rank dimm in slot 1 on the current channel
#define SR_DIMM2 0x0100 ///< Single rank dimm in slot 2 on the current channel
#define SR_DIMM3 0x1000 ///< Single rank dimm in slot 3 on the current channel
#define DR_DIMM0 0x0002 ///< Dual rank dimm in slot 0 on the current channel
#define DR_DIMM1 0x0020 ///< Dual rank dimm in slot 1 on the current channel
#define DR_DIMM2 0x0200 ///< Dual rank dimm in slot 2 on the current channel
#define DR_DIMM3 0x2000 ///< Dual rank dimm in slot 3 on the current channel
#define QR_DIMM0 0x0004 ///< Quad rank dimm in slot 0 on the current channel
#define QR_DIMM1 0x0040 ///< Quad rank dimm in slot 1 on the current channel
#define QR_DIMM2 0x0400 ///< Quad rank dimm in slot 2 on the current channel
#define QR_DIMM3 0x4000 ///< Quad rank dimm in slot 3 on the current channel
#define ANY_DIMM0 0x000F ///< Any Dimm combination in slot 0 on the current channel
#define ANY_DIMM1 0x00F0 ///< Any Dimm combination in slot 1 on the current channel
#define ANY_DIMM2 0x0F00 ///< Any Dimm combination in slot 2 on the current channel
#define ANY_DIMM3 0xF000 ///< Any Dimm combination in slot 3 on the current channel
///
///< Number of Dimms on the current channel
///< This is a mask used to indicate the number of dimms in a channel
///< They can be added to indicate multiple conditions (i.e 1 OR 2 Dimms)
///
#define ANY_NUM 0xFF ///< Any number of Dimms
#define NO_DIMM 0x00 ///< No Dimms present
#define ONE_DIMM 0x01 ///< One dimm Poulated on the current channel
#define TWO_DIMM 0x02 ///< Two dimms Poulated on the current channel
#define THREE_DIMM 0x04 ///< Three dimms Poulated on the current channel
#define FOUR_DIMM 0x08 ///< Four dimms Poulated on the current channel
/*----------------------------------------------------------------------------------------
*
* Platform Specific Override Definitions for Socket, Channel and Dimm
* This indicates where a platform override will be applied.
*
*----------------------------------------------------------------------------------------
*/
///
///< SOCKET MASKS
///< Indicates associated processor sockets to apply override settings
///
#define ANY_SOCKET 0xFF ///< Apply to all sockets
#define SOCKET0 0x01 ///< Apply to socket 0
#define SOCKET1 0x02 ///< Apply to socket 1
#define SOCKET2 0x04 ///< Apply to socket 2
#define SOCKET3 0x08 ///< Apply to socket 3
#define SOCKET4 0x10 ///< Apply to socket 4
#define SOCKET5 0x20 ///< Apply to socket 5
#define SOCKET6 0x40 ///< Apply to socket 6
#define SOCKET7 0x80 ///< Apply to socket 7
///
///< CHANNEL MASKS
///< Indicates Memory channels where override should be applied
///
#define ANY_CHANNEL 0xFF ///< Apply to all Memory channels
#define CHANNEL_A 0x01 ///< Apply to Channel A
#define CHANNEL_B 0x02 ///< Apply to Channel B
#define CHANNEL_C 0x04 ///< Apply to Channel C
#define CHANNEL_D 0x08 ///< Apply to Channel D
///
/// DIMM MASKS
/// Indicates Dimm Slots where override should be applied
///
#define ALL_DIMMS 0xFF ///< Apply to all dimm slots
#define DIMM0 0x01 ///< Apply to Dimm Slot 0
#define DIMM1 0x02 ///< Apply to Dimm Slot 1
#define DIMM2 0x04 ///< Apply to Dimm Slot 2
#define DIMM3 0x08 ///< Apply to Dimm Slot 3
///
/// REGISTER ACCESS MASKS
/// Not supported as an at this time
///
#define ACCESS_NB0 0x0
#define ACCESS_NB1 0x1
#define ACCESS_NB2 0x2
#define ACCESS_NB3 0x3
#define ACCESS_NB4 0x4
#define ACCESS_PHY 0x5
#define ACCESS_DCT_XT 0x6
/*----------------------------------------------------------------------------------------
*
* Platform Specific Overriding Table Definitions
*
*----------------------------------------------------------------------------------------
*/
#define PSO_END 0 ///< Table End
#define PSO_CKE_TRI 1 ///< CKE Tristate Map
#define PSO_ODT_TRI 2 ///< ODT Tristate Map
#define PSO_CS_TRI 3 ///< CS Tristate Map
#define PSO_MAX_DIMMS 4 ///< Max Dimms per channel
#define PSO_CLK_SPEED 5 ///< Clock Speed
#define PSO_DIMM_TYPE 6 ///< Dimm Type
#define PSO_MEMCLK_DIS 7 ///< MEMCLK Disable Map
#define PSO_MAX_CHNLS 8 ///< Max Channels per Socket
#define PSO_BUS_SPEED 9 ///< Max Memory Bus Speed
#define PSO_MAX_CHIPSELS 10 ///< Max Chipsel per Channel
#define PSO_MEM_TECH 11 ///< Channel Memory Type
#define PSO_WL_SEED 12 ///< DDR3 Write Levelization Seed delay
#define PSO_LVDIMM_VOLT1_5_SUPPORT 16 ///< Force LvDimm voltage to 1.5V
/*----------------------------------
* CONDITIONAL PSO SPECIFIC ENTRIES
*---------------------------------*/
// Condition Types
#define CONDITIONAL_PSO_MIN 100 ///< Start of Conditional Entry Types
#define PSO_CONDITION_AND 100 ///< And Block - Start of Conditional block
#define PSO_CONDITION_LOC 101 ///< Location - Specify Socket, Channel, Dimms to be affected
#define PSO_CONDITION_SPD 102 ///< SPD - Specify a specific SPD value on a Dimm on the channel
#define PSO_CONDITION_REG 103 // Reserved
#define PSO_CONDITION_MAX 103 ///< End Of Condition Entry Types
// Action Types
#define PSO_ACTION_MIN 120 ///< Start of Action Entry Types
#define PSO_ACTION_ODT 120 ///< ODT values to override
#define PSO_ACTION_ADDRTMG 121 ///< Address/Timing values to override
#define PSO_ACTION_ODCCONTROL 122 ///< ODC Control values to override
#define PSO_ACTION_SLEWRATE 123 ///< Slew Rate value to override
#define PSO_ACTION_REG 124 // Reserved
#define PSO_ACTION_SPEEDLIMIT 125 ///< Memory Bus speed Limit based on configuration
#define PSO_ACTION_MAX 125 ///< End of Action Entry Types
#define CONDITIONAL_PSO_MAX 139 ///< End of Conditional Entry Types
/*----------------------------------------------------------------------------------------
* CONDITIONAL OVERRIDE TABLE MACROS
*----------------------------------------------------------------------------------------
*/
#define MEMCLK_DIS_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map) \
PSO_MEMCLK_DIS, 10, SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map
#define CKE_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map) \
PSO_CKE_TRI, 4, SocketID, ChannelID, Bit0Map, Bit1Map
#define ODT_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map) \
PSO_ODT_TRI, 6, SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map
#define CS_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map) \
PSO_CS_TRI, 10, SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map
#define NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) \
PSO_MAX_DIMMS, 3, SocketID, ChannelID, NumberOfDimmSlotsPerChannel
#define NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) \
PSO_MAX_CHIPSELS, 3, SocketID, ChannelID, NumberOfChipSelectsPerChannel
#define NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) \
PSO_MAX_CHNLS, 3, SocketID, ANY_CHANNEL, NumberOfChannelsPerSocket
#define OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, TimingMode, BusSpeed) \
PSO_BUS_SPEED, 10, SocketID, ChannelID, TimingMode, (TimingMode >> 8), (TimingMode >> 16), (TimingMode >> 24), \
BusSpeed, (BusSpeed >> 8), (BusSpeed >> 16), (BusSpeed >> 24)
#define DRAM_TECHNOLOGY(SocketID, MemTechType) \
PSO_MEM_TECH, 6, SocketID, ANY_CHANNEL, MemTechType, (MemTechType >> 8), (MemTechType >> 16), (MemTechType >> 24)
#define WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \
Byte6Seed, Byte7Seed, ByteEccSeed) \
PSO_WL_SEED, 11, SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \
Byte6Seed, Byte7Seed, ByteEccSeed
#define LVDIMM_FORCE_VOLT1_5_FOR_D0 \
PSO_LVDIMM_VOLT1_5_SUPPORT, 3, ANY_SOCKET, ANY_CHANNEL, TRUE
/*----------------------------------------------------------------------------------------
* CONDITIONAL OVERRIDE TABLE MACROS
*----------------------------------------------------------------------------------------
*/
#define CONDITION_AND \
PSO_CONDITION_AND, 0
#define COND_LOC(SocketMsk, ChannelMsk, DimmMsk) \
PSO_CONDITION_LOC, 3, SocketMsk, ChannelMsk, DimmMsk
#define COND_SPD(Byte, Mask, Value) \
PSO_CONDITION_SPD, 3, Byte, Mask, Value
#define COND_REG(Access, Offset, Mask, Value) \
PSO_CONDITION_REG, 11, Access, (Offset & 0x0FF), (Offset >> 8), \
((Mask) & 0x0FF), (((Mask) >> 8) & 0x0FF), (((Mask) >> 16) & 0x0FF), (((Mask) >> 24) & 0x0FF), \
((Value) & 0x0FF), (((Value) >> 8) & 0x0FF), (((Value) >> 16) & 0x0FF), (((Value) >> 24) & 0x0FF)
#define ACTION_ODT(Frequency, Dimms, QrDimms, DramOdt, QrDramOdt, DramDynOdt) \
PSO_ACTION_ODT, 9, \
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), ((Frequency >> 24)& 0x0FF), \
Dimms, QrDimms, DramOdt, QrDramOdt, DramDynOdt
#define ACTION_ADDRTMG(Frequency, DimmConfig, AddrTmg) \
PSO_ACTION_ADDRTMG, 10, \
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
(AddrTmg & 0x0FF), ((AddrTmg >> 8)& 0x0FF), ((AddrTmg >> 16)& 0x0FF), ((AddrTmg >> 24)& 0x0FF)
#define ACTION_ODCCTRL(Frequency, DimmConfig, OdcCtrl) \
PSO_ACTION_ODCCONTROL, 10, \
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
(OdcCtrl & 0x0FF), ((OdcCtrl >> 8)& 0x0FF), ((OdcCtrl >> 16)& 0x0FF), ((OdcCtrl >> 24)& 0x0FF)
#define ACTION_SLEWRATE(Frequency, DimmConfig, SlewRate) \
PSO_ACTION_SLEWRATE, 10, \
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
(SlewRate & 0x0FF), ((SlewRate >> 8)& 0x0FF), ((SlewRate >> 16)& 0x0FF), ((SlewRate >> 24)& 0x0FF)
#define ACTION_SPEEDLIMIT(DimmConfig, Dimms, SpeedLimit15, SpeedLimit135, SpeedLimit125) \
PSO_ACTION_SPEEDLIMIT, 9, \
((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), Dimms, \
(SpeedLimit15 & 0x0FF), ((SpeedLimit15 >> 8)& 0x0FF), \
(SpeedLimit135 & 0x0FF), ((SpeedLimit135 >> 8)& 0x0FF), \
(SpeedLimit125 & 0x0FF), ((SpeedLimit125 >> 8)& 0x0FF)
/*----------------------------------------------------------------------------------------
* END OF CONDITIONAL OVERRIDE TABLE MACROS
*----------------------------------------------------------------------------------------
*/
#endif // _PLATFORM_MEMORY_CONFIGURATION_H_

162
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@ -1,162 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Topology interface definitions.
*
* Contains AMD AGESA internal interface for topology related data which
* is consumed by code other than HyperTransport init (and produced by
* HyperTransport init.)
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _TOPOLOGY_H_
#define _TOPOLOGY_H_
// Defines for limiting data structure maximum allocation and limit checking.
#define MAX_NODES 8
#define MAX_SOCKETS MAX_NODES
#define MAX_DIES 2
// Defines useful with package link
#define HT_LIST_MATCH_INTERNAL_LINK_0 0xFA
#define HT_LIST_MATCH_INTERNAL_LINK_1 0xFB
#define HT_LIST_MATCH_INTERNAL_LINK_2 0xFC
/**
* Hop Count Table.
* This is a heap data structure. The Hops array is filled as a size x size matrix.
* The unused space, if any, is all at the end.
*/
typedef struct {
UINT8 Size; ///< The row and column size of actual hop count data */
UINT8 Hops[MAX_NODES * MAX_NODES]; ///< Room for a dynamic two dimensional array of [size][size] */
} HOP_COUNT_TABLE;
/**
* Socket and Module to Node Map Item.
* Provide the Node Id and core id range for each module in each processor.
*/
typedef struct {
UINT8 Node; ///< The module's Node id.
UINT8 LowCore; ///< The lowest processor core id for this module.
UINT8 HighCore; ///< The highest processor core id for this module.
UINT8 EnabledComputeUnits; ///< The value of Enabled for this processor module.
UINT8 DualCoreComputeUnits; ///< The value of DualCore for this processor module.
} SOCKET_DIE_TO_NODE_ITEM;
/**
* Socket and Module to Node Map.
* This type is a pointer to the actual map, it can be used for a struct item or
* for typecasting a heap buffer pointer.
*/
typedef SOCKET_DIE_TO_NODE_ITEM (*SOCKET_DIE_TO_NODE_MAP)[MAX_SOCKETS][MAX_DIES];
/**
* Node id to Socket Die Map Item.
*/
typedef struct {
UINT8 Socket; ///< socket of the processor containing the Node.
UINT8 Die; ///< the module in the processor which is Node.
} NODE_TO_SOCKET_DIE_ITEM;
/**
* Node id to Socket Die Map.
*/
typedef NODE_TO_SOCKET_DIE_ITEM (*NODE_TO_SOCKET_DIE_MAP)[MAX_NODES];
/**
* Provide AP core with socket and node context at start up.
* This information is posted to the AP cores using a register as a mailbox.
*/
typedef struct {
UINT32 Node:4; ///< The node id of Core's node.
UINT32 Socket:4; ///< The socket of this Core's node.
UINT32 Module:2; ///< The internal module number for Core's node.
UINT32 ModuleType:2; ///< Single Module = 0, Multi-module = 1.
UINT32 :20; ///< Reserved
} AP_MAIL_INFO_FIELDS;
/**
* AP info fields can be written and read to a register.
*/
typedef union {
UINT32 Info; ///< Just a number for register access, or opaque passing.
AP_MAIL_INFO_FIELDS Fields; ///< access to the info fields.
} AP_MAIL_INFO;
/**
* Provide AP core with system degree and system core number at start up.
* This information is posted to the AP cores using a register as a mailbox.
*/
typedef struct {
UINT32 SystemDegree:3; ///< The number of connected links
UINT32 :3; ///< Reserved
UINT32 HeapIndex:6; ///< The zero-based system core number
UINT32 :20; ///< Reserved
} AP_MAIL_EXT_INFO_FIELDS;
/**
* AP info fields can be written and read to a register.
*/
typedef union {
UINT32 Info; ///< Just a number for register access, or opaque passing.
AP_MAIL_EXT_INFO_FIELDS Fields; ///< access to the info fields.
} AP_MAIL_EXT_INFO;
/**
* AP Info mailbox set.
*/
typedef struct {
AP_MAIL_INFO ApMailInfo; ///< The AP mail info
AP_MAIL_EXT_INFO ApMailExtInfo; ///< The extended AP mail info
} AP_MAILBOXES;
/**
* Provide a northbridge to package mapping for link assignments.
*
*/
typedef struct {
UINT8 Link; ///< The Node's link
UINT8 Module; ///< The internal module position of Node
UINT8 PackageLink; ///< The corresponding package link
} PACKAGE_HTLINK_MAP_ITEM;
/**
* A Processor's complete set of link assignments
*/
typedef PACKAGE_HTLINK_MAP_ITEM (*PACKAGE_HTLINK_MAP)[];
#endif // _TOPOLOGY_H_

132
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@ -1,132 +0,0 @@
/**
* @file
*
* AMD binary block interface
*
* Contains the block entry function dispatcher
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Legacy
* @e \$Revision: 7116 $ @e \$Date: 2008-08-01 10:39:07 -0500 (Fri, 01 Aug 2008) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Dispatcher.h"
#include "Options.h"
#include "Filecode.h"
#define FILECODE LEGACY_PROC_DISPATCHER_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
extern CONST DISPATCH_TABLE DispatchTable[];
extern AMD_MODULE_HEADER mCpuModuleID;
/*---------------------------------------------------------------------------------------*/
/**
* The Dispatcher is the entry point into the AGESA software. It takes a function
* number as entry parameter in order to invoke the published function
*
* @param[in,out] ConfigPtr
*
* @return AGESA Status.
*
*/
AGESA_STATUS
CALLCONV
AmdAgesaDispatcher (
IN OUT VOID *ConfigPtr
)
{
AGESA_STATUS Status;
MODULE_ENTRY ModuleEntry;
DISPATCH_TABLE *Entry;
Status = AGESA_UNSUPPORTED;
ModuleEntry = NULL;
Entry = (DISPATCH_TABLE *) DispatchTable;
while (Entry->FunctionId != 0) {
if ((((AMD_CONFIG_PARAMS *) ConfigPtr)->Func) == Entry->FunctionId) {
Status = Entry->EntryPoint (ConfigPtr);
break;
}
Entry++;
}
// 2. Try next dispatcher if possible, and we have not already got status back
if ((mCpuModuleID.NextBlock != NULL) && (Status == AGESA_UNSUPPORTED)) {
ModuleEntry = (MODULE_ENTRY) mCpuModuleID.NextBlock->ModuleDispatcher;
if (ModuleEntry != NULL) {
Status = (*ModuleEntry) (ConfigPtr);
}
}
return (Status);
}
/*---------------------------------------------------------------------------------------*/
/**
* The host environment interface of callout.
*
* @param[in] Func
* @param[in] Data
* @param[in,out] ConfigPtr
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
CALLCONV
AmdAgesaCallout (
IN UINT32 Func,
IN UINTN Data,
IN OUT VOID *ConfigPtr
)
{
UINT32 Result;
Result = AGESA_UNSUPPORTED;
if (((AMD_CONFIG_PARAMS *) ConfigPtr)->CalloutPtr == NULL) {
return Result;
}
Result = (((AMD_CONFIG_PARAMS *) ConfigPtr)->CalloutPtr) (Func, Data, ConfigPtr);
return (Result);
}

371
src/vendorcode/amd/agesa/f10/Legacy/Proc/agesaCallouts.c
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@ -1,371 +0,0 @@
/**
* @file
*
* AMD CPU AGESA Callout Functions
*
* Contains code to set / get useful platform information.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Common
* @e \$Revision: 5931 $ @e \$Date: 2008-04-24 18:01:47 -0700 (Thu, 24 Apr 2008) $
*
*/
/*****************************************************************************
* AMD Generic Encapsulated Software Architecture
*
* Description: agesaCallouts.c - AGESA Call out functions
*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "Dispatcher.h"
#include "Ids.h"
#include "Filecode.h"
#define FILECODE LEGACY_PROC_AGESACALLOUTS_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S - (AGESA ONLY)
*----------------------------------------------------------------------------------------
*/
AGESA_STATUS
AgesaGetIdsData (
IN UINTN Data,
IN OUT IDS_CALLOUT_STRUCT *IdsCalloutData
);
/*---------------------------------------------------------------------------------------*/
/**
*
* Call the host environment interface to do the warm or cold reset.
*
* @param[in] ResetType Warm or Cold Reset is requested
* @param[in,out] StdHeader Config header
*
*/
VOID
AgesaDoReset (
IN UINTN ResetType,
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_DO_RESET, (UINT32)ResetType, (VOID *) StdHeader);
}
/*---------------------------------------------------------------------------------------*/
/**
*
* Call the host environment interface to allocate buffer in main system memory.
*
* @param[in] FcnData
* @param[in,out] AllocParams Heap manager parameters
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaAllocateBuffer (
IN UINTN FcnData,
IN OUT AGESA_BUFFER_PARAMS *AllocParams
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_ALLOCATE_BUFFER, (UINT32)FcnData, (VOID *) AllocParams);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to deallocate buffer in main system memory.
*
* @param[in] FcnData
* @param[in,out] DeallocParams Heap Manager parameters
*
* @return The AGESA Status returned from the callout.
*/
AGESA_STATUS
AgesaDeallocateBuffer (
IN UINTN FcnData,
IN OUT AGESA_BUFFER_PARAMS *DeallocParams
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_DEALLOCATE_BUFFER, (UINT32)FcnData, (VOID *) DeallocParams);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
*
* Call the host environment interface to Locate buffer Pointer in main system memory
*
* @param[in] FcnData
* @param[in,out] LocateParams Heap manager parameters
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaLocateBuffer (
IN UINTN FcnData,
IN OUT AGESA_BUFFER_PARAMS *LocateParams
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_LOCATE_BUFFER, (UINT32)FcnData, (VOID *) LocateParams);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to launch APs
*
* @param[in] ApicIdOfCore
* @param[in,out] LaunchApParams
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaRunFcnOnAp (
IN UINTN ApicIdOfCore,
IN AP_EXE_PARAMS *LaunchApParams
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_RUNFUNC_ONAP, (UINT32)ApicIdOfCore, (VOID *) LaunchApParams);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to read an SPD's content.
*
* @param[in] FcnData
* @param[in,out] ReadSpd
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaReadSpd (
IN UINTN FcnData,
IN OUT AGESA_READ_SPD_PARAMS *ReadSpd
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_READ_SPD, (UINT32)FcnData, ReadSpd);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to read an SPD's content.
*
* @param[in] FcnData
* @param[in,out] ReadSpd
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaReadSpdRecovery (
IN UINTN FcnData,
IN OUT AGESA_READ_SPD_PARAMS *ReadSpd
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_READ_SPD_RECOVERY, (UINT32)FcnData, ReadSpd);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to provide a user hook opportunity.
*
* @param[in] FcnData
* @param[in,out] MemData
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaHookBeforeDramInit (
IN UINTN FcnData,
IN OUT MEM_DATA_STRUCT *MemData
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_HOOKBEFORE_DRAM_INIT, (UINT32)FcnData, MemData);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to provide a user hook opportunity.
*
* @param[in] FcnData
* @param[in,out] MemData
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaHookBeforeDQSTraining (
IN UINTN FcnData,
IN OUT MEM_DATA_STRUCT *MemData
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_HOOKBEFORE_DQS_TRAINING, (UINT32)FcnData, MemData);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to provide a user hook opportunity.
*
* @param[in] FcnData
* @param[in,out] MemData
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaHookBeforeExitSelfRefresh (
IN UINTN FcnData,
IN OUT MEM_DATA_STRUCT *MemData
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_HOOKBEFORE_EXIT_SELF_REF, (UINT32)FcnData, MemData);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to provide a user hook opportunity.
*
* @param[in] Data
* @param[in,out] IdsCalloutData
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaGetIdsData (
IN UINTN Data,
IN OUT IDS_CALLOUT_STRUCT *IdsCalloutData
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_GET_IDS_INIT_DATA, (UINT32)Data, IdsCalloutData);
return Status;
}
/*----------------------------------------------------------------------------------------*/
/**
* PCIE slot reset control
*
*
*
* @param[in] FcnData Function data
* @param[in] ResetInfo Reset information
* @retval Status Agesa status
*/
AGESA_STATUS
AgesaPcieSlotResetControl (
IN UINTN FcnData,
IN PCIe_SLOT_RESET_INFO *ResetInfo
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_GNB_PCIE_SLOT_RESET, (UINT32) FcnData, ResetInfo);
return Status;
}

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/**
* @file
*
* AMD Hob Transfer functions.
*
* Contains code that copy Heap to temp memory or main memory.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU
* @e \$Revision: 7532 $ @e \$Date: 2008-08-22 04:50:27 +0800 (Fri, 22 Aug 2008) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "cpuRegisters.h"
#include "GeneralServices.h"
#include "heapManager.h"
#include "cpuPostInit.h"
#include "cpuEnvInit.h"
#include "Filecode.h"
#define FILECODE LEGACY_PROC_HOBTRANSFER_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P U B L I C F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
extern BUILD_OPT_CFG UserOptions;
/* -----------------------------------------------------------------------------*/
/**
*
* CopyHeapToTempRamAtPost
*
* This function copies BSP heap content to RAM
*
* @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct.
*
* @retval AGESA_STATUS
*
*/
AGESA_STATUS
CopyHeapToTempRamAtPost (
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 i;
UINT32 *HeapBufferPtr;
UINT32 *HeapRamPtr;
UINT64 MsrData;
HEAP_MANAGER *HeapManagerPtr;
BUFFER_NODE *CurrentNodePtr;
AGESA_STATUS IgnoredSts;
UINT32 AmdHeapRamAddress;
UINT32 HeapRamFixMtrr;
AmdHeapRamAddress = (UINT32) UserOptions.CfgHeapDramAddress;
//
//If the user define address above 1M, Mem Init has already set
//whole available memory as WB cacheable.
//
if (AmdHeapRamAddress < 0x100000) {
// Region below 1MB
// Fixed MTRR region
// turn on modification bit
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData |= 0x80000;
LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader);
if (AmdHeapRamAddress >= 0xC0000) {
//
// 0xC0000 ~ 0xFFFFF
//
HeapRamFixMtrr = (UINT32) (AMD_MTRR_FIX4k_C0000 + (((AmdHeapRamAddress >> 16) & 0x3) * 2));
MsrData = AMD_MTRR_FIX4K_WB_DRAM;
LibAmdMsrWrite (HeapRamFixMtrr, &MsrData, StdHeader);
LibAmdMsrWrite ((HeapRamFixMtrr + 1), &MsrData, StdHeader);
} else if (AmdHeapRamAddress >= 0x80000) {
//
// 0x80000~0xBFFFF
//
HeapRamFixMtrr = (UINT32) (AMD_MTRR_FIX16k_80000 + ((AmdHeapRamAddress >> 17) & 0x1));
MsrData = AMD_MTRR_FIX16K_WB_DRAM;
LibAmdMsrWrite (HeapRamFixMtrr, &MsrData, StdHeader);
} else {
//
// 0x0 ~ 0x7FFFF
//
LibAmdMsrRead (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader);
MsrData = MsrData & (~(0xFF << (8 * ((AmdHeapRamAddress >> 16) & 0x7))));
MsrData = MsrData | (AMD_MTRR_FIX64K_WB_DRAM << (8 * ((AmdHeapRamAddress >> 16) & 0x7)));
LibAmdMsrWrite (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader);
}
// Turn on MTRR enable bit and turn off modification bit
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData &= 0xFFFFFFFFFFF7FFFFull;
LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader);
}
// Copying Heap content
if (IsBsp (StdHeader, &IgnoredSts)) {
HeapBufferPtr = (UINT32 *)AMD_HEAP_START_ADDRESS;
HeapRamPtr = (UINT32 *)AmdHeapRamAddress;
for (i = 0; i < AMD_HEAP_COPY_SIZE_DWORD; i++) {
*HeapRamPtr = *HeapBufferPtr;
HeapBufferPtr++;
HeapRamPtr++;
}
// re-calculate NextNodePtr of every Heap
HeapManagerPtr = (HEAP_MANAGER *) AmdHeapRamAddress;
if (HeapManagerPtr->AvailableSize != AMD_HEAP_SIZE_PER_CORE - sizeof (HEAP_MANAGER)) {
CurrentNodePtr = (BUFFER_NODE *) (AmdHeapRamAddress + sizeof (HEAP_MANAGER));
while (CurrentNodePtr != NULL) {
if (CurrentNodePtr->NextNodePtr != NULL) {
CurrentNodePtr->NextNodePtr = (BUFFER_NODE *) ((UINT8 *) CurrentNodePtr->NextNodePtr - AMD_HEAP_START_ADDRESS + AmdHeapRamAddress);
}
CurrentNodePtr = CurrentNodePtr->NextNodePtr;
}
}
}
return AGESA_SUCCESS;
}
/* -----------------------------------------------------------------------------*/
/**
*
* CopyHeapToMainRamAtPost
*
* This function copies Temp Ram heap content to Main Ram
*
* @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct.
*
* @retval AGESA_STATUS
*
*/
AGESA_STATUS
CopyHeapToMainRamAtPost (
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 * HeapTempRamPtr;
UINT8 * HeapMainRamPtr;
UINT32 i;
HEAP_MANAGER *HeapManagerPtr;
BUFFER_NODE *CurrentNodePtr;
AGESA_BUFFER_PARAMS agesaAllocateBuffer;
AGESA_STATUS AgesaStatus;
UINT32 AmdHeapRamAddress;
AmdHeapRamAddress = (UINT32) UserOptions.CfgHeapDramAddress;
// initialize StdHeader
AgesaStatus = AGESA_SUCCESS;
agesaAllocateBuffer.StdHeader = *StdHeader;
HeapManagerPtr = (HEAP_MANAGER *) AmdHeapRamAddress;
CurrentNodePtr = (BUFFER_NODE *) (AmdHeapRamAddress + sizeof (HEAP_MANAGER));
if (HeapManagerPtr->AvailableSize != AMD_HEAP_SIZE_PER_CORE - sizeof (HEAP_MANAGER)) {
while (CurrentNodePtr != NULL) {
// allocate buffer
agesaAllocateBuffer.BufferHandle = CurrentNodePtr->BufferHandle;
agesaAllocateBuffer.BufferLength = CurrentNodePtr->BufferSize;
AgesaStatus = AgesaAllocateBuffer (0, &agesaAllocateBuffer);
if (AgesaStatus == AGESA_SUCCESS) {
// copy heap from temp ram to real ram
HeapMainRamPtr = (UINT8 *) agesaAllocateBuffer.BufferPointer;
HeapTempRamPtr = (UINT8 *) ((UINT8 *) CurrentNodePtr + sizeof (BUFFER_NODE));
for (i = 0; i < CurrentNodePtr->BufferSize; i++) {
*HeapMainRamPtr = *HeapTempRamPtr;
HeapMainRamPtr++;
HeapTempRamPtr++;
}
} else {
return AgesaStatus;
}
CurrentNodePtr = CurrentNodePtr->NextNodePtr;
}
}
return AGESA_SUCCESS;
}

119
src/vendorcode/amd/agesa/f10/MainPage.h
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@ -1,119 +0,0 @@
/**
* @file
*
* Create outline and references for mainpage documentation.
*
* Design guides, maintenance guides, and general documentation, are
* collected using this file onto the documentation mainpage.
* This file contains doxygen comment blocks, only.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Documentation
* @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/**
* @mainpage
*
* The design and maintenance documentation for AGESA Sample Code is organized as
* follows. On this page, you can reference design guides, maintenance guides, and
* general documentation. Detailed Data Structure, Function, and Interface documentation
* may be found using the Data Structures or Files tabs. See Related Pages for a
* Release content summary, and, if this is not a production release, lists of To Do's,
* Deprecated items, etc.
*
* @subpage starthere "Start Here - Initial Porting and Integration."
*
* @subpage optionmain "Build Configuration and Options Guides and Documentation."
*
* @subpage commonmain "Processor Common Component Guides and Documentation."
*
* @subpage cpumain "CPU Component Guides and Documentation."
*
* @subpage htmain "HT Component Guides and Documentation."
*
* @subpage memmain "MEM Component Guides and Documentation."
*
* @subpage gnbmain "GNB Component Documentation."
*
* @subpage idsmain "IDS Component Guides and Documentation."
*
* @subpage recoverymain "Recovery Component Guides and Documentation."
*
*/
/**
* @page starthere Initial Porting and Integration
*
* @par Basic Check List
*
* <ul>
* <li> Copy the \<plat\>Options.c file from the Addendum directory to the platform tip build directory.
* AMD recommends the use of a sub-directory named AGESA to contain these files and the build output files.
* <li> Copy the OptionsIds.h content in the spec to OptionsIds.h in the platform build tip directory
* and make changes to enable the IDS support desired. It is highly recommended to set the following for
* initial integration and development:@n
* @code
* #define IDSOPT_IDS_ENABLED TRUE
* #define IDSOPT_ERROR_TRAP_ENABLED TRUE
* #define IDSOPT_ASSERT_ENABLED TRUE
* @endcode
* <li> Edit and modify the option selections in those two files to meet the needs of the specific platform.
* <li> Set the environment variable AGESA_ROOT to the root folder of the AGESA code.
* <li> Set the environment variable AGESA_OptsDir the platform build tip AGESA directory.
* <li> Generate the doxygen documentation or locate the file arch2008.chm within your AGESA release package.
* </ul>
*
* @par Debugging Using ASSERT and IDS_ERROR_TRAP
*
* While AGESA code uses ::ASSERT and ::IDS_ERROR_TRAP to check for internal errors, these macros can also
* catch and assist debug of wrapper and platform BIOS issues.
*
* When an ::ASSERT fails or an ::IDS_ERROR_TRAP is executed, the AGESA code will enter a halt loop and display a
* Stop Code. A Stop Code is eight hex digits. The first (most significant) four are the FILECODE.
* FILECODEs can be looked up in Filecode.h to determine which file contains the stop macro. Each file has a
* unique code value.
* The least significant digits are the line number in that file.
* For example, 0210 means the macro is on line two hundred ten.
* (see ::IdsErrorStop for more details on stop code display.)
*
* Enabling ::ASSERT and ::IDS_ERROR_TRAP ensure errors are caught and also provide a useful debug assist.
* Comments near each macro use will describe the nature of the error and typical wrapper errors or other
* root causes.
*
* After your wrapper consistently executes ::ASSERT and ::IDS_ERROR_TRAP stop free, you can disable them in
* OptionsIds.h, except for regression testing. IDS is not expected to be enabled in production BIOS builds.
*
*/

325
src/vendorcode/amd/agesa/f10/Makefile.inc
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@ -1,325 +0,0 @@
#*****************************************************************************
#
# This file is part of the coreboot project.
#
# Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
#*****************************************************************************
# AGESA V5 Files
AGESA_ROOT = src/vendorcode/amd/agesa/f10
AGESA_INC = -I$(src)/vendorcode/amd/include -I$(src)/mainboard/$(MAINBOARDDIR)
AGESA_INC += -I$(AGESA_ROOT)
AGESA_INC += -I$(AGESA_ROOT)/../common
AGESA_INC += -I$(AGESA_ROOT)/Include
AGESA_INC += -I$(AGESA_ROOT)/Legacy
AGESA_INC += -I$(AGESA_ROOT)/Proc/Common
AGESA_INC += -I$(AGESA_ROOT)/Proc/HT
AGESA_INC += -I$(AGESA_ROOT)/Proc/HT/NbCommon
AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU
AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Feature
AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Family
AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Family/0x10
AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem
AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem/Feat/IDENDIMM/
AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem/NB/HY
AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem/Main
AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS
AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS/Family
AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS/Family/0x10
AGESA_INC += -I$(AGESA_ROOT)/Proc/Recovery/CPU
AGESA_INC += -I$(AGESA_ROOT)/Proc/Recovery/Mem
## AGESA need sse feature ##
CFLAGS_x86_32 += -msse3 -fno-zero-initialized-in-bss -fno-strict-aliasing
CFLAGS_x86_64 += -msse3 -fno-zero-initialized-in-bss -fno-strict-aliasing
export AGESA_ROOT := $(AGESA_ROOT)
export AGESA_INC := $(AGESA_INC)
CPPFLAGS_x86_32 += $(AGESA_INC)
CPPFLAGS_x86_64 += $(AGESA_INC)
#######################################################################
#libagesa-y += Proc/CPU/Family/0x10/F10IoCstate.c
#libagesa-y += Proc/CPU/Feature/cpuIoCstate.c
#libagesa-y += Proc/Mem/NB/ON/mnprotoon.c
libagesa-y += Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c4.c
libagesa-y += Proc/CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c
libagesa-y += Proc/CPU/cpuInitEarlyTable.c
libagesa-y += Proc/CPU/cahalt.c
libagesa-y += Proc/CPU/Feature/cpuC6State.c
libagesa-y += Proc/Mem/Main/mm.c
libagesa-y += Proc/CPU/Family/0x10/cpuCommonF10Utilities.c
libagesa-y += Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c
libagesa-y += Proc/Mem/Tech/mttml.c
libagesa-y += Proc/Mem/Tech/DDR3/mtrci3.c
libagesa-y += Proc/CPU/Feature/cpuCacheInit.c
libagesa-y += Proc/Mem/Tech/mttdimbt.c
libagesa-y += Proc/Mem/Tech/DDR3/mtsdi3.c
libagesa-y += Proc/Mem/Tech/mthdi.c
libagesa-y += Proc/Mem/NB/mnfeat.c
libagesa-y += Proc/Mem/Main/mmStandardTraining.c
libagesa-y += Proc/CPU/cpuBist.c
libagesa-y += Proc/Recovery/Mem/mrdef.c
libagesa-y += Proc/Mem/Main/mmParallelTraining.c
libagesa-y += Proc/Mem/Feat/LVDDR3/mflvddr3.c
libagesa-y += Proc/CPU/Family/0x10/cpuF10PowerPlane.c
libagesa-y += Proc/Mem/NB/mnreg.c
#libagesa-y += Proc/Common/AmdInitReset.c
#libagesa-y += Proc/Recovery/HT/htInitReset.c
libagesa-y += Proc/Mem/Feat/CHINTLV/mfchi.c
libagesa-y += Proc/Mem/Tech/mt.c
libagesa-y += Proc/Mem/NB/mnflow.c
libagesa-y += Proc/IDS/Debug/IdsDebug.c
libagesa-y += Proc/CPU/Feature/cpuFeatureLeveling.c
libagesa-y += Proc/Mem/Tech/mttoptsrc.c
libagesa-y += Proc/Mem/Feat/PARTRN/mfParallelTraining.c
libagesa-y += Proc/Mem/Main/mmEcc.c
libagesa-y += Legacy/Proc/Dispatcher.c
libagesa-y += Proc/Mem/Feat/MEMCLR/mfmemclr.c
libagesa-y += Proc/CPU/Feature/cpuDmi.c
libagesa-y += Proc/Mem/Tech/mttsrc.c
libagesa-y += Proc/Mem/NB/mnmct.c
libagesa-y += Proc/HT/htInterfaceNonCoherent.c
libagesa-y += Proc/CPU/Feature/cpuSrat.c
libagesa-y += Proc/Common/AmdS3LateRestore.c
libagesa-y += Proc/CPU/Table.c
libagesa-y += Proc/HT/htInterface.c
libagesa-y += Proc/IDS/Perf/IdsPerf.c
libagesa-y += Proc/CPU/Feature/cpuCacheFlushOnHalt.c
libagesa-y += Proc/Mem/Main/minit.c
libagesa-y += Proc/Mem/Feat/INTLVRN/mfintlvrn.c
libagesa-y += Proc/Mem/Feat/IDENDIMM/mfidendimm.c
libagesa-y += Proc/Mem/Main/mmflow.c
libagesa-y += Proc/Mem/Ardk/ma.c
libagesa-y += Proc/Common/CommonInits.c
libagesa-y += Proc/CPU/Feature/cpuPstateLeveling.c
libagesa-y += Proc/Common/AmdInitPost.c
libagesa-y += Proc/CPU/cpuBrandId.c
libagesa-y += Proc/Mem/NB/mnphy.c
libagesa-y += Proc/Common/AmdInitEnv.c
libagesa-y += Proc/Mem/Main/mmConditionalPso.c
libagesa-y += Proc/Common/CommonReturns.c
libagesa-y += Proc/CPU/cpuPowerMgmt.c
libagesa-y += Proc/Common/AmdInitResume.c
libagesa-y += Proc/Common/AmdInitEarly.c
libagesa-y += Proc/CPU/cpuFamilyTranslation.c
libagesa-y += Proc/CPU/cpuPostInit.c
libagesa-y += Proc/Mem/NB/mn.c
libagesa-y += Proc/CPU/Feature/cpuHwC1e.c
libagesa-y += Proc/CPU/cpuLateInit.c
libagesa-y += Proc/Common/CreateStruct.c
libagesa-y += Proc/CPU/Feature/cpuWhea.c
libagesa-y += Proc/Mem/Feat/CSINTLV/mfcsi.c
libagesa-y += Proc/Mem/Feat/ECC/mfecc.c
libagesa-y += Proc/Mem/Feat/DMI/mfDMI.c
libagesa-y += Proc/Common/AmdLateRunApTask.c
libagesa-y += Proc/CPU/cpuPowerMgmtMultiSocket.c
libagesa-y += Proc/Mem/Main/mmUmaAlloc.c
libagesa-y += Proc/CPU/Feature/cpuPstateTables.c
libagesa-y += Proc/CPU/cpuPowerMgmtSingleSocket.c
libagesa-y += Proc/Mem/Tech/DDR3/mt3.c
libagesa-y += Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
libagesa-y += Proc/Mem/Main/mmExcludeDimm.c
libagesa-y += Proc/HT/htInterfaceGeneral.c
libagesa-y += Proc/CPU/S3.c
libagesa-y += Proc/CPU/Feature/cpuFeatures.c
libagesa-y += Proc/Mem/Ps/mp.c
libagesa-y += Proc/Mem/Main/mdef.c
libagesa-y += Proc/Mem/Tech/mtthrc.c
libagesa-y += Proc/CPU/cpuGeneralServices.c
libagesa-y += Proc/HT/htNb.c
libagesa-y += Proc/CPU/Feature/cpuSlit.c
libagesa-y += Proc/Mem/Feat/ECC/mfemp.c
libagesa-y += Proc/Mem/Main/mmNodeInterleave.c
libagesa-y += Proc/Mem/Main/mu.c
libagesa-y += Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c
libagesa-y += Proc/IDS/Control/IdsCtrl.c
libagesa-y += Proc/Mem/Tech/mttEdgeDetect.c
libagesa-y += Proc/Common/AmdInitLate.c
libagesa-y += Proc/HT/htFeat.c
libagesa-y += Proc/CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c
libagesa-y += Legacy/Proc/hobTransfer.c
libagesa-y += Proc/CPU/cpuApicUtilities.c
#libagesa-y += Proc/Mem/Main/mmMemRestore.c
#libagesa-y += Proc/Recovery/Mem/NB/ON/mrnmcton.c
#libagesa-y += Proc/Recovery/Mem/NB/OR/mrnprotoor.c
#libagesa-y += Proc/Recovery/Mem/mrm.c
#libagesa-y += Proc/Recovery/Mem/mruc.c
#libagesa-y += Proc/Recovery/CPU/cpuRecovery.c
#libagesa-y += Proc/Recovery/HT/htInitRecovery.c
#libagesa-y += Proc/Recovery/Mem/NB/mrntrain3.c
#libagesa-y += Proc/Recovery/Mem/Tech/DDR3/mrtsdi3.c
#libagesa-y += Proc/Recovery/Mem/Tech/DDR3/mrt3.c
#libagesa-y += Proc/Recovery/Mem/Tech/DDR3/mrttwl3.c
#libagesa-y += Proc/Recovery/Mem/Tech/DDR3/mrtrci3.c
#libagesa-y += Proc/Recovery/Mem/NB/mrn.c
#libagesa-y += Proc/Recovery/Mem/Tech/mrttpos.c
#libagesa-y += Proc/Recovery/Mem/NB/mrnmct.c
#libagesa-y += Proc/Recovery/Mem/Tech/DDR3/mrtspd3.c
#libagesa-y += Proc/Recovery/Mem/NB/mrndct.c
#libagesa-y += Proc/Recovery/Mem/Tech/mrttsrc.c
#libagesa-y += Proc/Mem/NB/ON/mnS3on.c
libagesa-y += Proc/CPU/cpuEventLog.c
libagesa-y += Proc/HT/htInterfaceCoherent.c
libagesa-y += Proc/Mem/Main/muc.c
libagesa-y += Proc/Mem/Main/mmLvDdr3.c
libagesa-y += Proc/CPU/cpuMicrocodePatch.c
libagesa-y += Proc/Mem/Tech/mttecc.c
libagesa-y += Legacy/Proc/agesaCallouts.c
libagesa-y += Proc/Mem/Feat/ODTHERMAL/mfodthermal.c
libagesa-y += Proc/Mem/Feat/PARTRN/mfStandardTraining.c
libagesa-y += Proc/Mem/NB/mndct.c
libagesa-y += Proc/Mem/Main/mmOnlineSpare.c
libagesa-y += Proc/CPU/cpuEarlyInit.c
libagesa-y += Proc/Mem/Main/merrhdl.c
libagesa-y += Proc/Common/AmdS3Save.c
libagesa-y += Proc/IDS/Control/IdsLib.c
libagesa-y += Proc/Mem/Tech/DDR3/mtspd3.c
libagesa-y += Proc/HT/htMain.c
libagesa-y += Proc/CPU/cpuWarmReset.c
libagesa-y += Proc/Mem/Tech/DDR3/mttwl3.c
libagesa-y += Proc/CPU/Feature/cpuPstateGather.c
libagesa-y += Proc/Mem/Tech/DDR3/mtot3.c
libagesa-y += Proc/Mem/Main/mmMemClr.c
libagesa-y += Proc/Mem/Feat/TABLE/mftds.c
libagesa-y += Proc/Mem/Feat/S3/mfs3.c
libagesa-y += Proc/HT/htNotify.c
libagesa-y += Proc/Mem/NB/mnS3.c
libagesa-y += Proc/CPU/heapManager.c
libagesa-y += Proc/Mem/Tech/DDR3/mttecc3.c
libagesa-y += Proc/Common/AmdInitMid.c
libagesa-y += Proc/Mem/NB/mntrain3.c
libagesa-y += Proc/Common/S3SaveState.c
libagesa-y += Proc/Common/S3RestoreState.c
libagesa-y += Proc/Mem/Feat/OLSPARE/mfspr.c
libagesa-y += Proc/CPU/Feature/cpuMsgBasedC1e.c
libagesa-y += Proc/CPU/Feature/cpuCoreLeveling.c
libagesa-y += Proc/CPU/Feature/PreserveMailbox.c
libagesa-y += Proc/HT/NbCommon/htNbCoherent.c
libagesa-y += Proc/HT/NbCommon/htNbNonCoherent.c
libagesa-y += Proc/HT/NbCommon/htNbOptimization.c
libagesa-y += Proc/HT/NbCommon/htNbUtilities.c
libagesa-y += Proc/HT/Fam10/htNbCoherentFam10.c
libagesa-y += Proc/HT/Fam10/htNbOptimizationFam10.c
libagesa-y += Proc/HT/Fam10/htNbFam10.c
libagesa-y += Proc/HT/Fam10/htNbNonCoherentFam10.c
libagesa-y += Proc/HT/Fam10/htNbUtilitiesFam10.c
libagesa-y += Proc/HT/Fam10/htNbSystemFam10.c
libagesa-y += Proc/HT/Features/htFeatDynamicDiscovery.c
libagesa-y += Proc/HT/Features/htFeatSets.c
libagesa-y += Proc/HT/Features/htFeatGanging.c
libagesa-y += Proc/HT/Features/htFeatSublinks.c
libagesa-y += Proc/HT/Features/htFeatNoncoherent.c
libagesa-y += Proc/HT/Features/htFeatTrafficDistribution.c
libagesa-y += Proc/HT/Features/htFeatOptimization.c
libagesa-y += Proc/HT/Features/htIds.c
libagesa-y += Proc/HT/Features/htFeatRouting.c
libagesa-y += Proc/CPU/Family/0x10/cpuF10PciTables.c
libagesa-y += Proc/CPU/Family/0x10/cpuF10CacheDefaults.c
libagesa-y += Proc/CPU/Family/0x10/cpuF10PowerCheck.c
libagesa-y += Proc/CPU/Family/0x10/cpuF10BrandId.c
libagesa-y += Proc/CPU/Family/0x10/cpuF10Dmi.c
libagesa-y += Proc/CPU/Family/0x10/cpuF10Pstate.c
libagesa-y += Proc/CPU/Family/0x10/cpuF10SoftwareThermal.c
libagesa-y += Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c
libagesa-y += Proc/CPU/Family/0x10/cpuF10Utilities.c
libagesa-y += Proc/CPU/Family/0x10/cpuF10WheaInitDataTables.c
libagesa-y += Proc/CPU/Family/0x10/cpuF10MsrTables.c
libagesa-y += Proc/CPU/Family/0x10/cpuF10CacheFlushOnHalt.c
libagesa-y += Proc/CPU/Family/0x10/cpuF10PowerMgmtSystemTables.c
libagesa-y += Proc/CPU/Family/0x10/cpuF10EarlyInit.c
libagesa-y += Proc/CPU/Family/0x10/cpuF10BrandIdG34.c
##libagesa-y += Proc/CPU/Family/0x10/cpuF10BrandIdAm3.c
##libagesa-y += Proc/CPU/Family/0x10/cpuF10BrandIdAsb2.c
##libagesa-y += Proc/CPU/Family/0x10/cpuF10BrandIdC32.c
##libagesa-y += Proc/CPU/Family/0x10/cpuF10BrandIdFr1207.c
##libagesa-y += Proc/CPU/Family/0x10/cpuF10BrandIdS1g3.c
##libagesa-y += Proc/CPU/Family/0x10/cpuF10BrandIdS1g4.c
libagesa-y += Proc/CPU/Family/0x10/F10MultiLinkPciTables.c
libagesa-y += Proc/CPU/Family/0x10/cpuF10HtPhyTables.c
libagesa-y += Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c
libagesa-y += Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c
libagesa-y += Proc/CPU/Family/0x10/RevD/F10RevDHtAssist.c
libagesa-y += Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c
libagesa-y += Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c
libagesa-y += Proc/CPU/Family/0x10/RevD/HY/F10HyHtPhyTables.c
libagesa-y += Proc/HT/htGraph/htGraph1.c
libagesa-y += Proc/HT/htGraph/htGraph6DoubloonUpper.c
libagesa-y += Proc/HT/htGraph/htGraph2.c
libagesa-y += Proc/HT/htGraph/htGraph6FullyConnected.c
libagesa-y += Proc/HT/htGraph/htGraph3Line.c
libagesa-y += Proc/HT/htGraph/htGraph6TwinTriangles.c
libagesa-y += Proc/HT/htGraph/htGraph3Triangle.c
libagesa-y += Proc/HT/htGraph/htGraph6TwistedLadder.c
libagesa-y += Proc/HT/htGraph/htGraph4Degenerate.c
libagesa-y += Proc/HT/htGraph/htGraph7FullyConnected.c
libagesa-y += Proc/HT/htGraph/htGraph4FullyConnected.c
libagesa-y += Proc/HT/htGraph/htGraph7TwistedLadder.c
libagesa-y += Proc/HT/htGraph/htGraph4Kite.c
libagesa-y += Proc/HT/htGraph/htGraph8DoubloonM.c
libagesa-y += Proc/HT/htGraph/htGraph4Line.c
libagesa-y += Proc/HT/htGraph/htGraph8FullyConnected.c
libagesa-y += Proc/HT/htGraph/htGraph4Square.c
libagesa-y += Proc/HT/htGraph/htGraph8Ladder.c
libagesa-y += Proc/HT/htGraph/htGraph4Star.c
libagesa-y += Proc/HT/htGraph/htGraph8TwinFullyFourWays.c
libagesa-y += Proc/HT/htGraph/htGraph5FullyConnected.c
libagesa-y += Proc/HT/htGraph/htGraph8TwistedLadder.c
libagesa-y += Proc/HT/htGraph/htGraph5TwistedLadder.c
libagesa-y += Proc/HT/htGraph/htGraph.c
libagesa-y += Proc/HT/htGraph/htGraph6DoubloonLower.c
libagesa-y += Proc/Mem/Main/HY/mmflowhy.c
libagesa-y += Proc/Mem/Feat/NDINTLV/mfndi.c
libagesa-y += Proc/Mem/NB/HY/mnS3hy.c
libagesa-y += Proc/Mem/NB/HY/mnhy.c
libagesa-y += Proc/Mem/NB/HY/mndcthy.c
libagesa-y += Proc/Mem/NB/HY/mnflowhy.c
libagesa-y += Proc/Mem/NB/HY/mnidendimmhy.c
libagesa-y += Proc/Mem/NB/HY/mnmcthy.c
libagesa-y += Proc/Mem/NB/HY/mnothy.c
libagesa-y += Proc/Mem/NB/HY/mnParTrainHy.c
libagesa-y += Proc/Mem/NB/HY/mnphyhy.c
libagesa-y += Proc/Mem/NB/HY/mnprotohy.c
libagesa-y += Proc/Mem/NB/HY/mnreghy.c
libagesa-y += Proc/Mem/Ps/HY/mprhy3.c
libagesa-y += Proc/Mem/Ps/HY/mpuhy3.c
libagesa-y += Proc/Mem/Ps/HY/mpshy3.c
libagesa-y += Proc/Mem/Ardk/HY/marhy3.c
libagesa-y += Proc/Mem/Ardk/HY/mauhy3.c
libagesa-y += Proc/CPU/Feature/cpuHtAssist.c
libagesa-y += Proc/CPU/Family/0x10/F10PmNbCofVidInit.c
libagesa-y += Proc/CPU/Family/0x10/F10PmNbPstateInit.c
##C32
#libagesa-y += Proc/Mem/Main/C32/mmflowC32.c
$(obj)/libagesa.fam10.a: $$(libagesa-objs)
@printf " AGESA $(subst $(obj)/,,$(@))\n"
ar rcs $@ $+
romstage-libs += $(obj)/libagesa.fam10.a
ramstage-libs += $(obj)/libagesa.fam10.a

1442
src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10MultiLinkPciTables.c
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File diff suppressed because it is too large Load Diff

83
src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PackageType.h
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@ -1,83 +0,0 @@
/**
* @file
*
* AMD Family_10 Package Type Definitions
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F10
* @e \$Revision: 6524 $ @e \$Date: 2008-06-24 17:00:51 -0500 (Tue, 24 Jun 2008) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef _F10_PACKAGE_TYPE_H_
#define _F10_PACKAGE_TYPE_H_
/*---------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*---------------------------------------------------------------------------------------
*/
// Below equates are defined to cooperate with LibAmdGetPackageType.
#define PACKAGE_TYPE_FR2_FR5_FR6 (1 << 0)
#define PACKAGE_TYPE_AM2R2_AM3 (1 << 1)
#define PACKAGE_TYPE_S1G3_S1G4 (1 << 2)
#define PACKAGE_TYPE_G34 (1 << 3)
#define PACKAGE_TYPE_ASB2 (1 << 4)
#define PACKAGE_TYPE_C32 (1 << 5)
#define PACKAGE_TYPE_FR2 PACKAGE_TYPE_FR2_FR5_FR6
#define PACKAGE_TYPE_FR5 PACKAGE_TYPE_FR2_FR5_FR6
#define PACKAGE_TYPE_FR6 PACKAGE_TYPE_FR2_FR5_FR6
#define PACKAGE_TYPE_S1G3 PACKAGE_TYPE_S1G3_S1G4
#define PACKAGE_TYPE_S1G4 PACKAGE_TYPE_S1G3_S1G4
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*---------------------------------------------------------------------------------------
*/
#endif // _F10_PACKAGE_TYPE_H_

287
src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c
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@ -1,287 +0,0 @@
/**
* @file
*
* AMD Family_10 NB COF VID Initialization
*
* Performs the "BIOS Northbridge COF and VID Configuration" as
* described in the BKDG.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F10
* @e \$Revision: 6524 $ @e \$Date: 2008-06-24 17:00:51 -0500 (Tue, 24 Jun 2008) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "cpuRegisters.h"
#include "cpuF10PowerMgmt.h"
#include "cpuApicUtilities.h"
#include "OptionMultiSocket.h"
#include "cpuServices.h"
#include "GeneralServices.h"
#include "cpuFamilyTranslation.h"
#include "cpuF10Utilities.h"
#include "cpuCommonF10Utilities.h"
#include "F10PmNbCofVidInit.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X10_F10PMNBCOFVIDINIT_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/// Structure used for performing the steps outlined in
/// the NB COFVID configuration sequence
typedef struct {
UINT8 NewNbVid; ///< Destination NB VID code
BOOLEAN NbVidUpdateAll; ///< Status of NbVidUpdateAll
} NB_COF_VID_INIT_WARM;
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
STATIC
PmNbCofVidInitP0P1Core (
IN VOID *NewNbVid,
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID
STATIC
PmNbCofVidInitWarmCore (
IN VOID *FunctionData,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
/*---------------------------------------------------------------------------------------*/
/**
* Family 10h core 0 entry point for performing the "Northbridge COF and
* VID Configuration" algorithm.
*
* The steps are as follows:
* 1. Determine if the algorithm is necessary by checking if all NB FIDs
* match in the coherent fabric. If so, check to see if NbCofVidUpdate
* is zero for all CPUs. If that is also true, no further steps are
* necessary. If not + cold reset, proceed to step 2. If not + warm
* reset, proceed to step 8.
* 2. Determine NewNbVid & NewNbFid.
* 3. Copy Startup Pstate settings to P0/P1 MSRs on all local cores.
* 4. Copy NewNbVid to P0 NbVid on all local cores.
* 5. Transition to P1 on all local cores.
* 6. Transition to P0 on local core 0 only.
* 7. Copy NewNbFid to F3xD4[NbFid], set NbFidEn, and issue a warm reset.
* 8. Update all enabled Pstate MSRs' NbVids according to NbVidUpdateAll
* on all local cores.
* 9. Transition to Startup Pstate on all local cores.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] CpuEarlyParamsPtr Service related parameters (unused).
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
F10PmNbCofVidInit (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
BOOLEAN PerformNbCofVidCfg;
BOOLEAN SystemNbCofsMatch;
UINT8 NewNbFid;
UINT8 NewNbVid;
UINT32 Socket;
UINT32 Module;
UINT32 Core;
UINT32 SystemNbCof;
UINT32 AndMask;
UINT32 OrMask;
UINT32 Ignored;
UINT32 NewNbVoltage;
WARM_RESET_REQUEST Request;
AP_TASK TaskPtr;
PCI_ADDR PciAddress;
AGESA_STATUS IgnoredSts;
NB_COF_VID_INIT_WARM FunctionData;
PerformNbCofVidCfg = TRUE;
OptionMultiSocketConfiguration.GetSystemNbCof (&SystemNbCof, &SystemNbCofsMatch, StdHeader);
if (SystemNbCofsMatch) {
if (!OptionMultiSocketConfiguration.GetSystemNbCofVidUpdate (StdHeader)) {
PerformNbCofVidCfg = FALSE;
}
}
if (PerformNbCofVidCfg) {
// get the local node ID
IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
ASSERT (Core == 0);
// get NewNbVid
FamilySpecificServices->GetNbFrequency (FamilySpecificServices, &PciAddress, &Ignored, &NewNbVoltage, StdHeader);
ASSERT (((1550000 - NewNbVoltage) % 12500) == 0);
NewNbVid = (UINT8) ((1550000 - NewNbVoltage) / 12500);
ASSERT (NewNbVid < 0x80);
if (!(IsWarmReset (StdHeader))) {
// determine NewNbFid
NewNbFid = (UINT8) ((SystemNbCof / 200) - 4);
TaskPtr.FuncAddress.PfApTaskI = PmNbCofVidInitP0P1Core;
TaskPtr.DataTransfer.DataSizeInDwords = 1;
TaskPtr.DataTransfer.DataPtr = &NewNbVid;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.ExeFlags = 0;
ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
// Transition core 0 to P0 and wait for change to complete
FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) TRUE, StdHeader);
PciAddress.Address.Register = CPTC0_REG;
AndMask = 0xFFFFFFFF;
((CLK_PWR_TIMING_CTRL_REGISTER *) &AndMask)->NbFid = 0;
OrMask = 0x00000000;
((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->NbFid = NewNbFid;
((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->NbFidEn = 1;
ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
// warm reset request
FamilySpecificServices->GetWarmResetFlag (FamilySpecificServices, StdHeader, &Request);
Request.RequestBit = TRUE;
FamilySpecificServices->SetWarmResetFlag (FamilySpecificServices, StdHeader, &Request);
} else {
// warm reset path
FunctionData.NewNbVid = NewNbVid;
FamilySpecificServices->IsNbCofInitNeeded (FamilySpecificServices, &PciAddress, &FunctionData.NbVidUpdateAll, StdHeader);
TaskPtr.FuncAddress.PfApTaskI = PmNbCofVidInitWarmCore;
TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (NB_COF_VID_INIT_WARM);
TaskPtr.DataTransfer.DataPtr = &FunctionData;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.ExeFlags = WAIT_FOR_CORE;
ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
}
} // skip whole algorithm
}
/*---------------------------------------------------------------------------------------*/
/**
* Cold reset support routine for F10PmNbCofVidInit.
*
* This function implements steps 3, 4, & 5 on each core.
*
* @param[in] NewNbVid NewNbVid determined by core 0 in step 2.
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
STATIC
PmNbCofVidInitP0P1Core (
IN VOID *NewNbVid,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 MsrAddress;
UINT64 MsrRegister;
CPU_SPECIFIC_SERVICES *FamilySpecificServices = NULL;
GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
MsrAddress = (UINT32) ((((COFVID_STS_MSR *) &MsrRegister)->StartupPstate) + PS_REG_BASE);
LibAmdMsrRead (MsrAddress, &MsrRegister, StdHeader);
LibAmdMsrWrite ((UINT32) (PS_REG_BASE + 1), &MsrRegister, StdHeader);
((PSTATE_MSR *) &MsrRegister)->NbVid = *(UINT8 *) NewNbVid;
LibAmdMsrWrite (PS_REG_BASE, &MsrRegister, StdHeader);
FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 1, (BOOLEAN) FALSE, StdHeader);
}
/*---------------------------------------------------------------------------------------*/
/**
* Warm reset support routine for F10PmNbCofVidInit.
*
* This function implements steps 8 & 9 on each core.
*
* @param[in] FunctionData Contains NewNbVid determined by core 0 in step
* 2, and NbVidUpdateAll.
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
STATIC
PmNbCofVidInitWarmCore (
IN VOID *FunctionData,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 MsrAddress;
UINT64 MsrRegister;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
for (MsrAddress = PS_REG_BASE; MsrAddress <= PS_MAX_REG; MsrAddress++) {
LibAmdMsrRead (MsrAddress, &MsrRegister, StdHeader);
if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) {
if ((((PSTATE_MSR *) &MsrRegister)->NbDid == 0) || ((NB_COF_VID_INIT_WARM *) FunctionData)->NbVidUpdateAll) {
((PSTATE_MSR *) &MsrRegister)->NbVid = ((NB_COF_VID_INIT_WARM *) FunctionData)->NewNbVid;
LibAmdMsrWrite (MsrAddress, &MsrRegister, StdHeader);
}
}
}
LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) (((COFVID_STS_MSR *) &MsrRegister)->StartupPstate), (BOOLEAN) FALSE, StdHeader);
}

76
src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PmNbCofVidInit.h
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@ -1,76 +0,0 @@
/**
* @file
*
* AMD Family_10 NB COF VID Initialization
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F10
* @e \$Revision: 6524 $ @e \$Date: 2008-06-24 17:00:51 -0500 (Tue, 24 Jun 2008) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef _CPU_F10_PM_NB_COF_VID_INIT_H_
#define _CPU_F10_PM_NB_COF_VID_INIT_H_
/*---------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*---------------------------------------------------------------------------------------
*/
VOID
F10PmNbCofVidInit (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
IN AMD_CONFIG_PARAMS *StdHeader
);
#endif // _CPU_F10_PM_NB_COF_VID_INIT_H_

186
src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PmNbPstateInit.c
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@ -1,186 +0,0 @@
/**
* @file
*
* AMD Family_10 NB Pstate Initialization
*
* Performs the action described in F3x1F0[NbPstate] as
* described in the BKDG.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F10
* @e \$Revision: 6524 $ @e \$Date: 2008-06-24 17:00:51 -0500 (Tue, 24 Jun 2008) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "cpuRegisters.h"
#include "cpuF10PowerMgmt.h"
#include "cpuApicUtilities.h"
#include "GeneralServices.h"
#include "cpuFamilyTranslation.h"
#include "F10PmNbPstateInit.h"
#include "F10PackageType.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X10_F10PMNBPSTATEINIT_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/// Structure used for modifying the P-state
/// MSRs on fuse enable CPUs.
typedef struct {
UINT8 NbVid1; ///< Destination NB VID code
UINT8 NbPstate; ///< Status of NbVidUpdateAll
} NB_PSTATE_INIT;
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
STATIC
PmNbPstateInitCore (
IN VOID *NbPstateParams,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
* Family 10h core 0 entry point for performing the actions described in the
* description of F3x1F0[NbPstate].
*
* If F3x1F0[NbPstate] is non zero, it specifies the highest performance
* P-state in which to enable NbDid. Each core must loop through their
* P-state MSRs, enabling NbDid and changing NbVid to a lower voltage.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] CpuEarlyParamsPtr Service related parameters (unused).
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
F10PmNbPstateInit (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 Core;
UINT32 Module;
UINT32 PciRegister;
UINT32 ProcessorPackageType;
UINT32 Socket;
AP_TASK TaskPtr;
PCI_ADDR PciAddress;
AGESA_STATUS IgnoredSts;
NB_PSTATE_INIT ApParams;
if (FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, StdHeader)) {
ProcessorPackageType = LibAmdGetPackageType (StdHeader);
if ((CpuEarlyParamsPtr->PlatformConfig.PlatformProfile.PlatformPowerPolicy == BatteryLife) ||
(ProcessorPackageType != PACKAGE_TYPE_S1G3_S1G4)) {
IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
ASSERT (Core == 0);
GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
PciAddress.Address.Function = FUNC_3;
PciAddress.Address.Register = 0x1F0;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
if ((PciRegister & 0x00070000) != 0) {
ApParams.NbPstate = (UINT8) ((PciRegister & 0x00070000) >> 16);
ASSERT (ApParams.NbPstate < NM_PS_REG);
PciAddress.Address.Function = FUNC_4;
PciAddress.Address.Register = 0x1F4;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
ApParams.NbVid1 = (UINT8) ((PciRegister & 0x00003F80) >> 7);
TaskPtr.FuncAddress.PfApTaskI = PmNbPstateInitCore;
TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (NB_PSTATE_INIT);
TaskPtr.DataTransfer.DataPtr = &ApParams;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.ExeFlags = WAIT_FOR_CORE;
ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
}
}
}
}
/*---------------------------------------------------------------------------------------*/
/**
* Support routine for F10PmNbPstateInit.
*
* This function modifies NbVid and NbDid on each core.
*
* @param[in] NbPstateParams Appropriate NbVid1 and NbPstate as determined by core 0.
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
STATIC
PmNbPstateInitCore (
IN VOID *NbPstateParams,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 MsrAddress;
UINT64 MsrRegister;
for (MsrAddress = (PS_REG_BASE + ((NB_PSTATE_INIT *) NbPstateParams)->NbPstate); MsrAddress <= PS_MAX_REG; MsrAddress++) {
LibAmdMsrRead (MsrAddress, &MsrRegister, StdHeader);
if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) {
((PSTATE_MSR *) &MsrRegister)->NbDid = 1;
((PSTATE_MSR *) &MsrRegister)->NbVid = ((NB_PSTATE_INIT *) NbPstateParams)->NbVid1;
LibAmdMsrWrite (MsrAddress, &MsrRegister, StdHeader);
}
}
}

76
src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PmNbPstateInit.h
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@ -1,76 +0,0 @@
/**
* @file
*
* AMD Family_10 NB P-State Initialization
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F10
* @e \$Revision: 6524 $ @e \$Date: 2008-06-24 17:00:51 -0500 (Tue, 24 Jun 2008) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef _CPU_F10_PM_NB_PSTATE_INIT_H_
#define _CPU_F10_PM_NB_PSTATE_INIT_H_
/*---------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*---------------------------------------------------------------------------------------
*/
VOID
F10PmNbPstateInit (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
IN AMD_CONFIG_PARAMS *StdHeader
);
#endif // _CPU_F10_PM_NB_PSTATE_INIT_H_

1267
src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10SingleLinkPciTables.c
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File diff suppressed because it is too large Load Diff

146
src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c
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@ -1,146 +0,0 @@
/**
* @file
*
* AMD CPU Cache Flush On Halt Function.
*
* Contains code to Level the Feature in a multi-socket system
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x10/BL
* @e \$Revision: 10071 $ @e \$Date: 2008-12-17 08:03:04 +0800 (Wed, 17 Dec 2008) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*----------------------------------------------------------------------------
*/
/*
*----------------------------------------------------------------------------
* MODULES USED
*
*----------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "cpuServices.h"
#include "cpuFamilyTranslation.h"
#include "cpuPostInit.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLCACHEFLUSHONHALT_FILECODE
/*----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* TYPEDEFS AND STRUCTURES
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* PROTOTYPES OF LOCAL FUNCTIONS
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P U B L I C F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/* -----------------------------------------------------------------------------*/
/**
* Enable BL-C Cpu Cache Flush On Halt Function
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in,out] PciAddress Pointer to Pci address struct.
* @param[in,out] AndMask Pointer to AND mask bits.
* @param[in,out] OrMask Pointer to Or mask bits.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*/
VOID
GetF10BlCacheFlushOnHaltRegister (
IN CPU_CFOH_FAMILY_SERVICES *FamilySpecificServices,
IN OUT PCI_ADDR *PciAddress,
IN OUT UINT32 *AndMask,
IN OUT UINT32 *OrMask,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 CoreCount;
CPU_LOGICAL_ID CpuFamilyRevision;
GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
PciAddress->Address.Function = FUNC_3;
PciAddress->Address.Register = CLOCK_POWER_TIMING_CTRL2_REG;
if (CpuFamilyRevision.Revision == AMD_F10_BL_C3) {
//
// F3xDC[25:19] = 04h
// F3xDC[18:16] = 111b
//
*AndMask = 0xFC00FFFF;
*OrMask = 0x00270000;
} else {
//
// F3xDC[25:19] = 28h
// F3xDC[18:16] = 111b
//
*AndMask = 0xFC00FFFF;
*OrMask = 0x01470000;
//
//For BL_C2 single Core, F3xDC[18:16] = 0
//
GetActiveCoresInCurrentSocket (&CoreCount, StdHeader);
if (CoreCount == 1) {
if (CpuFamilyRevision.Revision == AMD_F10_BL_C2) {
*OrMask = 0x01400000;
}
}
}
}
CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10BlCacheFlushOnHalt =
{
0,
GetF10BlCacheFlushOnHaltRegister
};

102
src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c
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@ -1,102 +0,0 @@
/**
* @file
*
* AMD Family_10 BL Equivalence Table related data
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x10
* @e \$Revision: 6381 $ @e \$Date: 2008-06-15 17:26:25 -0500 (Sun, 15 Jun 2008) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuFamilyTranslation.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLEQUIVALENCETABLE_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
STATIC CONST UINT16 ROMDATA CpuF10BlMicrocodeEquivalenceTable[] =
{
0x1052, 0x1041,
0x1053, 0x1043
};
/*---------------------------------------------------------------------------------------*/
/**
* Returns the appropriate microcode patch equivalent ID table.
*
* @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[out] BlEquivalenceTablePtr Points to the first entry in the table.
* @param[out] NumberOfElements Number of valid entries in the table.
* @param[in] StdHeader Header for library and services.
*
*/
VOID
GetF10BlMicrocodeEquivalenceTable (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **BlEquivalenceTablePtr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
*NumberOfElements = ((sizeof (CpuF10BlMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
*BlEquivalenceTablePtr = CpuF10BlMicrocodeEquivalenceTable;
}

117
src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlHtPhyTables.c
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@ -1,117 +0,0 @@
/**
* @file
*
* AMD Family_10 BL PCI tables with values as defined in BKDG
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/FAMILY/0x10
* @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "Table.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLHTPHYTABLES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
// HT Phy T a b l e s
// -------------------------
STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10BlHtPhyRegisters[] =
{
//
// NOTE: This entry is here for making this array not to be empty.
// This entry should be removed after adding another.
//
//
// Deemphasis Settings
//
// For BL-C3, also set [7]TxLs23ClkGateEn.
//deemphasis level DL1[20:16], DL2[12:8], DP1[4:0] PostCur1En[31] PostCur2En[30] PreCur1En[29] MapPostCur2En[6]
// No deemphasis 00h 00h 00h 0 0 0 0
// -3dB postcursor 12h 00h 00h 1 0 0 0
// -6dB postcursor 1Fh 00h 00h 1 0 0 0
// -8dB postcursor 1Fh 06h 00h 1 1 0 1
// -11dB postcursor 1Fh 0Dh 00h 1 1 0 1
// -11dB postcursor with
// -8dB precursor 1Fh 06h 07h 1 1 1 1
{
DeemphasisRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_BL_C3 // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
DEEMPHASIS_LEVEL_NONE,
HTPHY_LINKTYPE_SL0_HT3, //
0xC5, // Address
0x00000080, // regData
0xE01F1FDF, // regMask
}
},
};
CONST REGISTER_TABLE ROMDATA F10BlHtPhyRegisterTable = {
PrimaryCores,
(sizeof (F10BlHtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
F10BlHtPhyRegisters
};

102
src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlLogicalIdTables.c
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@ -1,102 +0,0 @@
/**
* @file
*
* AMD Family_10 BL Logical ID Table
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/FAMILY/0x10
* @e \$Revision: 6261 $ @e \$Date: 2008-06-04 17:38:17 -0500 (Wed, 04 Jun 2008) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLLOGICALIDTABLES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
STATIC CONST CPU_LOGICAL_ID_XLAT ROMDATA CpuF10BlLogicalIdAndRevArray[] =
{
{
0x1052,
AMD_F10_BL_C2
},
{
0x1053,
AMD_F10_BL_C3
}
};
VOID
GetF10BlLogicalIdAndRev (
OUT CONST CPU_LOGICAL_ID_XLAT **BlIdPtr,
OUT UINT8 *NumberOfElements,
OUT UINT64 *LogicalFamily,
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
*NumberOfElements = (sizeof (CpuF10BlLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT));
*BlIdPtr = CpuF10BlLogicalIdAndRevArray;
*LogicalFamily = AMD_FAMILY_10_BL;
}
//CONST LOGICAL_ID_TABLE ROMDATA CpuF10BlLogicalIdAndRev =
//{
// (sizeof (CpuF10BlLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT)),
// (CPU_LOGICAL_ID_XLAT *) &CpuF10BlLogicalIdAndRevArray
//};

104
src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c
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@ -1,104 +0,0 @@
/**
* @file
*
* AMD Family_10 BL PCI tables with values as defined in BKDG
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x10
* @e \$Revision: 6049 $ @e \$Date: 2008-05-13 23:58:02 -0700 (Tue, 13 May 2008) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "cpuEarlyInit.h"
#include "cpuFamilyTranslation.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLMICROCODEPATCHTABLES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
extern CONST MICROCODE_PATCHES ROMDATA *CpuF10BlMicroCodePatchArray[];
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
* Returns a table containing the appropriate microcode patches.
*
* @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[out] BlUcodePtr Points to the first entry in the table.
* @param[out] NumberOfElements Number of valid entries in the table.
* @param[in] StdHeader Header for library and services.
*
*/
VOID
GetF10BlMicroCodePatchesStruct (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **BlUcodePtr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 NumberOfUcode;
for (NumberOfUcode = 0; CpuF10BlMicroCodePatchArray[NumberOfUcode] != 0; NumberOfUcode++) {
}
*NumberOfElements = NumberOfUcode;
*BlUcodePtr = &CpuF10BlMicroCodePatchArray[0];
}

101
src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlMsrTables.c
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@ -1,101 +0,0 @@
/**
* @file
*
* AMD Family_10 BL, MSR tables with values as defined in BKDG
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU
* @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "Table.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLMSRTABLES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10BlMsrRegisters[] =
{
// M S R T a b l e s
// ----------------------
//
// NOTE: This entry is here for making this array not to be empty.
// This entry should be removed after adding another.
//
// MSR_LS_CFG (0xC0011020)
// bit[1] = 0
{
MsrRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_GT_B0 // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
MSR_LS_CFG, // MSR Address
0x0000000000000000, // OR Mask
(1 << 1), // NAND Mask
}
}
};
CONST REGISTER_TABLE ROMDATA F10BlMsrRegisterTable = {
AllCores,
(sizeof (F10BlMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
(TABLE_ENTRY_FIELDS *) &F10BlMsrRegisters,
};

174
src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlPciTables.c
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@ -1,174 +0,0 @@
/**
* @file
*
* AMD Family_10 BL PCI tables with values as defined in BKDG
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/FAMILY/0x10
* @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "Table.h"
#include "F10PackageType.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLPCITABLES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
// P C I T a b l e s
// ----------------------
STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10BlPciRegisters[] =
{
// Function 0
// F0x16C - Link Global Extended Control Register, Errata 351
// bit[15:13] ForceFullT0 = 0
// bit[5:0] T0Time = 0x14
{
PciRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_BL_C2 // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
0x00000014, // regData
0x0000E03F, // regMask
}
},
// F0x16C - Link Global Extended Control Register
// bit[7:6] InLnSt = 0x01
{
PciRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_BL_C3 // CpuRevision
},
AMD_PF_SINGLE_LINK, // platformFeatures
{
MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
0x00000040, // regData
0x000000C0, // regMask
}
},
// F0x170 - Link Extended Control Register - Link 0, sublink 0
// Errata 351 (only need to override single link case.)
// bit[8] LS2En = 0,
{
PciRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_BL_C2 // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
MAKE_SBDFO (0, 0, 24, FUNC_0, 0x170), // Address
0x00000000, // regData
0x00000100, // regMask
}
},
// F3x80 - ACPI Power State Control
// ACPI FIDVID Change
// bits[0] CpuPrbEn = 1
// bits[1] NbLowPwrEn = 1
// bits[2] NbGateEn = 0
// bits[3] = 1
// bits[4] AltVidEn = 0
// bits[7:5] ClkDivisor = 0
{
HtFeatPciRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_BL_Cx // CpuRevision
},
AMD_PF_SINGLE_LINK, // platformFeatures
{
HT_HOST_FEATURES_ALL, // link feats
PACKAGE_TYPE_S1G3_S1G4, // package type
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80), // Address
0x000B0000, // regData
0x00FF0000, // regMask
}
},
// F3xA0 - Power Control Miscellaneous
// bits[28] NbPstateForce = 1
{
PciRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_BL_C3 // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0), // Address
0x10000000, // regData
0x10000000, // regMask
}
}
};
CONST REGISTER_TABLE ROMDATA F10BlPciRegisterTable = {
PrimaryCores,
(sizeof (F10BlPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
F10BlPciRegisters,
};

136
src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c
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@ -1,136 +0,0 @@
/**
* @file
*
* AMD CPU Cache Flush On Halt Function.
*
* Contains code to Level the Feature in a multi-socket system
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x10/DA
* @e \$Revision: 10071 $ @e \$Date: 2008-12-17 08:03:04 +0800 (Wed, 17 Dec 2008) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*----------------------------------------------------------------------------
*/
/*
*----------------------------------------------------------------------------
* MODULES USED
*
*----------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "cpuServices.h"
#include "cpuFamilyTranslation.h"
#include "cpuPostInit.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DACACHEFLUSHONHALT_FILECODE
/*----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* TYPEDEFS AND STRUCTURES
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* PROTOTYPES OF LOCAL FUNCTIONS
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P U B L I C F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/* -----------------------------------------------------------------------------*/
/**
* Enable DA-C Cpu Cache Flush On Halt Function
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in,out] PciAddress Pointer to Pci address struct.
* @param[in,out] AndMask Pointer to AND mask bits.
* @param[in,out] OrMask Pointer to Or mask bits.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*/
VOID
GetF10DaCacheFlushOnHaltRegister (
IN CPU_CFOH_FAMILY_SERVICES *FamilySpecificServices,
IN OUT PCI_ADDR *PciAddress,
IN OUT UINT32 *AndMask,
IN OUT UINT32 *OrMask,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 CoreCount;
CPU_LOGICAL_ID LogicalId;
//
// F3xDC[25:19] = 04h
// F3xDC[18:16] = 111b
//
PciAddress->Address.Function = FUNC_3;
PciAddress->Address.Register = CLOCK_POWER_TIMING_CTRL2_REG;
*AndMask = 0xFC00FFFF;
*OrMask = 0x00270000;
GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
if (LogicalId.Revision == AMD_F10_DA_C2) {
//
//For DA_C2 single Core, F3xDC[18:16] = 0
//
GetActiveCoresInCurrentSocket (&CoreCount, StdHeader);
if (CoreCount == 1) {
*OrMask = 0x00200000;
}
}
}
CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10DaCacheFlushOnHalt =
{
0,
GetF10DaCacheFlushOnHaltRegister
};

102
src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c
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@ -1,102 +0,0 @@
/**
* @file
*
* AMD Family_10 DA Equivalence Table related data
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x10
* @e \$Revision: 6381 $ @e \$Date: 2008-06-15 17:26:25 -0500 (Sun, 15 Jun 2008) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuFamilyTranslation.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DAEQUIVALENCETABLE_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
STATIC CONST UINT16 ROMDATA CpuF10DaMicrocodeEquivalenceTable[] =
{
0x1062, 0x1062,
0x1063, 0x1043
};
/*---------------------------------------------------------------------------------------*/
/**
* Returns the appropriate microcode patch equivalent ID table.
*
* @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[out] DaEquivalenceTablePtr Points to the first entry in the table.
* @param[out] NumberOfElements Number of valid entries in the table.
* @param[in] StdHeader Header for library and services.
*
*/
VOID
GetF10DaMicrocodeEquivalenceTable (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **DaEquivalenceTablePtr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
*NumberOfElements = ((sizeof (CpuF10DaMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
*DaEquivalenceTablePtr = CpuF10DaMicrocodeEquivalenceTable;
}

278
src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaHtPhyTables.c
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@ -1,278 +0,0 @@
/**
* @file
*
* AMD Family_10 DA PCI tables with values as defined in BKDG
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/FAMILY/0x10
* @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "Table.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DAHTPHYTABLES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
// HT Phy T a b l e s
// -------------------------
STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10DaHtPhyRegisters[] =
{
//
// Deemphasis Settings
//
// For DA, also set [7]TxLs23ClkGateEn.
//deemphasis level DL1[20:16], DL2[12:8], DP1[4:0] PostCur1En[31] PostCur2En[30] PreCur1En[29] MapPostCur2En[6]
// No deemphasis 00h 00h 00h 0 0 0 0
// -3dB postcursor 12h 00h 00h 1 0 0 0
// -6dB postcursor 1Fh 00h 00h 1 0 0 0
// -8dB postcursor 1Fh 06h 00h 1 1 0 1
// -11dB postcursor 1Fh 0Dh 00h 1 1 0 1
// -11dB postcursor with
// -8dB precursor 1Fh 06h 07h 1 1 1 1
{
DeemphasisRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_C2 // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
DEEMPHASIS_LEVEL_NONE,
HTPHY_LINKTYPE_SL0_HT3, //
0xC5, // Address
0x00000080, // regData
0xE01F1FDF, // regMask
}
},
{
DeemphasisRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_C2 // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
DEEMPHASIS_LEVEL_NONE,
HTPHY_LINKTYPE_SL1_HT3, //
0xD5, // Address
0x00000080, // regData
0xE01F1FDF, // regMask
}
},
{
DeemphasisRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_C2 // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
DEEMPHASIS_LEVEL__3,
HTPHY_LINKTYPE_SL0_HT3, //
0xC5, // Address
0x80120080, // regData
0xE01F1FDF, // regMask
}
},
{
DeemphasisRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_C2 // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
DEEMPHASIS_LEVEL__3,
HTPHY_LINKTYPE_SL1_HT3, //
0xD5, // Address
0x80120080, // regData
0xE01F1FDF, // regMask
}
},
{
DeemphasisRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_C2 // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
DEEMPHASIS_LEVEL__6,
HTPHY_LINKTYPE_SL0_HT3, //
0xC5, // Address
0x801F0080, // regData
0xE01F1FDF, // regMask
}
},
{
DeemphasisRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_C2 // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
DEEMPHASIS_LEVEL__6,
HTPHY_LINKTYPE_SL1_HT3, //
0xD5, // Address
0x801F0080, // regData
0xE01F1FDF, // regMask
}
},
{
DeemphasisRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_C2 // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
DEEMPHASIS_LEVEL__8,
HTPHY_LINKTYPE_SL0_HT3, //
0xC5, // Address
0xC01F06C0, // regData
0xE01F1FDF, // regMask
}
},
{
DeemphasisRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_C2 // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
DEEMPHASIS_LEVEL__8,
HTPHY_LINKTYPE_SL1_HT3, //
0xD5, // Address
0xC01F06C0, // regData
0xE01F1FDF, // regMask
}
},
{
DeemphasisRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_C2 // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
DEEMPHASIS_LEVEL__11,
HTPHY_LINKTYPE_SL0_HT3, //
0xC5, // Address
0xC01F0DC0, // regData
0xE01F1FDF, // regMask
}
},
{
DeemphasisRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_C2 // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
DEEMPHASIS_LEVEL__11,
HTPHY_LINKTYPE_SL1_HT3, //
0xD5, // Address
0xC01F0DC0, // regData
0xE01F1FDF, // regMask
}
},
{
DeemphasisRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_C2 // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
DEEMPHASIS_LEVEL__11_8,
HTPHY_LINKTYPE_SL0_HT3, //
0xC5, // Address
0xE01F06C7, // regData
0xE01F1FDF, // regMask
}
},
{
DeemphasisRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_C2 // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
DEEMPHASIS_LEVEL__11_8,
HTPHY_LINKTYPE_SL1_HT3, //
0xD5, // Address
0xE01F06C7, // regData
0xE01F1FDF, // regMask
}
},
};
CONST REGISTER_TABLE ROMDATA F10DaHtPhyRegisterTable = {
PrimaryCores,
(sizeof (F10DaHtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
F10DaHtPhyRegisters
};

102
src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaLogicalIdTables.c
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@ -1,102 +0,0 @@
/**
* @file
*
* AMD Family_10 DA Logical ID Table
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/FAMILY/0x10
* @e \$Revision: 6261 $ @e \$Date: 2008-06-04 17:38:17 -0500 (Wed, 04 Jun 2008) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DALOGICALIDTABLES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
STATIC CONST CPU_LOGICAL_ID_XLAT ROMDATA CpuF10DaLogicalIdAndRevArray[] =
{
{
0x1062,
AMD_F10_DA_C2
},
{
0x1063,
AMD_F10_DA_C3
}
};
VOID
GetF10DaLogicalIdAndRev (
OUT CONST CPU_LOGICAL_ID_XLAT **DaIdPtr,
OUT UINT8 *NumberOfElements,
OUT UINT64 *LogicalFamily,
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
*NumberOfElements = (sizeof (CpuF10DaLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT));
*DaIdPtr = CpuF10DaLogicalIdAndRevArray;
*LogicalFamily = AMD_FAMILY_10_DA;
}
//CONST LOGICAL_ID_TABLE ROMDATA CpuF10DaLogicalIdAndRev =
//{
// (sizeof (CpuF10DaLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT)),
// (CPU_LOGICAL_ID_XLAT *) &CpuF10DaLogicalIdAndRevArray
//};

104
src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c
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@ -1,104 +0,0 @@
/**
* @file
*
* AMD Family_10 DA PCI tables with values as defined in BKDG
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x10
* @e \$Revision: 6049 $ @e \$Date: 2008-05-13 23:58:02 -0700 (Tue, 13 May 2008) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "cpuEarlyInit.h"
#include "cpuFamilyTranslation.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DAMICROCODEPATCHTABLES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
extern CONST MICROCODE_PATCHES ROMDATA *CpuF10DaMicroCodePatchArray[];
/*---------------------------------------------------------------------------------------*/
/**
* Returns a table containing the appropriate microcode patches.
*
* @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[out] DaUcodePtr Points to the first entry in the table.
* @param[out] NumberOfElements Number of valid entries in the table.
* @param[in] StdHeader Header for library and services.
*
*/
VOID
GetF10DaMicroCodePatchesStruct (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **DaUcodePtr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 NumberOfUcode;
for (NumberOfUcode = 0; CpuF10DaMicroCodePatchArray[NumberOfUcode] != 0; NumberOfUcode++) {
}
*NumberOfElements = NumberOfUcode;
*DaUcodePtr = &CpuF10DaMicroCodePatchArray[0];
}

101
src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaMsrTables.c
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/**
* @file
*
* AMD Family_10 DA, MSR tables with values as defined in BKDG
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU
* @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "Table.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DAMSRTABLES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10DaMsrRegisters[] =
{
// M S R T a b l e s
// ----------------------
//
// NOTE: This entry is here for making this array not to be empty.
// This entry should be removed after adding another.
//
// MSR_LS_CFG (0xC0011020)
// bit[1] = 0
{
MsrRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_GT_B0 // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
MSR_LS_CFG, // MSR Address
0x0000000000000000, // OR Mask
(1 << 1), // NAND Mask
}
}
};
CONST REGISTER_TABLE ROMDATA F10DaMsrRegisterTable = {
AllCores,
(sizeof (F10DaMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
(TABLE_ENTRY_FIELDS *) &F10DaMsrRegisters,
};

172
src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaPciTables.c
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@ -1,172 +0,0 @@
/**
* @file
*
* AMD Family_10 DA PCI tables with values as defined in BKDG
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/FAMILY/0x10
* @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "Table.h"
#include "F10PackageType.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DAPCITABLES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
// P C I T a b l e s
// ----------------------
STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10DaPciRegisters[] =
{
// F0x16C - Link Global Extended Control Register
// bit[7:6] InLnSt = 0x01
{
PciRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_DA_ALL // CpuRevision
},
AMD_PF_SINGLE_LINK, // platformFeatures
{
MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
0x00000040, // regData
0x000000C0, // regMask
}
},
// F3x80 - ACPI Power State Control
// ACPI FIDVID Change
// bits[0] CpuPrbEn = 1
// bits[1] NbLowPwrEn = 1
// bits[2] NbGateEn = 0
// bits[3] = 1
// bits[4] AltVidEn = 0
// bits[7:5] ClkDivisor = 0
{
HtFeatPciRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_DA_Cx // CpuRevision
},
AMD_PF_SINGLE_LINK, // platformFeatures
{
HT_HOST_FEATURES_ALL, // link feats
PACKAGE_TYPE_S1G3_S1G4, // package type
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80), // Address
0x000B0000, // regData
0x00FF0000, // regMask
}
},
// F3xA0 - Power Control Miscellaneous
// bits[13:11] PllLockTime = 1
// bits[28] NbPstateForce = 1
{
PciRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_DA_ALL // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0), // Address
0x10000800, // regData
0x10003800, // regMask
}
},
// F3xD4 - Clock Power/Timing Control 0 Register
// bits[30:28] NbClkDiv = 5
{
HtFeatPciRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_DA_C2 // CpuRevision
},
AMD_PF_SINGLE_LINK, // platformFeatures
{
HT_HOST_FEAT_HT3, // link feats
PACKAGE_TYPE_S1G3_S1G4, // package type
MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD4), // Address
0x50000000, // regData
0x70000000, // regMask
}
},
// F3x188 - NB Extended Configuration Low Register
// bits[4] EnStpGntOnFlushMaskWakeup = 1
{
PciRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_DA_Cx // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x188), // Address
0x00000010, // regData
0x00000010, // regMask
}
}
};
CONST REGISTER_TABLE ROMDATA F10DaPciRegisterTable = {
PrimaryCores,
(sizeof (F10DaPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
F10DaPciRegisters,
};

1035
src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c
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src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000086.c
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src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000098.c
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src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000b6.c
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436
src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10RevCHtPhyTables.c
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@ -1,436 +0,0 @@
/**
* @file
*
* AMD Family_10 Rev C HT PCI tables with values as defined in BKDG
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/FAMILY/0x10
* @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "Table.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCHTPHYTABLES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
// HT Phy T a b l e s
// -------------------------
STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10RevCHtPhyRegisters[] =
{
// 0x60:0x68
{
HtPhyRangeRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_GT_C0 // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
HTPHY_LINKTYPE_SL0_ALL, //
0x60, 0x68, // Address range
0x00000040, // regData
0x00000040, // regMask
}
},
// 0x70:0x78
{
HtPhyRangeRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_GT_C0 // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
HTPHY_LINKTYPE_SL1_ALL, //
0x70, 0x78, // Address range
0x00000040, // regData
0x00000040, // regMask
}
},
// Erratum 354
// 0x40:48
{
HtPhyRangeRegister,
{
AMD_FAMILY_10, // CpuFamily
(AMD_F10_C2 | AMD_F10_C3) // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
HTPHY_LINKTYPE_SL0_HT3, //
0x40, 0x48, // Address
0x00000040, // regData
0x00000040, // regMask
}
},
// 0x50:0x58
{
HtPhyRangeRegister,
{
AMD_FAMILY_10, // CpuFamily
(AMD_F10_C2 | AMD_F10_C3) // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
HTPHY_LINKTYPE_SL1_HT3, //
0x50, 0x58, // Address
0x00000040, // regData
0x00000040, // regMask
}
},
// 0xC0
{
HtPhyRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_Cx // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
HTPHY_LINKTYPE_SL0_ALL, //
0xC0, // Address
0x40040000, // regData
0xe01F0000, // regMask
}
},
// 0xD0
{
HtPhyRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_Cx // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
HTPHY_LINKTYPE_SL1_ALL, //
0xD0, // Address
0x40040000, // regData
0xe01F0000, // regMask
}
},
// 0xCF
// FIFO_PTR_OPT_VALUE
{
HtPhyProfileRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_C3 // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
PERFORMANCE_NB_PSTATES_ENABLE,
HTPHY_LINKTYPE_SL0_HT3, //
0xCF, // Address
0x0000004A, // regData
0x000000FF, // regMask
}
},
// 0xDF
// FIFO_PTR_OPT_VALUE
{
HtPhyProfileRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_C3 // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
PERFORMANCE_NB_PSTATES_ENABLE,
HTPHY_LINKTYPE_SL1_HT3, //
0xDF, // Address
0x0000004A, // regData
0x000000FF, // regMask
}
},
// 0x520A
{
HtPhyRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_Cx // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
HTPHY_LINKTYPE_SL0_ALL, //
0x520A, // Address
0x00004000, // regData
0x00006000, // regMask
}
},
// 0x530A
{
HtPhyRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_Cx // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
HTPHY_LINKTYPE_SL1_ALL, //
0x530A, // Address
0x00004000, // regData
0x00006000, // regMask
}
},
//
// Deemphasis Settings
//
// For C3, also set [7]TxLs23ClkGateEn.
//deemphasis level DL1[20:16], DL2[12:8], DP1[4:0] PostCur1En[31] PostCur2En[30] PreCur1En[29] MapPostCur2En[6]
// No deemphasis 00h 00h 00h 0 0 0 0
// -3dB postcursor 12h 00h 00h 1 0 0 0
// -6dB postcursor 1Fh 00h 00h 1 0 0 0
// -8dB postcursor 1Fh 06h 00h 1 1 0 1
// -11dB postcursor 1Fh 0Dh 00h 1 1 0 1
// -11dB postcursor with
// -8dB precursor 1Fh 06h 07h 1 1 1 1
{
DeemphasisRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_C3 // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
DEEMPHASIS_LEVEL_NONE,
HTPHY_LINKTYPE_SL0_HT3, //
0xC5, // Address
0x00000080, // regData
0xE01F1FDF, // regMask
}
},
{
DeemphasisRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_C3 // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
DEEMPHASIS_LEVEL_NONE,
HTPHY_LINKTYPE_SL1_HT3, //
0xD5, // Address
0x00000080, // regData
0xE01F1FDF, // regMask
}
},
{
DeemphasisRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_C3 // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
DEEMPHASIS_LEVEL__3,
HTPHY_LINKTYPE_SL0_HT3, //
0xC5, // Address
0x80120080, // regData
0xE01F1FDF, // regMask
}
},
{
DeemphasisRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_C3 // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
DEEMPHASIS_LEVEL__3,
HTPHY_LINKTYPE_SL1_HT3, //
0xD5, // Address
0x80120080, // regData
0xE01F1FDF, // regMask
}
},
{
DeemphasisRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_C3 // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
DEEMPHASIS_LEVEL__6,
HTPHY_LINKTYPE_SL0_HT3, //
0xC5, // Address
0x801F0080, // regData
0xE01F1FDF, // regMask
}
},
{
DeemphasisRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_C3 // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
DEEMPHASIS_LEVEL__6,
HTPHY_LINKTYPE_SL1_HT3, //
0xD5, // Address
0x801F0080, // regData
0xE01F1FDF, // regMask
}
},
{
DeemphasisRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_C3 // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
DEEMPHASIS_LEVEL__8,
HTPHY_LINKTYPE_SL0_HT3, //
0xC5, // Address
0xC01F06C0, // regData
0xE01F1FDF, // regMask
}
},
{
DeemphasisRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_C3 // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
DEEMPHASIS_LEVEL__8,
HTPHY_LINKTYPE_SL1_HT3, //
0xD5, // Address
0xC01F06C0, // regData
0xE01F1FDF, // regMask
}
},
{
DeemphasisRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_C3 // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
DEEMPHASIS_LEVEL__11,
HTPHY_LINKTYPE_SL0_HT3, //
0xC5, // Address
0xC01F0DC0, // regData
0xE01F1FDF, // regMask
}
},
{
DeemphasisRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_C3 // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
DEEMPHASIS_LEVEL__11,
HTPHY_LINKTYPE_SL1_HT3, //
0xD5, // Address
0xC01F0DC0, // regData
0xE01F1FDF, // regMask
}
},
{
DeemphasisRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_C3 // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
DEEMPHASIS_LEVEL__11_8,
HTPHY_LINKTYPE_SL0_HT3, //
0xC5, // Address
0xE01F06C7, // regData
0xE01F1FDF, // regMask
}
},
{
DeemphasisRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_C3 // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
DEEMPHASIS_LEVEL__11_8,
HTPHY_LINKTYPE_SL1_HT3, //
0xD5, // Address
0xE01F06C7, // regData
0xE01F1FDF, // regMask
}
},
};
CONST REGISTER_TABLE ROMDATA F10RevCHtPhyRegisterTable = {
PrimaryCores,
(sizeof (F10RevCHtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
F10RevCHtPhyRegisters
};

178
src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c
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@ -1,178 +0,0 @@
/**
* @file
*
* AMD Family_10 HW C1e feature support functions.
*
* Provides the functions necessary to initialize the hardware C1e feature.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F10
* @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "cpuRegisters.h"
#include "cpuHwC1e.h"
#include "cpuApicUtilities.h"
#include "cpuF10PowerMgmt.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCHWC1E_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
STATIC
F10InitializeHwC1eOnCore (
IN VOID *IntPendMsr,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
* Should hardware C1e be enabled
*
* @param[in] HwC1eServices Pointer to this CPU's HW C1e family services.
* @param[in] StdHeader Config Handle for library, services.
*
* @retval TRUE HW C1e is supported.
*
*/
BOOLEAN
STATIC
F10IsHwC1eSupported (
IN HW_C1E_FAMILY_SERVICES *HwC1eServices,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
return TRUE;
}
/*---------------------------------------------------------------------------------------*/
/**
* Enable Hardware C1e on a family 10h CPU.
*
* @param[in] HwC1eServices Pointer to this CPU's HW C1e family services.
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] StdHeader Config Handle for library, services.
*
* @return AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
F10InitializeHwC1e (
IN HW_C1E_FAMILY_SERVICES *HwC1eServices,
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 MsrRegister;
AP_TASK TaskPtr;
MsrRegister = 0;
((INTPEND_MSR *) &MsrRegister)->IoMsgAddr = PlatformConfig->C1ePlatformData;
((INTPEND_MSR *) &MsrRegister)->IoMsgData = 0xC1;
((INTPEND_MSR *) &MsrRegister)->IoRd = 1;
((INTPEND_MSR *) &MsrRegister)->C1eOnCmpHalt = 1;
((INTPEND_MSR *) &MsrRegister)->SmiOnCmpHalt = 0;
TaskPtr.FuncAddress.PfApTaskI = F10InitializeHwC1eOnCore;
TaskPtr.DataTransfer.DataSizeInDwords = 2;
TaskPtr.DataTransfer.DataPtr = &MsrRegister;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.ExeFlags = WAIT_FOR_CORE;
ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL);
return AGESA_SUCCESS;
}
/*---------------------------------------------------------------------------------------*/
/**
* Enable Hardware C1e on a family 10h core.
*
* @param[in] IntPendMsr MSR value to write to C001_0055 as determined by core 0.
* @param[in] StdHeader Config Handle for library, services.
*
*/
VOID
STATIC
F10InitializeHwC1eOnCore (
IN VOID *IntPendMsr,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 MsrRegister;
// Enable C1e
LibAmdMsrWrite (MSR_INTPEND, (UINT64 *) IntPendMsr, StdHeader);
// Set OS Visible Workaround Status BIT1 to indicate that C1e
// is enabled.
LibAmdMsrRead (MSR_OSVW_Status, &MsrRegister, StdHeader);
MsrRegister |= BIT1;
LibAmdMsrWrite (MSR_OSVW_Status, &MsrRegister, StdHeader);
}
CONST HW_C1E_FAMILY_SERVICES ROMDATA F10HwC1e =
{
0,
F10IsHwC1eSupported,
F10InitializeHwC1e
};

130
src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10RevCMsrTables.c
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@ -1,130 +0,0 @@
/**
* @file
*
* AMD Family_10 Rev C, MSR tables with values as defined in BKDG
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU
* @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "Table.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCMSRTABLES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10RevCMsrRegisters[] =
{
// M S R T a b l e s
// ----------------------
// MSR_LS_CFG (0xC0011020)
// bit[1] = 0
{
MsrRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_GT_B0 // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
MSR_LS_CFG, // MSR Address
0x0000000000000000, // OR Mask
(1 << 1), // NAND Mask
}
},
// MSR_BU_CFG (0xC0011023)
// bit[21] = 1
{
MsrRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_GT_B0 // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
MSR_BU_CFG, // MSR Address
(1 << 21), // OR Mask
(1 << 21), // NAND Mask
}
},
// MSR_BU_CFG2 (0xC001102A)
// bit[50] = 1
// For GH rev C1 and later [RdMmExtCfgQwEn]=1
{
MsrRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_GT_C0 // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
MSR_BU_CFG2, // MSR Address
0x0004000000000000, // OR Mask
0x0004000000000000, // NAND Mask
}
},
};
CONST REGISTER_TABLE ROMDATA F10RevCMsrRegisterTable = {
AllCores,
(sizeof (F10RevCMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
(TABLE_ENTRY_FIELDS *) &F10RevCMsrRegisters,
};

261
src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10RevCPciTables.c
View File

@ -1,261 +0,0 @@
/**
* @file
*
* AMD Family_10 Rev C PCI tables with values as defined in BKDG
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/FAMILY/0x10/RevC
* @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "Table.h"
#include "F10PackageType.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCPCITABLES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
// P C I T a b l e s
// ----------------------
STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10RevCPciRegisters[] =
{
// Function 2 - DRAM Controller
// F2x1B0 - Extended Memory Controller Configuration Low Register
//
// bit[5:4], AdapPrefNegativeStep = 0
{
PciRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_Cx // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
MAKE_SBDFO (0, 0, 24, FUNC_2, 0x1B0), // Address
0x00000000, // regData
0x00000030, // regMask
}
},
// Function 3 - Misc. Control
// F3x158 - Link to XCS Token Count
// bits[3:0] LnkToXcsDRToken = 3
{
PciRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_GT_A2 // CpuRevision
},
AMD_PF_UMA, // platformFeatures
{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x158), // Address
0x00000003, // regData
0x0000000F, // regMask
}
},
// F3x80 - ACPI Power State Control
// ACPI State C2
// bits[0] CpuPrbEn = 1
// bits[1] NbLowPwrEn = 0
// bits[2] NbGateEn = 0
// bits[3] = 0
// bits[4] AltVidEn = 0
// bits[7:5] ClkDivisor = 1
// ACPI State C3, C1E or Link init
// bits[0] CpuPrbEn = 0
// bits[1] NbLowPwrEn = 1
// bits[2] NbGateEn = 1
// bits[3] = 0
// bits[4] AltVidEn = 0
// bits[7:5] ClkDivisor = 7
{
PciRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_Cx // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80), // Address
0x0000E681, // regData
0x0000FFFF, // regMask
}
},
// F3x80 - ACPI Power State Control
// ACPI State C3, C1E or Link init
// bits[0] CpuPrbEn = 1
// bits[1] NbLowPwrEn = 1
// bits[2] NbGateEn = 1
// bits[3] = 0
// bits[4] AltVidEn = 0
// bits[7:5] ClkDivisor = 4
{
HtFeatPciRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_Cx // CpuRevision
},
AMD_PF_SINGLE_LINK, // platformFeatures
{
HT_HOST_FEAT_HT1, // link feats
PACKAGE_TYPE_ASB2, // package type
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80), // Address
0x00008700, // regData
0x0000FF00, // regMask
}
},
// F3x80 - ACPI Power State Control
// ACPI State C3, C1E or Link init
// bits[0] CpuPrbEn = 0
// bits[1] NbLowPwrEn = 1
// bits[2] NbGateEn = 1
// bits[3] = 0
// bits[4] AltVidEn = 1
// bits[7:5] ClkDivisor = 7
{
ProfileFixup,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_C3 // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
PERFORMANCE_VRM_HIGH_SPEED_ENABLE, // PerformanceFeatures
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80), // Address
0x0000F600, // regData
0x0000FF00, // regMask
}
},
// F3x80 - ACPI Power State Control
// ACPI State C3, C1E or Link init
// bits[0] CpuPrbEn = 1
// bits[1] NbLowPwrEn = 1
// bits[2] NbGateEn = 1
// bits[3] = 0
// bits[4] AltVidEn = 0
// bits[7:5] ClkDivisor = 4
{
HtFeatPciRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_Cx // CpuRevision
},
AMD_PF_SINGLE_LINK, // platformFeatures
{
HT_HOST_FEAT_HT1, // link feats
PACKAGE_TYPE_ALL & (~ PACKAGE_TYPE_ASB2), // package type
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80), // Address
0x00008700, // regData
0x0000FF00, // regMask
}
},
// F3xDC - Clock Power Timing Control 2
// bits[14:12] NbsynPtrAdj = 5
{
PciRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_Cx // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC), // Address
0x00005000, // regData
0x00007000, // regMask
}
},
// F3x180 - NB Extended Configuration
// bits[23] SyncFloodOnDramTempErr = 1
{
PciRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_Cx // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x180), // Address
0x00800000, // regData
0x00800000, // regMask
}
},
// F3x188 - NB Extended Configuration Low Register
// Must be set by BIOS
{
PciRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_Cx // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x188), // Address
0x00400000, // regData
0x00400000, // regMask
}
}
};
CONST REGISTER_TABLE ROMDATA F10RevCPciRegisterTable = {
PrimaryCores,
(sizeof (F10RevCPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
F10RevCPciRegisters,
};

401
src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c
View File

@ -1,401 +0,0 @@
/**
* @file
*
* AMD Family_10 revision Cx specific utility functions.
*
* Provides numerous utility functions specific to family 10h rev C.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F10
* @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "cpuRegisters.h"
#include "cpuFamilyTranslation.h"
#include "cpuF10PowerMgmt.h"
#include "GeneralServices.h"
#include "cpuEarlyInit.h"
#include "cpuPostInit.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCUTILITIES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
* Set down core register on a revision C processor.
*
* This function set F3x190 Downcore Control Register[5:0]
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] Socket Socket ID.
* @param[in] Module Module ID in socket.
* @param[in] LeveledCores Number of core.
* @param[in] StdHeader Header for library and services.
*
*/
VOID
F10CommonRevCSetDownCoreRegister (
IN CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices,
IN UINT32 *Socket,
IN UINT32 *Module,
IN UINT32 *LeveledCores,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 TempVar32_a;
UINT32 CoreDisableBits;
PCI_ADDR PciAddress;
AGESA_STATUS AgesaStatus;
switch (*LeveledCores) {
case 1:
CoreDisableBits = DOWNCORE_MASK_SINGLE;
break;
case 2:
CoreDisableBits = DOWNCORE_MASK_DUAL;
break;
case 3:
CoreDisableBits = DOWNCORE_MASK_TRI;
break;
default:
CoreDisableBits = 0;
break;
}
if (CoreDisableBits != 0) {
if (GetPciAddress (StdHeader, (UINT8) *Socket, (UINT8) *Module, &PciAddress, &AgesaStatus)) {
PciAddress.Address.Function = FUNC_3;
PciAddress.Address.Register = NORTH_BRIDGE_CAPABILITIES_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);
TempVar32_a = (TempVar32_a >> 12) & 0x3;
if (TempVar32_a == 0) {
CoreDisableBits &= 0x1;
} else if (TempVar32_a == 1) {
CoreDisableBits &= 0x3;
} else if (TempVar32_a == 2) {
CoreDisableBits &= 0x7;
} else if (TempVar32_a == 3) {
CoreDisableBits &= 0x0F;
}
PciAddress.Address.Register = DOWNCORE_CTRL;
LibAmdPciRead (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);
TempVar32_a |= CoreDisableBits;
LibAmdPciWrite (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);
}
}
return;
}
CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevCCoreLeveling =
{
0,
F10CommonRevCSetDownCoreRegister
};
/*---------------------------------------------------------------------------------------*/
/**
* Get CPU pstate current on a revision C processor.
*
* @CpuServiceMethod{::F_CPU_GET_IDD_MAX}.
*
* This function returns the ProcIddMax.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] Pstate The P-state to check.
* @param[out] ProcIddMax P-state current in mA.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
* @retval TRUE P-state is enabled
* @retval FALSE P-state is disabled
*/
BOOLEAN
F10CommonRevCGetProcIddMax (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN UINT8 Pstate,
OUT UINT32 *ProcIddMax,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 IddDiv;
UINT32 CmpCap;
UINT32 PciRegister;
UINT32 Socket;
UINT32 Module;
UINT32 Ignored;
UINT32 MsrAddress;
UINT32 SinglePlaneNbIdd;
UINT64 PstateMsr;
BOOLEAN IsPstateEnabled;
PCI_ADDR PciAddress;
AGESA_STATUS IgnoredSts;
IsPstateEnabled = FALSE;
MsrAddress = (UINT32) (Pstate + PS_REG_BASE);
ASSERT (MsrAddress <= PS_MAX_REG);
LibAmdMsrRead (MsrAddress, &PstateMsr, StdHeader);
if (((PSTATE_MSR *) &PstateMsr)->PsEnable == 1) {
IdentifyCore (StdHeader, &Socket, &Module, &Ignored, &IgnoredSts);
GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
PciAddress.Address.Function = FUNC_3;
PciAddress.Address.Register = NB_CAPS_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); // F3xE8
CmpCap = (UINT32) (((NB_CAPS_REGISTER *) &PciRegister)->CmpCapLo);
CmpCap++;
switch (((PSTATE_MSR *) &PstateMsr)->IddDiv) {
case 0:
IddDiv = 1000;
break;
case 1:
IddDiv = 100;
break;
case 2:
IddDiv = 10;
break;
default: // IddDiv = 3 is reserved. Use 10
ASSERT (FALSE);
IddDiv = 10;
break;
}
PciAddress.Address.Register = PW_CTL_MISC_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); // F3xE8
if (((POWER_CTRL_MISC_REGISTER *) &PciRegister)->PviMode == 1) {
*ProcIddMax = (UINT32) ((PSTATE_MSR *) &PstateMsr)->IddValue * IddDiv * CmpCap;
} else {
PciAddress.Address.Register = PRCT_INFO_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); // F3xE8
SinglePlaneNbIdd = ((PRODUCT_INFO_REGISTER *) &PciRegister)->SinglePlaneNbIdd;
SinglePlaneNbIdd <<= 1;
*ProcIddMax = ((UINT32) ((PSTATE_MSR *) &PstateMsr)->IddValue * IddDiv * CmpCap) - SinglePlaneNbIdd;
}
IsPstateEnabled = TRUE;
}
return IsPstateEnabled;
}
/*---------------------------------------------------------------------------------------*/
/**
* Returns whether or not BIOS is responsible for configuring the NB COFVID.
*
* @CpuServiceMethod{::F_CPU_IS_NBCOF_INIT_NEEDED}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] PciAddress The northbridge to query by pci base address.
* @param[out] NbVidUpdateAll Do all NbVids need to be updated
* @param[in] StdHeader Header for library and services
*
* @retval TRUE Perform northbridge frequency and voltage config.
* @retval FALSE Do not configure them.
*/
BOOLEAN
F10CommonRevCGetNbCofVidUpdate (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN PCI_ADDR *PciAddress,
OUT BOOLEAN *NbVidUpdateAll,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 ProductInfoRegister;
PciAddress->Address.Register = PRCT_INFO_REG;
PciAddress->Address.Function = FUNC_3;
LibAmdPciRead (AccessWidth32, *PciAddress, &ProductInfoRegister, StdHeader);
*NbVidUpdateAll = (BOOLEAN) (((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->NbVidUpdateAll == 1);
return (BOOLEAN) (((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->NbCofVidUpdate == 1);
}
/*---------------------------------------------------------------------------------------*/
/**
* Determines the NB clock on the desired node.
*
* @CpuServiceMethod{::F_CPU_GET_NB_FREQ}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] PciAddress The northbridge to query
* @param[out] FrequencyInMHz Northbridge clock frequency in MHz.
* @param[out] VoltageInuV Northbridge voltage in uV.
* @param[in] StdHeader Header for library and services
*
* @retval AGESA_SUCCESS Always succeeds.
*/
AGESA_STATUS
F10CommonRevCGetNbFrequency (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN PCI_ADDR *PciAddress,
OUT UINT32 *FrequencyInMHz,
OUT UINT32 *VoltageInuV,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 ProductInfoRegister;
UINT32 PciRegister;
UINT32 NbFid;
UINT32 NbVid;
UINT64 MsrRegister;
PciAddress->Address.Register = PRCT_INFO_REG;
PciAddress->Address.Function = FUNC_3;
LibAmdPciRead (AccessWidth32, *PciAddress, &ProductInfoRegister, StdHeader);
if ((((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->NbCofVidUpdate) == 0) {
PciAddress->Address.Register = CPTC0_REG;
LibAmdPciRead (AccessWidth32, *PciAddress, &PciRegister, StdHeader);
NbFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->NbFid;
LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
NbVid = (UINT32) ((COFVID_STS_MSR *) &MsrRegister)->CurNbVid;
} else {
NbFid = ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->SinglePlaneNbFid;
NbVid = ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->SinglePlaneNbVid;
PciAddress->Address.Register = PW_CTL_MISC_REG;
LibAmdPciRead (AccessWidth32, *PciAddress, &PciRegister, StdHeader);
if (((POWER_CTRL_MISC_REGISTER *) &PciRegister)->PviMode == 0) {
NbFid += ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->DualPlaneNbFidOff;
NbVid -= ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->DualPlaneNbVidOff;
}
}
*FrequencyInMHz = ((NbFid + 4) * 200);
*VoltageInuV = (1550000 - (12500 * NbVid));
return (AGESA_SUCCESS);
}
/*---------------------------------------------------------------------------------------*/
/**
* Is the Northbridge PState feature enabled?
*
* @CpuServiceMethod{::F_IS_NB_PSTATE_ENABLED}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
* @retval TRUE The NB PState feature is enabled.
* @retval FALSE The NB PState feature is not enabled.
*/
BOOLEAN
F10CommonRevCIsNbPstateEnabled (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 Core;
UINT32 Module;
UINT32 NbPstate;
UINT32 Socket;
PCI_ADDR PciAddress;
AGESA_STATUS IgnoredSts;
CPU_LOGICAL_ID LogicalId;
BOOLEAN Result;
Result = FALSE;
GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
if ((LogicalId.Revision & AMD_F10_C3) != 0) {
IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
PciAddress.Address.Function = FUNC_3;
PciAddress.Address.Register = 0x1F0;
LibAmdPciReadBits (PciAddress, 18, 16, &NbPstate, StdHeader);
if (NbPstate != 0) {
Result = TRUE;
}
}
return Result;
}
/*---------------------------------------------------------------------------------------*/
/**
* Get number of processor cores to be used in determining the brand string.
*
* @CpuServiceMethod{::F_CPU_NUMBER_OF_BRANDSTRING_CORES}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
* @return The number of cores to be used in brand string calculation.
*/
UINT8
F10CommonRevCGetNumberOfCoresForBrandstring (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 Socket;
UINT32 Module;
UINT32 Core;
UINT32 PciRegister;
PCI_ADDR PciAddress;
AGESA_STATUS IgnoredSts;
IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
PciAddress.Address.Function = FUNC_3;
PciAddress.Address.Register = NB_CAPS_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
return (UINT8) (((NB_CAPS_REGISTER *) &PciRegister)->CmpCapLo + 1);
}

105
src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c
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@ -1,105 +0,0 @@
/**
* @file
*
* AMD Family_10 RB Equivalence Table related data
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x10
* @e \$Revision: 6381 $ @e \$Date: 2008-06-15 17:26:25 -0500 (Sun, 15 Jun 2008) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuFamilyTranslation.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X10_REVC_RB_F10RBEQUIVALENCETABLE_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
STATIC CONST UINT16 ROMDATA CpuF10RbMicrocodeEquivalenceTable[] =
{
0x1040, 0x1040,
0x1041, 0x1041,
0x1042, 0x1041,
0x1043, 0x1043
};
/*---------------------------------------------------------------------------------------*/
/**
* Returns the appropriate microcode patch equivalent ID table.
*
* @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[out] RbEquivalenceTablePtr Points to the first entry in the table.
* @param[out] NumberOfElements Number of valid entries in the table.
* @param[in] StdHeader Header for library and services.
*
*/
VOID
GetF10RbMicrocodeEquivalenceTable (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **RbEquivalenceTablePtr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
*NumberOfElements = ((sizeof (CpuF10RbMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
*RbEquivalenceTablePtr = CpuF10RbMicrocodeEquivalenceTable;
}

115
src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbHtPhyTables.c
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@ -1,115 +0,0 @@
/**
* @file
*
* AMD Family_10 RB PCI tables with values as defined in BKDG
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/FAMILY/0x10
* @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "Table.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X10_REVC_RB_F10RBHTPHYTABLES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
// HT Phy T a b l e s
// -------------------------
STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10RbHtPhyRegisters[] =
{
// Erratum 354
// 0x40:0x48
{
HtPhyRangeRegister,
{
AMD_FAMILY_10, // CpuFamily
(AMD_F10_RB_C1) // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
HTPHY_LINKTYPE_SL0_HT3, //
0x40, 0x48, // Address
0x00000040, // regData
0x00000040, // regMask
}
},
// 0x50:0x58
{
HtPhyRangeRegister,
{
AMD_FAMILY_10, // CpuFamily
(AMD_F10_RB_C1) // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
HTPHY_LINKTYPE_SL1_HT3, //
0x50, 0x58, // Address
0x00000040, // regData
0x00000040, // regMask
}
},
};
CONST REGISTER_TABLE ROMDATA F10RbHtPhyRegisterTable = {
PrimaryCores,
(sizeof (F10RbHtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
F10RbHtPhyRegisters
};

109
src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbLogicalIdTables.c
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@ -1,109 +0,0 @@
/**
* @file
*
* AMD Family_10 RB Logical ID Table
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/FAMILY/0x10
* @e \$Revision: 6261 $ @e \$Date: 2008-06-04 17:38:17 -0500 (Wed, 04 Jun 2008) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X10_REVC_RB_F10RBLOGICALIDTABLES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
STATIC CONST CPU_LOGICAL_ID_XLAT ROMDATA CpuF10RbLogicalIdAndRevArray[] =
{
{
0x1040,
AMD_F10_RB_C0
},
{
0x1041,
AMD_F10_RB_C1
},
{
0x1042,
AMD_F10_RB_C2
},
{
0x1043,
AMD_F10_RB_C3
}
};
VOID
GetF10RbLogicalIdAndRev (
OUT CONST CPU_LOGICAL_ID_XLAT **RbIdPtr,
OUT UINT8 *NumberOfElements,
OUT UINT64 *LogicalFamily,
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
*NumberOfElements = (sizeof (CpuF10RbLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT));
*RbIdPtr = CpuF10RbLogicalIdAndRevArray;
*LogicalFamily = AMD_FAMILY_10_RB;
}
//CONST LOGICAL_ID_TABLE ROMDATA CpuF10RbLogicalIdAndRev =
//{
// (sizeof (CpuF10RbLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT)),
// (CPU_LOGICAL_ID_XLAT *) &CpuF10RbLogicalIdAndRevArray
//};

104
src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c
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@ -1,104 +0,0 @@
/**
* @file
*
* AMD Family_10 RB microcode patches
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x10
* @e \$Revision: 6049 $ @e \$Date: 2008-05-13 23:58:02 -0700 (Tue, 13 May 2008) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "cpuEarlyInit.h"
#include "cpuFamilyTranslation.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X10_REVC_RB_F10RBMICROCODEPATCHTABLES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
CONST MICROCODE_PATCHES ROMDATA *CpuF10RbMicroCodePatchArray[];
/*---------------------------------------------------------------------------------------*/
/**
* Returns a table containing the appropriate microcode patches.
*
* @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[out] RbUcodePtr Points to the first entry in the table.
* @param[out] NumberOfElements Number of valid entries in the table.
* @param[in] StdHeader Header for library and services.
*
*/
VOID
GetF10RbMicroCodePatchesStruct (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **RbUcodePtr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 NumberOfUcode;
for (NumberOfUcode = 0; CpuF10RbMicroCodePatchArray[NumberOfUcode] != 0; NumberOfUcode++) {
}
*NumberOfElements = NumberOfUcode;
*RbUcodePtr = &CpuF10RbMicroCodePatchArray[0];
}

115
src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbMsrTables.c
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@ -1,115 +0,0 @@
/**
* @file
*
* AMD Family_10 RB, MSR tables with values as defined in BKDG
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU
* @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "Table.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X10_REVC_RB_F10RBMSRTABLES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10RbMsrRegisters[] =
{
// M S R T a b l e s
// ----------------------
// MSR_DC_CFG (0xC0011022)
// bits[43:42] = 0
// Errata #326
{
MsrRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_RB_C0 // CpuRevision
},
AMD_PF_MULTI_LINK, // platformFeatures
{
MSR_DC_CFG, // MSR Address
0x0000000000000000, // OR Mask
0x00000C0000000000, // NAND Mask
}
},
// MSR_BU_CFG (0xC0011023)
// Erratum #309 BU_CFG[23]=1
{
MsrRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_RB_C0 // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
MSR_BU_CFG, // MSR Address
(1 << 23), // OR Mask
(1 << 23), // NAND Mask
}
}
};
CONST REGISTER_TABLE ROMDATA F10RbMsrRegisterTable = {
AllCores,
(sizeof (F10RbMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
(TABLE_ENTRY_FIELDS *) &F10RbMsrRegisters,
};

212
src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbPciTables.c
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@ -1,212 +0,0 @@
/**
* @file
*
* AMD Family_10 RB PCI tables with values as defined in BKDG
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/FAMILY/0x10
* @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
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* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
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* documentation and/or other materials provided with the distribution.
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* from this software without specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "Table.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X10_REVC_RB_F10RBPCITABLES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
// P C I T a b l e s
// ----------------------
STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10RbPciRegisters[] =
{
// Function 0
// F0x16C - Link Global Extended Control Register, Errata 351
// bit[15:13] ForceFullT0 = 0
// bit[5:0] T0Time = 0x14
{
PciRegister,
{
AMD_FAMILY_10, // CpuFamily
(AMD_F10_RB_C0 | AMD_F10_RB_C1 | AMD_F10_RB_C2) // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
0x00000014, // regData
0x0000E03F, // regMask
}
},
// F0x16C - Link Global Extended Control Register
// bit[7:6] InLnSt = 0x01
{
PciRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_RB_C3 // CpuRevision
},
AMD_PF_SINGLE_LINK, // platformFeatures
{
MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
0x00000040, // regData
0x000000C0, // regMask
}
},
// F0x170 - Link Extended Control Register - Link 0, sublink 0
// Errata 351 (only need to override single link case.)
// bit[8] LS2En = 0,
{
PciRegister,
{
AMD_FAMILY_10, // CpuFamily
(AMD_F10_RB_C0 | AMD_F10_RB_C1 | AMD_F10_RB_C2) // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
MAKE_SBDFO (0, 0, 24, FUNC_0, 0x170), // Address
0x00000000, // regData
0x00000100, // regMask
}
},
// F3xA0 - Power Control Miscellaneous
// bits[13:11] PllLockTime = 5
{
PciRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_RB_C0 // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0), // Address
0x00002800, // regData
0x00003800, // regMask
}
},
// F3xA0 - Power Control Miscellaneous
// bits[28] NbPstateForce = 1
{
PciRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_RB_C3 // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0), // Address
0x10000000, // regData
0x10000000, // regMask
}
},
// F3xDC - Clock Power Timing Control 2
// bits[14:12] NbsynPtrAdj = 6
{
PciRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_RB_ALL // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC), // Address
0x00006000, // regData
0x00007000, // regMask
}
},
// F3xDC - Clock Power Timing Control 2
// bits[14:12] NbsynPtrAdj = 5
{
PciRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_C0 // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC), // Address
0x00005000, // regData
0x00007000, // regMask
}
},
// F3xDC - Clock Power Timing Control 2
// bits[14:12] NbsynPtrAdj = 5
{
ProfileFixup,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_C3 // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
PERFORMANCE_NB_PSTATES_ENABLE, // PerformanceFeatures
MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC), // Address
0x00005000, // regData
0x00007000, // regMask
}
}
};
CONST REGISTER_TABLE ROMDATA F10RbPciRegisterTable = {
PrimaryCores,
(sizeof (F10RbPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
F10RbPciRegisters,
};

1037
src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c4.c
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