soc/amd/mendocino/acpi: remove RTC wake workaround

Commit 78ee4889dc ("soc/amd/cezanne/acpi: Add support for RTC
workaround") added a workaround for the Cezanne silicon. This was copied
to the Mendocino code, but from both the discussion in b:209705576 and
the referenced amd_pmc_verify_czn_rtc function in drivers/platform/x86/
amd/pmc.c that is only called if pdev->cpu_id == AMD_CPU_ID_CZN is true
Mendocino doesn't need that workaround, so remove it.

TEST=Running suspend_stress_test -c 5 on Chausie shows no errors

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7d0b35ef8cf88ff0b9bed8820b8da32c2058cc1b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72091
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/amd/mendocino/acpi/rtc_workaround.asl

@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* TODO: Check if this is still correct */
-
-/*
- * Workaround for RTC on Cezanne.
- * See https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/third_party/kernel/v5.10/drivers/platform/x86/amd-pmc.c;l=416;drc=54a96af06ae6851e4a02e8dd700de0d579ef7839
- */
-
-Scope (\_SB.PEP) {
-	Name (_PRW, Package () {
-		Package() {\_SB.GPIO, 0},
-		0x03
-	})
-}
-
-Scope (\_SB.GPIO) {
-	Name (_AEI, ResourceTemplate () {
-		GpioInt(Edge, ActiveHigh, ExclusiveAndWake, PullNone, 0x0000, "\\_SB.GPIO",,,,)
-		{
-			44 /* int_shdwsysalarmfire */
-		}
-	})
-
-	Method (_E2C, 0, Serialized) {
-		Notify (\_SB_.PEP, 0x02)
-	}
-}

src/soc/amd/mendocino/acpi/soc.asl

@@ -33,8 +33,6 @@ Scope(\_SB) {
 #include <soc/amd/common/acpi/dptc.asl>
 #endif
 
-#include "rtc_workaround.asl"
-
 /* Enable DPTC interface with AMD ALIB */
 External(\_SB.DPTC, MethodObj)