soc/intel/xeon_sp/gnr: Add dimm_slot configuration

Add sample DIMM slot configuration table for avenuecity CRB
and beechnutcity CRB. This table will be used to fill SMBIOS
type 17 table.

TEST=Boot on intel/avenuecity CRB
It will help to update Locator, Bank Locator and Asset Tag
with the value described in dimm_slot_config_table

Change-Id: I53556c02eb75204994a1bcb42eccb940e83bd532
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83326
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/intel/avenuecity_crb/Makefile.mk

@@ -2,5 +2,7 @@
 
 bootblock-y += bootblock.c
 romstage-y += romstage.c
+romstage-y += config/dimm_slot.c
 romstage-y += config/iio.c
+ramstage-y += config/dimm_slot.c
 ramstage-y += ramstage.c

src/mainboard/intel/avenuecity_crb/config/dimm_slot.c

@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <commonlib/helpers.h>
+#include <soc/dimm_slot.h>
+
+/*
+ * TODO: add the rest of DIMM slots
+ */
+static const struct dimm_slot_config dimm_slot_config_table[] = {
+	/* socket, channel, dimm, dev_locator, bank_locator, asset_tag */
+	{0, 0, 0, "CPU0_DIMM_A1", "BANK 0", "CPU0_DIMM_A1_AssetTag"},
+};
+
+const struct dimm_slot_config *get_dimm_slot_config_table(int *size)
+{
+	*size = ARRAY_SIZE(dimm_slot_config_table);
+	return dimm_slot_config_table;
+}

src/mainboard/intel/avenuecity_crb/ramstage.c

@@ -1,8 +1,39 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <soc/dimm_slot.h>
 #include <soc/ramstage.h>
 
 void mainboard_silicon_init_params(FSPS_UPD *params)
 {
 
 }
+
+void smbios_fill_dimm_locator(const struct dimm_info *dimm, struct smbios_type17 *t)
+{
+	int size;
+	const struct dimm_slot_config *dimm_slot_config_table = get_dimm_slot_config_table(&size);
+
+	for (int i = 0; i < size; i++) {
+		if (DIMM_SLOT_EQUAL(dimm_slot_config_table[i],
+		    dimm->soc_num, dimm->channel_num, dimm->dimm_num)) {
+			const char *locator = dimm_slot_config_table[i].dev_locator;
+			t->device_locator = smbios_add_string(t->eos, locator);
+			locator = dimm_slot_config_table[i].bank_locator;
+			t->bank_locator = smbios_add_string(t->eos, locator);
+		}
+	}
+}
+
+void smbios_fill_dimm_asset_tag(const struct dimm_info *dimm, struct smbios_type17 *t)
+{
+	int size;
+	const struct dimm_slot_config *dimm_slot_config_table = get_dimm_slot_config_table(&size);
+
+	for (int i = 0; i < size; i++) {
+		if (DIMM_SLOT_EQUAL(dimm_slot_config_table[i],
+		    dimm->soc_num, dimm->channel_num, dimm->dimm_num)) {
+			const char *asset_tag = dimm_slot_config_table[i].asset_tag;
+			t->asset_tag = smbios_add_string(t->eos, asset_tag);
+		}
+	}
+}

src/mainboard/intel/avenuecity_crb/romstage.c

@@ -7,6 +7,7 @@
 #include <fmap_config.h>
 #include <device/device.h>
 #include <soc/ddr.h>
+#include <soc/dimm_slot.h>
 #include <soc/iio.h>
 #include <soc/romstage.h>
 
@@ -43,6 +44,13 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 
 bool mainboard_dimm_slot_exists(uint8_t socket, uint8_t channel, uint8_t dimm)
 {
-	//TODO: not implemented yet
+	int size;
+	const struct dimm_slot_config *dimm_slot_config_table = get_dimm_slot_config_table(&size);
+
+	for (int i = 0; i < size; i++) {
+		if (DIMM_SLOT_EQUAL(dimm_slot_config_table[i], socket, channel, dimm))
+			return true;
+	}
+
 	return false;
 }

src/mainboard/intel/beechnutcity_crb/Makefile.mk

@@ -2,5 +2,7 @@
 
 bootblock-y += bootblock.c
 romstage-y += romstage.c
+romstage-y += config/dimm_slot.c
 romstage-y += config/iio.c
+ramstage-y += config/dimm_slot.c
 ramstage-y += ramstage.c

src/mainboard/intel/beechnutcity_crb/config/dimm_slot.c

@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <commonlib/helpers.h>
+#include <soc/dimm_slot.h>
+
+/*
+ * TODO: add the rest of DIMM slots
+ */
+static const struct dimm_slot_config dimm_slot_config_table[] = {
+	/* socket, channel, dimm, dev_locator, bank_locator, asset_tag */
+	{0, 0, 0, "CPU0_DIMM_A1", "BANK 0", "CPU0_DIMM_A1_AssetTag"},
+};
+
+const struct dimm_slot_config *get_dimm_slot_config_table(int *size)
+{
+	*size = ARRAY_SIZE(dimm_slot_config_table);
+	return dimm_slot_config_table;
+}

src/mainboard/intel/beechnutcity_crb/ramstage.c

@@ -1,8 +1,39 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <soc/dimm_slot.h>
 #include <soc/ramstage.h>
 
 void mainboard_silicon_init_params(FSPS_UPD *params)
 {
 
 }
+
+void smbios_fill_dimm_locator(const struct dimm_info *dimm, struct smbios_type17 *t)
+{
+	int size;
+	const struct dimm_slot_config *dimm_slot_config_table = get_dimm_slot_config_table(&size);
+
+	for (int i = 0; i < size; i++) {
+		if (DIMM_SLOT_EQUAL(dimm_slot_config_table[i],
+		    dimm->soc_num, dimm->channel_num, dimm->dimm_num)) {
+			const char *locator = dimm_slot_config_table[i].dev_locator;
+			t->device_locator = smbios_add_string(t->eos, locator);
+			locator = dimm_slot_config_table[i].bank_locator;
+			t->bank_locator = smbios_add_string(t->eos, locator);
+		}
+	}
+}
+
+void smbios_fill_dimm_asset_tag(const struct dimm_info *dimm, struct smbios_type17 *t)
+{
+	int size;
+	const struct dimm_slot_config *dimm_slot_config_table = get_dimm_slot_config_table(&size);
+
+	for (int i = 0; i < size; i++) {
+		if (DIMM_SLOT_EQUAL(dimm_slot_config_table[i],
+		    dimm->soc_num, dimm->channel_num, dimm->dimm_num)) {
+			const char *asset_tag = dimm_slot_config_table[i].asset_tag;
+			t->asset_tag = smbios_add_string(t->eos, asset_tag);
+		}
+	}
+}

src/mainboard/intel/beechnutcity_crb/romstage.c

@@ -7,6 +7,7 @@
 #include <fmap_config.h>
 #include <device/device.h>
 #include <soc/ddr.h>
+#include <soc/dimm_slot.h>
 #include <soc/iio.h>
 #include <soc/romstage.h>
 
@@ -43,6 +44,13 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 
 bool mainboard_dimm_slot_exists(uint8_t socket, uint8_t channel, uint8_t dimm)
 {
-	//TODO: not implemented yet
+	int size;
+	const struct dimm_slot_config *dimm_slot_config_table = get_dimm_slot_config_table(&size);
+
+	for (int i = 0; i < size; i++) {
+		if (DIMM_SLOT_EQUAL(dimm_slot_config_table[i], socket, channel, dimm))
+			return true;
+	}
+
 	return false;
 }

src/soc/intel/xeon_sp/gnr/include/soc/dimm_slot.h

@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef _SOC_DIMM_SLOT_H_
+#define _SOC_DIMM_SLOT_H_
+
+#include <stdint.h>
+
+struct dimm_slot_config {
+	uint8_t socket;
+	uint8_t channel;
+	uint8_t dimm;
+	/*
+	 * Refer to DSP0134_3.6.0.pdf
+	 * page 103 'Device Locator', 'Bank Locator' and 'Asset Tag'.
+	 */
+	const char *dev_locator;
+	const char *bank_locator;
+	const char *asset_tag;
+};
+
+#define DIMM_SLOT_EQUAL(dimm_slot, s, c, d) (\
+	(dimm_slot.socket == s) &&\
+	(dimm_slot.channel == c) &&\
+	(dimm_slot.dimm == d))
+
+const struct dimm_slot_config *get_dimm_slot_config_table(int *size);
+
+#endif /* _SOC_DIMM_SLOT_H_ */